Abstract: An adaptive bandwidth phase locked loop (PLL) includes a phase frequency detector configured to generate a comparison pulse having a pulse-width and sign corresponding to a difference between a reference frequency and a first frequency. A pulse-voltage converter is configured to generate a control voltage corresponding to the comparison pulse. An oscillator is configured to generate the output frequency corresponding to the control voltage.

Abstract: The present invention provides a phase comparison signal processing circuit which processes an output rectangular wave signal of a digital phase comparator of a PLL, expands a pullable-in frequency width of the PLL and shortens a synchronization time. The phase comparison signal processing circuit includes a first signal path which is parallel-connected between a voltage shifter for converting a rectangular wave signal to a bipolar signal and an output terminal and comprises a rectifying circuit, an integration holding circuit, a differentiation circuit, a gate circuit, a voltage hold circuit and a common addition circuit, a second signal path comprising a rectifying circuit, an integration holding circuit, a differentiation circuit, a gate circuit, a voltage hold circuit and the addition circuit, and a control signal generator for individually controlling the integration holding circuits and the gate circuits of the first and second signal paths.

Abstract: A power on reset circuit initializes at power on a digital integrated circuit, and includes a first power on reset signal generator powered by an external power supply voltage and generates a first power on reset signal. A reference voltage generator is powered by the external power supply voltage, and is enabled by the first power on reset signal for generating a stable compensating reference voltage. A voltage down converter circuit receives the reference voltage and is enabled by the first power on reset signal, and converts the external applied power supply voltage to a stable regulated internal supply voltage. A second power on reset signal generator circuit receives the regulated internal supply voltage, and is enabled by the first power on reset signal for generating a second power on reset signal for core parts of the digital integrated circuit for initializing them at power on.

Abstract: A latch circuit includes first, second, and third inverter circuits, a switching element, and a capacitor element. The first inverter circuit and the second inverter circuit are cross-connected to each other. The third inverter circuit logically inverts an output from the first inverter circuit. The switching element is connected between the output terminal of the second inverter circuit and the output terminal of the third inverter circuit. The capacitor element is connected between the output terminal of the third inverter circuit and a reference voltage node.

Abstract: A design structure embodied in a machine readable medium includes information for designing, manufacturing and/or testing a programmable phase frequency divider circuit implemented in CMOS technology for space applications. The programmable phase frequency divider consists of three radiation hardened D-type flip flops and combinational logic circuits to provide the feedback controls that allow programmable frequency division ratios from 1 to 8. The radiation hardened D-type flip flop circuits are designed to keep on running properly at GHz frequencies even after a single event upset (SEU) hit. The novel D-type flip flop circuits each have two pairs of complementary inputs and outputs to mitigate SEU's. The combinational logic circuits are designed to utilize the complementary outputs in such a way that only one of the four dual complementary inputs to any D-type flip flop gets flipped at most after an SEU hit.

Abstract: A digitally programmable hysteresis comparator a includes digitally programmable variable resistor. One or more control bits are operable to modify the resistance of the variable resistor, and such modification is operable to modify the hysteresis width of the comparator.

Abstract: An interface circuit includes a variable delay circuit and a delay adjustment circuit to automatically detect a data valid window of a DQ signal and adjust an optimum delay amount of a DQS signal, and a fixed delay circuit to delay the DQ signal by a delay amount tFIXDLY satisfying tFIXDLY>tMINDLY+tSKEW?tSETUP where a minimum delay amount in the variable delay circuit is tMINDLY, a skew between the DQ signal and the DQS signal is tSKEW, and a setup time of the DQ signal is tSETUP.

Abstract: A delay adjustor for adjusting the delay time of a signal, the adjustor comprising: a first capacitance unit and a variable capacitance unit serially coupled to the first capacitor wherein the capacitance of the variable capacitance unit is adjusted according to a first control signal and the variable capacitance unit comprises a plurality of second capacitors and at least a first switch coupled to the at least one capacitor of the second capacitors.

Abstract: A delay circuit comprises: N-stage circuits having a first circuit to an N-th circuit connected in cascade, the input signal being input to the first circuit and a transmission signal delayed by a (k?1)-stage (where 2?k?N) circuit is input to a k-th circuit for sequential transmission; a common delay circuit for delaying the transmission signal of each stage commonly; and path control means for controlling a path of an i-th (1?i?N) circuit so that during a predetermined period from an edge timing of a signal input to the i-th circuit to an edge timing of the transmission signal delayed by the common delay circuit through the i-th circuit, the common delay circuit is connected to a signal path, and during the other period, the common delay circuit is disconnected from the signal path, wherein the delayed signal passing through the common delay circuit N times is generated.

Abstract: There is provided a delay circuit including a first delay element, a second delay element, and an initializing section that measures a delay amount generated by the first delay element with respect to each delay setting value and initializes the first delay element. The initializing section includes: a first loop path that inputs an output signal of the first delay element into the first delay element; a second loop path that inputs an output signal of the second delay element into the second delay element; a first measuring section that sequentially sets delay setting values mutually different from the delay setting value in the first delay element and sequentially measures delay amounts in the first delay element; a second measuring section that measures a delay amount in the second delay element; and a delay amount computing section that corrects a delay amount measured by the first measuring section.

Abstract: A circuit includes a first variable resistor having a resistance which is variable in response to a resistance control signal. A resistance control circuit includes a first current source circuit for supplying a first current through a reference resistor. A second current source circuit supplies a second current through the first variable resistor. In operational amplifier has a first input coupled to a first conductor connecting the first current source to the reference resistor, a second input coupled to a second conductor connecting the current source to the first variable resistor, and an output applying the first resistance control signal to a control terminal of the first variable resistor, to force the resistance of the first variable resistor to be equal to a resistance of the reference resistor. The resistance of a second variable resistor of an attenuator is controlled in response to the resistance control signal.

Abstract: In all electronic products, the voltage supply circuit is an essential component for providing a stable supply voltage into the application device. The present invention provides a multi-level voltage supply circuit for solving some problems existing in the application device, in which the multi-level voltage supply circuit includes a first voltage drop component, a second voltage drop component, and a control module. When the first voltage drop component is controlled by the control module in the conducting state, the output voltage is substantially equal to the input voltage minus the first voltage drop. When the first voltage drop component is controlled by the control module in the non-conducting state, the output voltage is substantially equal to the input voltage minus the second voltage drop.

Abstract: An amplifier circuit for regenerating complementary digital signals which comprises a differential pair of transistors (T5, T6). This circuit also comprises a pair of push-pull amplifiers (12a, 12b) which consists of a first and a second push-pull amplifier having a first and a second low input (L, Lb) which are coupled to a source for the input signal and its complement, respectively, a first and a second high input (H, Hb) which are coupled to a source of the complementary input signal and to a source of the input signal, respectively, a first and a second output (13a, 13b) which supply, under a low impedance and during switching, brief and intense current pulses of said complementary input signals of increased amplitude in order to apply these pulses to the first second control inputs (1a, 1b) of the first and second transistors (T5, T6) of the differential pair, respectively.

Abstract: A level shifter includes a level shifting circuit shifting a level of a boosted signal input through an input terminal connected to the level shifter and outputting the boosted signal at a new level, and a boosting circuit receiving an input signal, boosting a voltage of the input signal to generate the boosted signal, and providing the boosted signal to the input terminal.

Abstract: An input/output device includes: a level shifter configured to convert an input signal of a first voltage into an output signal of a second voltage; and an output driver configured to operate in response to the output signal. The level shifter is configured to generate the output signal with a predetermined level when the first voltage is interrupted to supply.

Abstract: A semiconductor integrated circuit includes an oscillation circuit outputting an oscillation signal, and a switch circuit switching whether the oscillation signal received from the oscillation circuit is to be output to the outside or not.

Abstract: A selection circuit and method. The selection circuit comprises a logic circuit, an array of sub-circuits and a switching circuit electrically coupled to each other. The selection circuit is subjected to a first operating condition. The switching circuit selects a group of sub-circuits from the array. The selection circuit generates a first frequency. The selection circuit is subjected to a second operating condition that is different from the first operating condition and generates a second frequency. A first frequency differential between the first frequency and the second frequency is compared to a predetermined frequency differential to determine if the first frequency differential is about equal to the predetermined frequency differential.

Abstract: To provide an output control circuit having a small circuit scale that still operates stably at high speed, an output control circuit includes a first inverter and a second inverter, connected in series for outputting signals at an inverted voltage level of an input signal, a first output unit, for which output is controlled based on a voltage level of a signal output by the second inverter, a third inverter, an output of which is connected to an output of the first inverter, for outputting a signal at an inverted voltage level of a signal output by the second inverter, and a second output unit for which output is controlled based on a voltage level of a signal output by the first inverter and a voltage level of a signal output by the third inverter.

Abstract: An embodiment of an electronic device having a plurality of operative parameters is provided. The electronic device includes means for applying a plurality of trimming actions to each parameter for causing a corresponding correction of the parameter, for at least one reference parameter, means for measuring the reference parameter responsive to the application of at least part of the trimming actions to select one of the trimming actions providing a target value of the reference parameter, and means for forcing the application of the selected trimming action for the reference parameter.

Abstract: A monolithically integratable circuit arrangement is provided, which has at least one inductor, formed as a conductor loop, and at least one capacitor, connected to the conductor loop. According to the invention, the circuit arrangement comprises (a) at least one first conductor loop placed in at least one first metallization level and having a first DC terminal for applying a first DC potential, (b) at least one second conductor loop placed in at least one second metallization level and having a second DC terminal for applying a second DC potential, (c) at least one metal-isolator-metal capacitor with a capacitor plate, which is placed in a third metallization level between the first and second metallization level, and (d) at least one metallic connecting means placed between the capacitor plate and the first conductor loop, said means which connects the capacitor plate in an electrically conducting manner to the first conductor loop.

Abstract: An integrated circuit device having at least one fuse capable of being blown in order to provide measurements of fuse current-voltage characteristics is provided. The integrated circuit device also provides at least one pulse generation circuit associated with the fuse and capable of generating a pulse to blow the fuse through one or more DC input signals.

Abstract: A superconducting switching amplifier embodying the invention includes superconductive devices responsive to input/control signals for clamping the output of the amplifier to a first voltage or to a second voltage. The amplifier includes a first set of superconducting devices serially connected between a first voltage line and an output terminal and a second set of superconducting devices serially connected between the output terminal and a second voltage line. The first set and the second set of devices are operated in a complementary fashion in response to control signals. When one of the first and second sets is driven to a superconducting (zero resistance) state the other set is driven to a resistive state. In accordance with the invention, the devices of each set are laid out in a pattern and driven in a manner to enable all the devices of each set to be driven to a selected state at substantially the same time.

Abstract: Disclosed is a bolometer infrared imaging device including a plural number of readout circuits, each comprising a bias circuit that includes a bias transistor that supplies a constant voltage to a bolometer device, a bias cancellation circuit that includes a canceller transistor that removes offset current component of the bolometer device and an integrating operational amplifier that integrates the difference current between the current flowing in the bias transistor and that flowing in the canceller transistor. The bias circuit includes a source follower circuit that receives a first input voltage and supplies an output voltage to the gate of the bias transistor. The bias cancellation circuit includes a source follower circuit that receives a second input voltage and supplies an output voltage to the gate of the canceller transistor.

Abstract: An electronic circuit device includes a negative resistance generating circuit, a second transistor and a path. The negative resistance generating circuit has a first transistor having a control terminal coupled to a resonator. The second transistor has a control terminal coupled to an output terminal of the first transistor and has an output terminal coupled to a DC bias terminal. The path is coupled to between the DC bias terminal and an output terminal of the first transistor through the second transistor and provides a bias to the first transistor.

Abstract: A power supply circuit is provided which is capable of preventing a drop in an output voltage of the power supply circuit used as a DC/DC converter made up of single and conductive type (n-type or p-type) MOS transistors and of improving efficiency. Since a control voltage having an amplitude [2×VDD] is applied from a level shift circuit to a charge-pump circuit, even when potentials at nodes becomes a level [2×VDD], pMOS transistors are kept in an OFF state, thereby preventing leakage of currents from pMOS transistors. This avoids a drop in an DC output voltage. As inputs to the level shift circuits, potentials at nodes of the charge-pump circuit are used and, therefore, even if potentials at nodes of the level shift circuits are high, pMOS transistors are kept in an OFF state.

Abstract: Techniques pertaining to a circuit architecture capable of controlling a current source to a predefined precision are disclosed. According to one aspect of the present invention, an automatic trimming circuit is proposed to automatically trim a current generated from a current generator or circuit in accordance with a reference current. The automatic trimming circuit includes a comparator, an ADC and a register. The comparator that may be implemented as a subtractor finds a difference between a generated current and a reference current. The difference is then digitized to an n-bit precision. A digital representation of the difference is then kept in a register and used subsequently correct or modify the generated current to produce a precisely controlled current.

Abstract: A semiconductor device includes a memory cell to and from which data is written and read in accordance with voltage supplied, a power supply circuit generating the voltage supplied to the memory cell, a microcomputer, an external terminal, a surge protection circuit clamping at a predetermined voltage value a voltage supplied to the external terminal, and a first switch circuit switching to output to one of the power supply circuit and the microcomputer a voltage having passed through the surge protection circuit. The power supply circuit includes a voltage conversion circuit changing the magnitude of a voltage received from the first switch circuit, and a second switch circuit switching to supply the memory cell with one of the voltage received from the first switch circuit and the voltage changed in magnitude.

Abstract: A circuit that can avoid drops in power supply and heat generation and save on manufacturing costs with no need of external controls are configured such that: a switching transformer has a terminal that produces an output of 22V at power-on and an output of 8V during standby and a terminal that produces an output of 10V at power-on and an output of 3V during standby; the output of 22V or 8V is lowered to 5V by a regulator IC1 and applied (input) to a regulator IC2; an input of 10V or 3V is produced at the regulator IC2; at power-on, the regulator IC2 lowers 10V to 3.3V and supplies the lowered 3.3V to the inverter circuit 10f, and during standby, a regulator IC lowers 8V to 3.3V and supplies the lowered 3.3V to the inverter circuit 10f.

Abstract: A balance compensation circuit for multi-power-output voltage is provided. The voltage balance compensation circuit comprises a ground terminal; a first output terminal providing a first output voltage; a first capacitor electrically connected between the first output terminal and the ground terminal and filtering the first output voltage; a second output terminal providing a second output voltage; a second capacitor electrically connected between the second output terminal and the ground terminal and filtering the second output voltage; a diode electrically connected between the first and the second output terminals and modulating a voltage difference between the first and the second output voltages by using a forward bias thereof; and a resistor electrically connected between the first and the second output terminals, serially connected to the diode, and having a resistance for assisting the modulation of the diode.

Abstract: A master bias current generating circuit includes a current source, a first reference leg, and a second reference leg. The first reference leg includes a first transistor having a first size parameter coupled to the current source and a first diode having a second size parameter coupled to the first transistor. The second reference leg includes a second transistor having a third size parameter less than the first size parameter coupled to the current source and a second diode having a fourth size parameter greater than the second size parameter coupled to the second transistor.

Abstract: A constant current circuit includes a first current mirror composed of a first transistor formed on a first current path and a second transistor formed on a second current path, a second current mirror composed of a third transistor formed on the first current path and a fourth transistor formed on the second current path, a first diode formed on the first current path, a second diode formed on the second current path, a resistor formed on the second current path, a variable resistance element connected with the first current path and with the second current path, and a feedback unit to control a resistance value of the variable resistance element based on a current flowing through the second current path.

Abstract: A sensor circuit has: a sensor portion that obtains, as an electrical signal, information on an object to be measured or detected; and a control circuit that controls the operation of the sensor portion. The control circuit receives a start input signal inputted thereto from outside for making the sensor portion operate only for a given duration after the start input signal is inputted thereto. With this configuration, it is possible to reduce the current consumption by arbitrarily controlling a period of an intermittent operation of the sensor circuit.

Abstract: A system, circuit, and method of canceling DC offset errors in cascaded amplifiers comprises arranging a plurality of any of analog voltage and analog current amplifier stages in any of cascaded and parallel configurations; operatively connecting a feedback comparator and digital logic in a feedback path around a given amplifier, wherein the digital logic comprises a finite state machine implementing an adaptive search algorithm comprising fixed switching and modulated switching; operatively connecting a switch at a differential input of the amplifier to short both input terminals of the amplifier; performing fixed switching on binary weighted elements generating discrete analog steps used to vary any of DC offset voltage and current at the input of the amplifier; and performing modulated switching on at least one lower least significant bit (LSB) of all bits used to vary the any of the DC offset voltage and current.

Abstract: An advanced balanced RF power amplifier circuit is provided. The RF power amplifier has a pair of RF amplification paths constructed to efficiently operate in a high-power mode. When instructed to operate in a low-power mode, one of the amplification paths is deactivated, and optionally, an impedance device is also set to operate at a low-power impedance value. With only one path operating in low-power mode, the network RF topology has changed from the topology of the high-power mode. This new topology provides increased impedance on the active RF amplification path as compared to when both RF amplification paths were active. This increased impedance causes the RF power amplifier to operate more efficiently in its low-power mode.

Abstract: An auto gain control circuit comprises a first peak detector, a variable gain amplifier, a second peak detector, a multiplexer and a controller. The first peak detector detects peaks of an input signal to generate a first peak signal. The variable gain amplifier amplifies the input signal to generate an output signal according to a control signal. The second peak detector detects peaks of the output signal to generate a second peak signal. The multiplexer selectively outputs the first peak signal or the second peak signal according to a first control signal. The controller generates the control signal according to the second peak signal and the first peak signal or according to the second peak signal and the reference voltage.

Abstract: The invention generally relates to stabilizing an MRI power delivery system. In one aspect, a stabilization module that is in electrical communication with the MRI power delivery system is provided. The stabilization module includes a closed loop control system. The closed loop control system is used to modify the at least one characteristic of the input signal. The modified input signal is provided to the MRI power delivery system.

Abstract: In a semiconductor device such as a high-frequency power amplifier module, a plurality of amplifying means are formed on a semiconductor chip which is mounted on a main surface of a wiring substrate, and electrodes of the semiconductor chip are electrically connected by wires to electrodes of the wiring substrate. In order to make the high-frequency power amplifier module small in size, a substrate-side bonding electrode electrically connected to a wire set at a fixed reference electric potential is place at a location farther from a side of the semiconductor chip than a substrate-side output electrode electrically connected to an output wire. A substrate-side input electrode electrically connected to an input wire is located at a distance from the side of the semiconductor chip about equal to the distance from the side of the semiconductor chip to the substrate-side output electrode, or at a location farther from the side of the semiconductor chip than the substrate-side bonding electrode is.

Abstract: A common-mode feedback circuit is provided. An amplifier with a common-mode feedback circuit is compensated by adding a compensating unit so that the amplifier totally has two poles and one zero in its frequency response. Accordingly, the gain of the amplifier is not sacrificed, and both the stability and the phase margin of the circuit are improved.

Abstract: A network device comprises an interface coupling an electronic device to a differential pair of signal lines, and an active common mode suppression circuit coupled to the interface in parallel to differential signal lines of the electronic device.

Abstract: Provided is a linearization apparatus of a triode region type operational transconductance amplifier that can provide a wide linear input range even when a differential pair input transistor having a short channel length is used at a low power supply voltage. The linearization apparatus of the triode region type operational transconductance amplifier includes: a first transconductor unit for receiving differential pair input voltages through differential pair input transistors and generating a basic transconductance; and a second transconductor unit for receiving the same differential pair input voltages, generating distortion transconductances, and overlapping the basic transconductace with the distortion transconductance for extending a linear range of a final transconductance.

Abstract: A circuit arrangement includes a signal processing unit and a regulation unit. The signal processing unit processes an input signal to form an analog output signal. The regulation unit is coupled to the signal processing unit in order to produce a digital regulation signal as a function of the analog output signal for regulation of the analog output signal.

Abstract: A method and apparatus is used to provide DC stabilization and noise reduction in a multistage power amplifier. The invention uses various feedback techniques to stabilize DC levels, which helps to reduce noise. The invention also uses other techniques to reduce noise, and to reduce the noise transfer function in a power amplifier.

Abstract: A bias circuit that supplies bias voltage or bias current to one end of a transmission line includes an inductor that prohibits a high frequency component of a baseband signal transmitted on the transmission line and passes a frequency component near direct current of the baseband signal, and an impedance-decrease prevention element that prevents impedance from decreasing, when viewed from the transmission line, that is produced due to a resonance between a parasitic capacitance generated due to the inductor and an inductance of the inductor.

Abstract: A circuit for a power amplifier includes a main amplifier stage having an operational amplifier (110), a buffer NPN transistor (126) and an NPN transistor (127) connected in a totem pole configuration, and a buffer PNP transistor (133) and a PNP transistor connected in a totem pole configuration. The transistors regulate the voltage to the components directly connected to the operational amplifier (110 ). A sampling resistor (137) located between a speaker (140) and an output of the power amplifier measures the current. The sampling resistor (137) is inside a negative feedback loop so that an output resistance will be near zero. A protection circuit includes a high common mode rejection difference amplifier that level shifts the sampling resistor voltage to a ground reference voltage. A precision rectifier full wave rectifies the current signal so that the current signal can he compared to a maximum current.

Abstract: Various embodiments of a two-stage low noise amplifier (LNA) having a gain that can be adjusted without varying input its impedance are disclosed. For example, in an illustrative embodiment, an exemplary low noise amplifier can include an input stage that includes a first transistor, and an output stage that includes a second transistor. The output of the input stage can have an optional stabilizing network. The output stage is coupled to the input stage and employs a shunt-feedback configuration.

Abstract: An oscillator provides a reference signal having a phase. A tunable reactive circuit, including an induction coil, is driven by the fixed frequency reference signal of the oscillator with coil adapted to be positioned adjacent the specimen to generate an oscillating signal corresponding to the condition of the specimen. The tunable reactive circuit provides an output signal having a parameter indicative of the condition of the specimen. A resonant control circuit compares the reference signal to the oscillating signal and provides to the tunable reactive circuit a resonance control signal representative of the comparison. The resonance control signal tunes the tunable reactive circuit, which may be a series RLC circuit, so that the frequency of the oscillating signal is substantially constant.

Abstract: Disclosed are embodiments of a phase control circuit with an analog phase controller having first and/or second order integration.

Abstract: A frequency tuning method for a voltage controlled oscillator includes outputting a first frequency selected from 2n discrete frequencies included in a frequency tuning range of the voltage controlled oscillator based on a predetermined control voltage and an n-bit control code during coarse tuning; outputting a third frequency corresponding to an average of the first frequency and a second frequency, that is, ½ of a code interval in response to the predetermined control voltage, the n-bit control code, and a control bit; and locking an output frequency of the voltage controlled oscillator to a reference frequency based on an analog control voltage and the third frequency during fine tuning. The second frequency is adjacent to the first frequency amoung the 2n discrete frequencies and the third frequency is used as an initial frequency in the fine tuning.

Abstract: Preferred embodiments of the present invention provide systems and methods that automatically correct the desired on-time of switching elements as the resonant frequency changes, so as to maintain the correct proportional value.

Abstract: A configurable ring oscillator is operated in a first configuration so that an oscillating signal passes from a first node to a second node through a first signal path. A first measurement of an operational characteristic is made. The ring oscillator is operated in a second configuration where an oscillating signal passes from the first node to the second node through a second signal path. A second measurement is made. The first and second measurements are used to determine a circuit simulator parameter. If the first path has little interconnect and the second path has substantial interconnect, then the effect on circuit operation due to interconnect loading can be isolated from the effects on circuit operation due to variations in transistor performance. If the first and second paths are laid out to be identical, then the first and second measurements are usable to determine a circuit simulator mismatch parameter.