Abstract: The invention relates to a magnetic resonance imaging (MRI) apparatus comprising an electrical coil system (17) for transmitting and receiving a radio-frequent (RF) magnetic field from an examination volume (3) of the MRI apparatus. The electrical coil system (17) comprises at least one surface coil (35) which substantially extends in a plane. The surface coil serves for transmitting and/or receiving an RF magnetic field which is substantially oriented perpendicular to the plane of the surface coil (35). The surface coil (35) has a main coil axis (37). When the MRI apparatus is in use the main coil axis (37) extends substantially parallel to a main magnetic field in the examination volume (3) of the MRI apparatus. On both sides of the main coil axis (37) the surface coil (35) comprises an electrically conducting element (39) which extends substantially parallel to the main coil axis (37).

Abstract: A radiofrequency (RF) resonator for magnetic resonance analysis, the RF resonator comprising: (a) at least two conductive elements, each having a first curvature along a direction perpendicular to a longitudinal axis, the at least two conductive elements being spaced along the longitudinal axis, so that when an RF current flows within the at least two conductive elements in a direction of the longitudinal axis, a substantially homogenous RF magnetic field, directed perpendicular to the longitudinal axis, is produced in a volume defined between the at least two conductive elements.

Abstract: Metal detectors include a sense coil coupled to an analog to digital converter that produces a numeric representation of an electrical signal associated with a conductive object situated in an active region of a sense coil. The numeric representation is processed to obtain a noise contribution associated with random noise, fixed pattern noise, and/or thermal drift. The noise is subtracted from the numeric representation to produce a numeric difference. The numeric difference includes contributions associated with conductive objects located in a sense volume defined by the sense coil. The numeric difference (or the numeric representation) can be digitally processed with, for example, a matched filter to enhance the conductive object contribution. The matched filter can be based on a measured sense coil speed or can be based on typical sense coil speeds.

Abstract: Misalignment of the transmitter and receiver coils of an induction logging tool is determined by positioning the logging tool with a coil axially encompassing the transmitter coil and/or the receiver coil, and activating the transmitter at a plurality of rotational angles. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.

Abstract: The present invention provides an assembled battery total voltage detection and leak detection apparatus which is reduced in size and is reduced in manufacturing costs. Detection of a total voltage is performed at a measurement time of a total voltage of an assembled battery 1 by connecting an output of a positive electrode resistance voltage dividing circuit composed of resistors 9 and 10 to + input of a differential amplifier 20 and connecting an output of a negative electrode resistance voltage dividing circuit composed of resistors 12 and 11 to ? input of the amplifier 20, and it performs leak detection at a leak detection time by connecting an output of a positive electrode resistance voltage dividing circuit to + input of the amplifier 20 and connecting + input of the amplifier 20 to the minus input of the differential amplifier 20 to measure an output voltage of the amplifier 20.

Abstract: A battery pack is disclosed. The battery pack includes at least one battery, a switch section, a measurement section, and a deterioration level calculation section. The switch section turns on and off charging to the battery. The measurement section measures an open circuit voltage of the battery. The deterioration level calculation section calculates the deterioration level of the battery based on the open circuit voltage measured by the measurement section after the switch section has repeatedly turned on and off the charging 10 times or more.

Abstract: A battery control device 1 has an electric circuit control unit 6 controlling a power supply; a voltage measuring unit 7 measuring a voltage; a current measuring unit 8 measuring an electric current; and a power source control unit 9, wherein the power source control unit 9 measures a first voltage defined as the voltage of the battery 4 and a first current defined as the current of the battery 4 in a state where the battery 4 supplies electric power to the load 3, measures a second voltage defined as the voltage of the battery 4 in a state where the supply of the electric power to the load 3 from the battery 4 is cut off, and calculates internal impedance of the battery 4 by dividing a value, obtained in a way that subtracts the first voltage from the second voltage, by the first current.

Abstract: A test apparatus includes lower and upper spacer discs for sandwiching and securing a printed circuit board therebetween, lower and upper plates, and a two-step driving mechanism. The lower and upper spacer discs are spaced apart from the lower and upper plates. Activation of the test apparatus in a first step results in relative movement between the spacer discs to sandwich the circuit board therebetween. Activation of the test apparatus in a second step results in relative movement between the lower and upper plates to sandwich the upper and lower spacer discs therebetween.

Abstract: An apparatus is disclosed for measuring the angular position of a movable part. The method and apparatus comprise at least two resonators formed by coupled slow-wave structures, e.g. coupled spirals, and a movable target. The angular position of the target is representative of the angular position of the movable part. A change in the angular position of the target causes a change in electrodynamic parameters of the resonators. The change in the electrodynamic parameters is converted to a reading of angular position of the target with respect to the resonators. An electromagnetic field is excited in the resonators at a frequency at which electromagnetic parameters of the resonators depend upon the position of the target.

Abstract: A filter rod measuring station is equipped with measuring devices which measure at least the mass (M) of a filter rod and the draw resistance (PD) of the filter rod, and a microwave measuring device is provided for measuring the mass of the softener and/or the moisture content and/or the dry mass of the filter rod.

Abstract: Systems, devices, and methods for evaluating iontophoretic properties of compounds. An impedance spectrometer is operable to determine an impedance of a compound and a processor is configured to compare the determined impedance of the compound to a database of stored values.

Abstract: Disclosed is a method and apparatus for an electrochemical impedance measurement, and in particular circuitry and components employed for such measurements. The system employs an injected broadband AC signal to produce an associated response signal. The subsequent analysis of injected and response signals, considering both magnitude and phase, gives broadband impedance and therefore fluid characteristic information. An embodiment described is relative to a smart oil sensor system suitable for sensing, analyzing and reporting the condition of oil or other liquids used in equipment and machinery.

Abstract: A semiconductor device and a method for measuring an analog channel resistance thereof are provided. The semiconductor device-includes-a substrate, a gate insulating layer and a gate formed on the substrate, a source and a drain formed in the substrate and at both sides of the gate, a source sense connected to the source, and a drain sense connected to the drain.

Abstract: It is an object of the present invention to provide a probe which can provide stable electrical conduction to an electrode of an object to be measured even when it is miniaturized. A probe 100 comprises a columnar contact part 110 which can come in contact with an electrode 10 of an object to be measured almost perpendicularly, and a base end (not shown) connected to the contact part 110, the contact part 110 comprises a base part 111 and an expansion part 111a bonded to an end of the base part 111 in a width direction, and the expansion part 111a is formed of a material having a thermal expansion coefficient higher than that of the base part 111.

Abstract: A contactor device comprising a plurality of probes disposed to contact ones of the electronic devices can be electrically connected to a source of test signals. A switch can be activated electrically connecting a connection to the source of test signals to a selected one of a first group of electrically connected ones of the probes disposed to contact a first set of a plurality of the electronic devices or a second group of electrically connected ones of the probes disposed to contact a second set of a plurality of the electronic devices.

Abstract: A vertical-type probe card includes a circuit board, which has signal circuits and grounding circuits arranged in such a manner that each signal circuit is disposed in parallel and adjacent to one grounding circuit and kept a predetermined distance from the grounding circuit, and a probe assembly, which is arranged at the bottom side of the circuit board and has an upper guide plate, a lower guide plate, a conducting layer provided on the lower guide plate, a plurality of signal probes respectively electrically connected to the signal circuits and adjacent to a plurality of compensation probes, and at least one grounding probe electrically connected to the grounding circuits in a manner that the signal, compensation and grounding probes are vertically inserted through the upper and lower guide plates, and the conducting layer is conducted with the compensation probe and the grounding probe while electrically insulated to the signal probe.

Abstract: A vertical probe device includes two guide members arranged in a stack manner and defining therebetween an accommodation chamber, a probe holder plate disposed between the guide members, and a plurality of probes inserted through the guide plates and the probe holder plate in such a manner that the probes are flexible within the accommodation chamber. One of the guide plates has at least one through hole. The probe holder plate is slightly moveable in horizontal and vertical directions but fixable to one of the guide plats under a force applied through the at least one through hole to the probe holder plate while the other of the guide plates is removed, thereby preventing damage of the probes or movement of the probes during a maintenance work.

Abstract: The present invention is a method for evaluating an SOI wafer by using a mercury probe, comprising at least steps of, subjecting the SOI wafer to a hydrofluoric acid cleaning treatment and thereby to remove a native oxide film formed in a surface of the SOI wafer, next subjecting the native oxide film-removed SOI wafer to a treatment for stabilizing charge state, then contacting the charge-state stabilizing-treated SOI wafer with the mercury probe, and thereby evaluating the SOI wafer. Thereby, there can be provided an evaluation method in which a large-scale apparatus and multiple steps such as a photolithography process are not required and by which an electric characteristic of an SOI wafer can be measured simply and high-precisely in a short time and operation rate of measurement apparatus is improved and thereby the SOI wafer can be effectively evaluated.

Abstract: It is an object to provide an apparatus for inspecting a circuit board and a method of inspecting a circuit board which can well absorb a variation in a height of an electrode to be inspected in a circuit board to be inspected and can maintain an insulating property between adjacent inspection electrodes even if the electrode to be inspected is arranged at a fine pitch. An intermediate holding plate 36 is provided in a relay pin unit 31, and a first abutment support position 38A of a first support pin 33 disposed between a first insulating plate 34 and the intermediate holding plate 36 with respect to the intermediate holding plate and a second abutment support position 38B of a second support pin 37 disposed between a second insulating plate 35 and the intermediate holding plate 36 with respect to the intermediate holding plate 36 are placed differently from each other over an intermediate holding plate projecting surface which is projected in a direction of a thickness of the intermediate holding plate 36.

Abstract: A cable includes an inner conductor, an inner dielectric, and a guard conductor, where the inner dielectric is between the inner conductor and the guard conductor. The cable also includes an outer dielectric, and a shield conductor, where the outer dielectric is between the guard conductor and the shield conductor. The cable further includes an additional layer of material between the outer dielectric and the shield conductor of suitable composition for reducing triboelectric current generation between the outer dielectric and the shield conductor to less than that which would occur were the outer dielectric and the shield conductor to directly adjoin each other.

Abstract: A probe measurement system for measuring the electrical characteristics of integrated circuits or other microelectronic devices at high frequencies.

Abstract: The present invention generally relates to testing of IC devices, more specifically to a contact (11) for a test socket (1) for interfacing leads (21) of the IC devices (2) with a printed circuit board (3) of a tester. The contact (11) comprises a contact body (12), a first arm (13) adapted for electronically engaging the leads (21) and a second arm (14) adapted for electronically engaging the corresponding terminals (31) on the printed circuit board (3). The first engaging means (15) is a wiping means for improved wiping action between the contact (11) and the leads (21). The wiping means enable a single contact to be used for various IC devices and also protects the leads (21) and contacts (11) of the test socket (1) from damage and extensive wear.

Abstract: A test chip socket comprises a contact block fixed to a tester substrate, a tray mounted to the contact block, the tray having a convex part for positioning test target chips to a plurality of mount positions, and a plurality of probes each of which is held by the contact block and contacts the tester substrate and the test target chip, wherein each probe contacts with a terminal of each test target chip mounted to the mounting position when the tray mounting the plurality of the test target chip is fixed to the contact block.

Abstract: An integrated circuit (IC) package testing apparatus integrates a temperature sensor, heater (or cooler), and controller within a single modular unit. The controller is a microprocessor embedded within the modular unit and in communication with the sensor and heater. The controller allows a selected testing temperature to be input by a user via a communications link to the controller. Each IC package has its testing temperature individually controlled by a controller. The module is easily attached and removed from an open-top socket through the use of latches on the testing socket. Many IC packages can be quickly placed and removed from testing sockets when a matrix of sensors and heaters (or coolers) are located on a single top attach plate with the sensors and heaters (or coolers) individually spring-loaded on the single top attach plate.

Abstract: The probe assembly has a plurality of probes, a probe base provided with the probes, and a plurality of guard members provided on the probe base. Each probe has an arm portion supported on the probe base at its one end and extending from a mounting surface of the probe base at a distance substantially along the mounting surface. At the other end of each arm portion is formed a tip projecting so as to project in a direction to be away from the mounting surface of the probe base. The guard member is supported on the probe base near at least one side of each arm portion. The guard surface is positioned in the vicinity of the height position of one surface and the opposite other surface of the arm portion opposing the mounting surface of the probe base.

Abstract: An electric potential difference detection method detecting an electric potential difference occurring between a surface of a sample and a probe of a cantilever of a scanning probe microscope includes: applying an AC voltage of a frequency of ½ of a resonance frequency of the cantilever, between the sample and the cantilever; detecting vibration characteristics of the cantilever; and judging an existence/nonexistence of the electric potential difference between the surface of the sample and the probe of the cantilever on the basis of the vibration characteristics of the cantilever.

Abstract: A probe measurement system for measuring the electrical characteristics of integrated circuits or other microelectronic devices at high frequencies.

Abstract: A method for testing a plurality of DUTs using a plurality of DC instruments and a pulsed instrument includes contemporaneously applying DC signals to the DUTs with respective DC instruments and sequentially performing pulsed measurements on the DUTs with the pulsed instrument.

Abstract: A method and system for detecting or reviewing defective contacts on a semiconductor device are disclosed. In a first embodiment, the method and system comprise providing a positive charge sufficient enough to turn on a gate of an associated MOS device and scanning an area of interest within the MOS device with a primary electron beam of proper landing energy to generate image. The method and system include analyzing the signal of contacts and identify the open contacts. In a second embodiment, the method and system comprises pre-scanning or irradiating the wafer surface defect with an accessory beam, a plurality of times, to achieve positive charged/sufficient to turn on the gate on the associated MOS devices of the wafer; and scanning the at least a portion of the device circuits with a primary electron beam of proper landing energy to generate images wafer or area of interest. The method and system include analyzing the signal and/or image of contacts and identify the open contacts.

Abstract: A method and apparatus for measuring a leakage current of a semiconductor device having a first end and a second end are disclosed. The apparatus for measuring a leakage current includes a capacitor having one end coupled with the first end of the semiconductor device; and a MOSFET transistor having a drain node, a gate node formed to be coupled with one end of the semiconductor and source and bulk nodes formed to be coupled with the second end of the semiconductor device and to receive power.

Abstract: The present invention relates to a scan chain and related cell design structures in a custom electronic circuit design with a plurality of storage elements. All scan inputs and all scan outputs of the storage elements are propagated to a top level of the design hierarchy in design. Each scan input and each scan output on the top level is declared a primary input and primary output, respectively. Propagating all the inputs and outputs of the storage elements to this level improves the wireability of the scan chain.

Abstract: A CMOS output driver is provided for driving a capacitive load over a circuit trace in high speed applications. The CMOS output driver comprises a signal input and a signal output. The output driver has a first buffer amplifier with an input connected to the signal input and an output connected to the signal output through a resistor. A second buffer amplifier is also provided, which has an input connected to the signal input and an output connected to the signal output through a capacitor.

Abstract: A method, system, and output driver calibration circuit determines calibration values for configuring adjustable impedance output drivers. The calibration circuit includes a pull-up calibration circuit configured to generate an averaged pull-up count signal for calibrating p-channel devices in the output driver with the averaged pull-up count signal being an average of a plurality of pull-up count signals. The calibration circuit further includes a pull-down calibration circuit configured to generate an averaged pull-down count signal for calibrating n-channel devices in the output driver with the averaged pull-down count signal being an average of a plurality of pull-down count signals.

Abstract: An output circuit includes a counter circuit that generates an ODT control signal ODTa, plural driver circuits having the ODT function, a synchronizing circuit that synchronizes a signal transmitted from the counter circuit to the driver circuit with an internal clock DLL, a first selecting circuit that activates one of plural ODT selection signals ODTb and ODTc based on the ODT control signal ODTa, and a second selecting circuit that selects a driver circuit to be used out of the plural driver circuits based on the activated ODT selection signal. The first selecting circuit is provided between the counter circuit and the synchronizing circuit, and the second selecting circuit is provided between the synchronizing circuit and the driver circuit.

Abstract: An output circuit of a semiconductor includes unit buffers, each unit buffer having transistors and resistors connected between a power source terminal VDDQ and an output terminal DQ, and transistors and resistors connected between a power source terminal VSSQ and an output terminal DQ. On-resistance values of transistors included in the unit buffers are mutually substantially the same, and resistance values of resistors included in the unit buffers are mutually different. A deviation of impedances attributable to a power source resistance can be offset based on a difference between resistance values of the resistors.

Abstract: A microcontroller may have at least a first and second output port coupled with external first and second pins, respectively, a programmable switching arrangement operable in a first mode to provide for a first and second output signal at the first and second pins, respectively, and in a second mode to provide for a first output signal at the first pin and an inverted first output signal at the second pin.

Abstract: Logic cells in an application-specific integrated circuit (ASIC) emulating standard gate sizing by duplicating elements within a single standard gate where logical high-drive gates are synthesized and converted to parallel elements as a post-process. The drive characteristics of the logical gates are retained during the conversion to the physical gate equivalents in the standard cell architecture. The logic cells in the device may include, for example, at least two two-input multiplexors.

Abstract: A circuit arrangement for converting logic signal levels has a level converter and a mixing arrangement for influencing a pulse width. The level converter includes a first signal path and a second signal path each having a series circuit comprising two transistors of different conductivity types and two outputs which are each connected to a tap between the transistors which are coupled in series. In this case, the transistors of one conductivity type can be controlled by means of a push-pull signal and the transistors of the other conductivity type in a respective one of the two signal paths can be controlled by means of a signal at the output of the respective other signal path. The mixing arrangement includes two inputs and two outputs, the first input being coupled to the first output and the second input being coupled to the second output.

Abstract: A level shifter circuit for converting a logic signal with logic ‘1’ and ‘0’ levels at first high and low supply voltage levels to a signal with second high and low supply voltage levels. In particular, the second high and low supply voltage levels are greater than the first high and low supply voltage levels. The disclosed level shifter is configured such that the size of the preceding logic gate and circuitry within the level shifter can be reduced, facilitating its layout in pitch-limited areas. The level shifter also includes circuitry to decouple the output pull-up and pull-down paths to further facilitate state transitions and reduce crowbar current consumption.

Abstract: An input signal is routed to a first logic one reference signal generator or alternatively routed to a second logic one reference signal generator based at least one a voltage level of the input signal. When the voltage level of the input signal is less than a threshold value, the first logic one reference signal generator selectively generates a first logic one reference signal. When the voltage level of the input signal is greater than or equal to the threshold value, the second logic one reference signal generator alternatively generates a second logic one reference signal. The first and second logic one reference signals may be used to control a first voltage scaling circuit that drives a scaled output signal having a logic one value corresponding to the voltage level of the first logic one reference signal.

Abstract: A variable switching point inverter (30) is disclosed which lowers the threshold voltage lowered for both rising and falling edge input voltages (VIN) by changing the P/N ratio of the inverter based on the delayed output state (VOUT) of the inverter. The variable switching point inverter may be constructed as a CMOS integrated circuit with a first inverter stage (33, 34) coupled in parallel to a second inverter stage (35, 36) having extra PMOS (37) and NMOS (38) transistors connected to VDD and VSS, respectively, where the extra PMOS and NMOS transistors are controlled by the delayed output signal (40) generated by a delay element (39) coupled to the output of the first inverter stage. By using a delayed feed back signal (40) to control the extra PMOS and NMOS gates (37, 38), the switching point voltage of the first inverter stage (33, 34) is altered, depending on whether the input transitions are high-to-low or low-to-high.

Abstract: An electronic circuit, including a signal transmitter, a signal generator and a ring oscillator, has a topography that is entirely symmetrical so that signals transmitted or produced by the circuit have symmetrical output signals tolerant to input timing skew, output delay/slewrate-mismatch, and complementary device-mismatch. Each P-type transistor in the circuit has a correspondingly connected P-type transistor connected to signal nodes and supply voltage nodes in a complementary manner. Similarly, each N-type transistor in the circuit has a correspondingly connected N-type transistor connected to signal nodes and supply voltage nodes in a complementary manner.

Abstract: Methods and apparatus are provided for loss-of-clock detection. A loss of a clock signal is detected by delaying the clock signal using one or more delay elements; and applying an output of the one or more delay elements to at least one logic gate having a plurality of inputs, wherein the at least one logic gate has a predefined binary output value when each of the inputs to the at least one logic gate have a predefined input binary value to detect when the clock signal is in a fixed binary position. The at least one logic gate can be an AND gate (or a NOR gate having inverted inputs) to detect when the clock signal is in a fixed high position. The at least one logic gate can also be a NOR gate (or an AND gate having inverted inputs) to detect when the clock signal is in a fixed low position. A third logic gate, such as an OR gate, can detect when at least one of two logic gates has a predefined binary output value.

Abstract: Logic LSI includes first power domains PD1 to PD4, thick-film power switches SW1 to SW4, and power switch controllers PSWC1 to PSWC4. The thick-film power switches are formed by thick-film power transistors manufactured in a process common to external input/output circuits I/O. The first power domains include second power domains SPD11 to SPD42 including logic blocks, control circuit blocks SCB1 to SCB4, and thin-film power switches SWN11 to SWN42 that are connected to the thick-film power switches via virtual ground lines VSSM1 to VSSM4, and formed by thin-film power transistors manufactured in a process common to the logic blocks. In this way, power switches having different thickness of gate insulating films from one another are vertically stacked so as to be in a hierarchical structure, and each power switch is individually controlled by a power switch controller and a control circuit block correspondingly to each mode.

Abstract: A semiconductor memory apparatus includes a phase comparator configured to compare phases of rising and falling feedback clocks with that of a reference clock, a delay circuit configured to delay the reference clock by a predetermined time based on a comparison result of the phase comparator to thereby generate rising and falling delayed clocks, a clock transmission block configured to invert the rising delayed clock outputted from the delay circuit when the rising and falling feedback clocks have substantially different phases, a duty compensator configured to compensate a duty ratio from outputs of the clock transmitting block to generate a delay locked clock having a compensated duty ratio, and a delay model configured to delay an output and an inverse output of the duty compensator by a modeled delay time respectively to generate the rising and falling feedback clocks.

Abstract: A method for operating a threshold circuit arrangement and a threshold circuit arrangement is disclosed. In one embodiment, the invention provides a threshold circuit arrangement, wherein a comparator circuit is configured to compare an input signal is compared with a predetermined threshold, and wherein, depending on the result of the comparison, an output signal is adapted to change its state. A circuit is provided for preventing the change of state of the output signal in the case of predetermined forms of the input signal.

Abstract: A comparator includes a differential pair of transistors providing a first amplification stage and receiving inverting and non-inverting input signals. An output transistor is coupled to the differential pair of transistors providing a second amplification stage and transitioning the output signal state when the non-inverting input signal is larger than the inverting input signal. The output node of one of the differential pair of transistors is connected to an input node of a current-tail transistor. The output node of the other differential transistor is connected to an input node of the output transistor. The other nodes of the differential pair of transistors are connected to each other and are coupled to an output node of the current-tail transistor. The output nodes of the differential pair of transistors and an output node of the output transistor are each coupled to a separate current generator that may include a complex impedance element.

Abstract: A system for detecting a direct current (DC) component of a pulse-width modulated (PWM) signal includes a modulator configured to provide at least one PWM signal to an input of an amplifier. A DC detector is configured to detect a DC component of a selected one of the at least one PWM signal as a function of a switching frequency of the selected PWM signal. The DC detector provides at least one report signal that indicates a level of the DC component of the selected PWM signal relative to a predetermined threshold.

Abstract: Methods and apparatus are disclosed to track and hold a voltage. An example track and hold circuit comprises a first electronic switch, a second electronic switch, and a current mode logic amplifier.

Abstract: A clock switching circuit for switching between plural clock signals includes a selector for outputting a first control signal when a low speed clock is selected by a selection signal with a permission signal halted, and a second control signal when a high speed clock is selected by the selection signal with a second permission signal halted. The switching circuit includes a first stabilizer for holding the first control signal in timed with the low speed clock to output the second permission signal, and a second stabilizer for holding the second control signal in timed with the high speed clock to output the first permission signal. The switching circuit includes a first and a second gating cell circuit for latching and outputting the low speed clock and the high speed clock when the second permission signal and the first permission signal is supplied, respectively.