Abstract: A driving circuit includes a first switchable current module for providing a first current, a second switchable current module for providing a second current, a first switchable current source having an input end coupled to a first output end of the second switchable current module, a second switchable current source having an input end coupled to a second output end of the second switchable current module, a third switchable current source having an input coupled to a first output end of the first switchable current module, a fourth switchable current source having an input end coupled to a second output end of the first switchable current module, and a termination impedance circuit. The termination impedance circuit has a first end coupled to the first switchable current source and the third switchable current source, and a second end coupled to the second switchable current source and the fourth switchable current source.

Abstract: An analog buffer used in a source driver is provided. The analog buffer havs an input end, an output end, a transistor, first and second capacitors, first, second, third, fourth and fifth switches. The source and the drain of the transistor is coupled to the output end and receives a first voltage respectively. The first end of the first and the second capacitors are coupled to the gate of the transistor. The second end of the first and the second capacitors are coupled to the first end of the first, second and fourth switches and the first end of the third and fifth switches respectively. The second end of the first switch receives a second voltage. The second end of the second and third switches are coupled to the input end. The second end of the fourth and fifth switches are coupled to the output end.

Abstract: When a signal of a double frequency is generated from the original signal, conventionally a 90-degree phase-shift circuit is necessary to suppress an output of a DC component and efficiently obtain a double wave. According to the present invention, an equal RF signal is inputted to input terminals and an output is matched with a frequency as high as that of the original frequency in a Gillbert cell double-balanced mixer, so that a doubled output is obtained with no DC offset. According to the circuit configuration of the present invention, it is possible to provide a circuit readily performing integration and to efficiently output only a double frequency merely by inputting a simple differential signal without the need for the original signal which has been phase controlled. Further, a DC short circuit in the resonance circuit makes it possible to eliminate a DC offset voltage in an output.

Abstract: A system-on-chip may include a hard-macro block, a deepstop control logic circuit, and/or a multi-threshold complementary metal-oxide-semiconductor (MTCMOS) logic circuit. The deepstop control logic circuit may be configured to transfer data to the hard-macro block from the multi-threshold complementary metal-oxide-semiconductor (MTCMOS) logic circuit during a normal mode. The deepstop control logic circuit may be configured to latch the data output from the MTCMOS logic circuit upon an entry into a deepstop mode and interrupt a power supply to the hard-macro block during the deepstop mode.

Abstract: A skew correction apparatus is composed of a variable delay line 200 for generating a delayed clock signal DCLK by delaying a clock signal CLK by a variable delay amount DT, a phase comparator 10 for comparing a phase of the delayed clock signal DCLK with transition of rising of a data signal DAT, a voltage holding means 6 for holding a voltage Vcntl for controlling the delay amount DT of the variable delay line 200, a charging/discharging means 30 for charging or discharging the voltage holding means 6, depending on a comparison result of the phase comparator 10, a charging means 40 for setting the voltage Vcntl of the voltage holding means 6 during initial setting, and a control circuit 500 for controlling the charging means 40.

Abstract: A delay line comprises first and second delay arrays and a multiplexer. The first delay array receives a clock signal and a delay control signal, and delays the clock signal to output a first delay array clock signal according to the delay control signal. The second delay array receives a power control signal, the first delay array clock signal and the delay control signal. The second delay array is turned on or off according to the power control signal. If the second delay array is turned on, the second delay array delays the first delay array clock signal to output a second delay array clock signal according to the delay control signal. The multiplexer receives a selecting control signal, the first and second delay array clock signals, and outputs the first delay array clock signal or the second delay array clock according to the selecting control signal.

Abstract: A DLL circuit includes a first delay adjusting circuit that adjusts an amount of delay of a frequency-divided signal CK1, a second delay adjusting circuit that adjusts an amount of delay of a frequency-divided signal CK2, a synthesizing circuit that synthesizes outputs of these delay adjusting circuits to generate an internal clock signal, and supplies the internal clock signal to a real path, a clock driver that receives the output of the first delay adjusting circuit and supplies the output to a replica path, and a clock driver that receives the output of the second delay adjusting circuit. These clock drivers have substantially the same circuit configuration. Accordingly, even when the power supply voltage fluctuates, influences of the fluctuations on the respective frequency-divided signals are almost equal. Thus, deterioration of the function of the DLL circuit due to fluctuations of the power supply voltage can be prevented.

Abstract: A phase-locked loop (PLL) circuit includes a reference clock divider with a reference clock input, a phase-frequency detector, a charge pump, a loop filter, a voltage controlled oscillator and a feedback divider. A method of operating the PLL circuit comprises the steps of detecting a failure of a reference clock applied to the reference clock input, disabling the charge pump upon detection of a reference clock failure, monitoring the reference clock to detect restoration of a regular reference clock, upon detection of a regular reference clock, detecting occurrence of the next pulse from the feedback divider, and enabling the charge pump upon detection of the next pulse from the feedback divider.

Abstract: The method is for controlling a charge pump of the type where two flying capacitors charge and discharge to a reservoir capacitor in sequence. Part of the switching is carried out in parallel, lengthening the charging pulse at the expense of the conventional comparatively long discharge pulse, thus providing operation at higher frequencies than previously possible.

Abstract: A delay looked loop (DLL) having a charge pump gain independent of the operating frequency of the DLL. A method for providing a constant gain for a charge pump component of a delay locked loop (DLL) is disclosed, and includes: providing a switched capacitor stage responsive to a charge phase for charging a capacitor and a dump phase for dumping the capacitor; and aligning the charge phase and the dump phase such that a control voltage provided by the charge pump is independent of a frequency of a DLL charge and discharge phase.

Abstract: A delay looked loop (DLL) having a charge pump gain independent of the operating frequency of the DLL.

Abstract: A semiconductor memory device includes a delay locked loop for correcting a duty cycle rate of a delay locked clock signal. The semiconductor memory device includes a delay locked circuit, a duty cycle correction circuit, and a clock synchronization circuit. The delay locked circuit outputs a delay locked clock by delaying a system clock by a predetermined time. The duty cycle correction circuit outputs a first clock by correcting a duty cycle of the delay locked clock, wherein the proportion of high to low level periods of the delay locked clock is controlled according to a time difference between a second edge of the first clock and that of a second clock derived from the first clock. The clock synchronization circuit synchronizes a first edge of the first clock with that of the second clock.

Abstract: Disclosed is a module where semiconductor memory devices each having a DLL (Delay Lock Loop) are stacked or a multi-chip module (MCM) having the semiconductor memory devices, a dedicated pad for sharing a clock signal between one of the semiconductor memory devices and other semiconductor memory device is included. The clock signal is delay adjusted by the DLL. The DLL in the one semiconductor memory device is operated, while the DLL in the other semiconductor memory device is not operated. A flying lock clock signal synchronized with an external differential clock signal and generated from a clock signal delay adjusted by the DLL is output from the dedicated pad of the one semiconductor memory device. The other semiconductor memory device receives the flying lock clock signal from the dedicated pad.

Abstract: A jitter reduction circuit includes a signal line transmitting a first signal and having a plurality of sections, and a plurality of delay lines transmitting a second signal and provided in one-to-one correspondence to the sections of the signal line, wherein the plurality of delay lines is configured such that a delay of the second signal on a given one of the delay lines is set to a first delay in response to a first level of the first signal in a corresponding one of the sections, and is set to a second delay in response to a second level of the first signal in the corresponding one of the sections.

Abstract: A method and apparatus for correcting for deterministic jitter in a sequential sampling timebase. The value of a fine analog delay is held at a substantially constant nominal rate during a duration of a counting of a digital clock. A time difference between a trigger at which a fine analog delay starts measuring time and the occurrence of a digital pulse of a stable clock used to count a coarse delay is measured. An input waveform is sampled at a sample time having a nominal delay time. After sampling, a desired compensation time is provided for the sample of the input waveform in accordance with combinations of three independent variables defining a calibration table. The waveform is reconstructed by shifting a delay time of a sampled value of the input waveform from its nominal delay time in accordance with a value defined by the calibration table.

Abstract: The present invention relates to a signal transferring system. The signal transferring system includes a first and second layout paths, and a first and second circuits. Lengths of the first and second layout paths are different. The first and second circuits are used for transmitting and receiving at least two signals respectively. In addition, one of the first circuit and the second circuit includes a compensation circuit for adjusting transmission time of one of the at least two transferred signals or adjusting reception time of one of the at least two transferred signals such that the at least two transferred signals reach a second circuit through the first and the second layout paths at substantially the same time.

Abstract: A circuit and method for controlling a slew rate of an output buffer. A pre-driver is provided that drives an input of an output pad driver of the output buffer. An output slew rate of the pre-driver is electronically selected among at least two electronically selectable slew rates. An output amplitude of the pre-driver is controlled such that the output amplitude is not greater than an amplitude that is generally minimally sufficient to cause the output pad driver to produce an output signal having a desired dynamic range.

Abstract: A system for changing voltage states at an output of an electronic device. In one embodiment, the system includes a voltage conveyor module coupled to the output of the electronic device and a voltage signal generator capable of producing a first voltage at the output. The voltage conveyor module is controllably coupled to the output, and the voltage signal generator is controllably uncoupled from the output of the electronic device. The voltage conveyor conveys the second voltage to the output in a characteristic manner. The second voltage level is provided as input to the voltage signal generator and the voltage signal generator is recoupled to the output of the electronic device. The voltage conveyor is then electrically uncoupled from the output. The voltage conveyor may control the voltage transition such that the voltage transitions without discontinuities. In other embodiments, the voltage may transition monotonically.

Abstract: A pulse width modulation control circuit for providing a pulse width modulation signal in accordance with an embodiment of the present application includes a comparator operable to compare a first input to a second input and to provide the pulse width modulation signal based on the comparison, wherein the first input is an error signal and the second input is a ramp signal, wherein a first portion of the ramp is a decreasing ramp signal having a first slew rate and a second portion of the ramp signal is an increasing ramp signal having a second slew rate.

Abstract: Bistable circuit switching at the edges of a clock signal, including means for pre-charging an intermediate node of the circuit, delay means including a chain of inverters defining a time window around an edge of said clock signal, means for discharging the intermediate node controlled by at least one input data item making it possible to discharge the intermediate node for the duration of said time window, characterized in that the delay means include means for temporally adjusting the duration of the time window to the time for discharging the intermediate node through said discharge means.

Abstract: An improved CMOS high-voltage latch stores data bits to be written to memory cells of a non-volatile memory has two cross-coupled CMOS inverters. One of the inverters has a pull-down leg that includes a pass-gate high-voltage NMOS transistor that is connected between a latch output node and a second high-voltage, low-threshold NMOS pull-down transistor that is connected to ground. A gate of the pass-gate high-voltage NMOS transistor receives a standby signal with a logic HIGH value of at most Vdd to turn on the pass-gate high-voltage NMOS transistor when the high-voltage CMOS latch is in a voltage mode of operation and during a high-voltage write mode of operation. The pass-gate high-voltage NMOS transistor thereby limits the voltage across the second high-voltage, low-threshold NMOS pull-down transistor to less than the standby signal in order to reduce punch-trough current and drain-to-substrate leakage of the second high-voltage, low-threshold NMOS pull-down transistor.

Abstract: In high-speed flip-flops and complex gates using the same, the flip-flop includes a first PMOS transistor and second and third NMOS transistors, which are serially connected between a power supply voltage and a ground voltage. Gates of the first PMOS transistor and the second NMOS transistor are connected to input data. A gate of the third NMOS transistor is connected to a clock pulse signal. A logic level of a first intermediate node between the first PMOS transistor and the second NMOS transistor is latched by a first latch. The flip-flop further includes a fourth PMOS transistor and fifth and sixth NMOS transistors, which are serially connected between a power supply voltage and a ground voltage. Gates of the fourth PMOS transistor and the fifth NMOS transistor are connected to the first intermediate node. A gate of the sixth NMOS transistor is connected to the clock pulse signal.

Abstract: Circuitry for latching receives an input signal and a control signal and provides an output signal. In one embodiment, the setup time (t(SL) and t(SH)) of the input signal with reference to the control signal is to the first edge of the control signal, the holding time (t(HL) and t(HH)) of the input signal with reference to the control signal is independent of the second edge of the control signal, and the output signal goes to a predetermined state in response to the second edge of the control signal. In one embodiment, the control signal may be a clock. The circuitry for latching may be used with static circuits and/or with dynamic circuits.

Abstract: Objects of the invention are to provide a clock generation circuit, in which, even when different clock signals are used among a plurality of circuits such as a transmitting circuit and a receiving circuit, stabilized communication is possible; and to provide a semiconductor device including the clock generation circuit. The clock generation circuit includes an edge detection circuit, a reference clock generation circuit, a reference clock counter circuit, and a frequency-divider circuit. The reference clock counter circuit is a circuit which outputs a counter value, which is obtained by counting the number of waves of a reference clock signal outputted from the reference clock generation circuit, in a period of time from when the edge detection circuit detects an edge of a signal which is externally inputted to the edge detection circuit to when the edge detection circuit detects the next edge, to the frequency-divider circuit.

Abstract: An electronic circuit for performing clock gating on a clock signal supplied to a clock system using both edges, has a non-inverted/inverted signal selector which has an input connected to an input terminal, is fed with the clock signal through the input terminal, and outputs a first signal obtained by non-inverting or inverting the clock signal in response to a control signal; a signal latch which has an input connected to an output of the non-inverted/inverted signal selector, outputs the inputted first signal as a second signal through an output terminal, and latches a state of the second signal in response to an enable signal inputted through an enable terminal; and an input/output comparator which compares the clock signal and the second signal and outputs the control signal to the non-inverted/inverted signal selector such that the first signal agrees with the second signal.

Abstract: A level-determining device of pulse width modulation (PWM) signal includes a PWM signal generating circuit, a reference voltage generating circuit and a determining circuit. The PWM signal generating circuit generates a first PWM signal. The reference voltage generating circuit generates a reference voltage signal. The determining circuit is respectively electrically connected to the PWM signal generating circuit and the reference voltage generating circuit for determining high level or low level of the first PWM signal in accordance with the reference voltage signal for generating a second PWM signal.

Abstract: A level shifting circuit converts an input signal that varies between ground and a first voltage to a shifted signal that varies between ground and a second voltage higher than the first voltage. The level shifting circuit has two branches, in each of which a p-channel transistor and two n-channel transistors are connected in series between the second voltage and ground. When the two n-channel transistors in each branch are turned off, a clamping circuit clamps the node between them to the first voltage level, so that neither n-channel transistor has to withstand the full difference between the second voltage and ground. The level shifting circuit can accordingly be fabricated with transistors of small size, reducing the cost of driving circuits, light-emitting-diode print heads, and image forming apparatus in which the level shifting circuit is used.

Abstract: A level shifting circuit having a signal input that operates in a first voltage domain and a signal output that operates in a second voltage domain. In some embodiments, the level shifting circuit includes a clocked level shifter. In some embodiments, the level shifting circuit includes a level shifting latch that latches a translated output signal. In one example, the level shifting latch includes a latch portion and a stack of transistors with a transistor having a control electrode coupled to a clock input.

Abstract: A calibration circuit includes: a replica buffer that drives a calibration terminal ZQ; a reference voltage generating circuit that generates a reference voltage VMID; a comparing circuit that compares a voltage appearing in the calibration terminal ZQ with the reference voltage VMID; an impedance adjusting circuit that changes an output impedance of the replica buffer based on a result of comparison carried out by the comparing circuit; and a reference voltage adjusting circuit that adjusts the reference voltage VMID. With this arrangement, the reference voltage VMID can be offset by taking into account a resistance component present between the calibration terminal ZQ and the external terminal, and therefore, a more accurate calibration operation can be carried out.

Abstract: Example embodiments relate to a low power level shifter. The low power level shifter may include an input unit, a pull-down driving unit, a pull-up driving unit and a blocking unit. The input unit may be configured to generate a current signal based on an input signal applied to an input port, so that the input signal may switch between a first voltage level and a second voltage level. The pull-down driving unit may be connected to an output port, the pull-up driving unit may be between a power supply voltage having a third voltage level and the output port, and the blocking unit may be between the input unit and the pull-up driving unit.

Abstract: Methods and systems for reducing parasitic capacitance of a buffer for an electric circuit are disclosed and may include coupling a gate of a first transistor to a first differential input of the buffer via a first capacitor, coupling a gate of a second transistor to a second differential input of the buffer via a second capacitor. The first and second transistors may be biased by a common mode output of a direct current (DC) voltage source for the buffer. The common mode output of the DC voltage source may be directly coupled to at least one differential output of the buffer via an inductor. The first transistor and the second transistor may comprise NMOS transistors and/or PMOS transistors. The DC voltage source may comprise a PMOS transistor and/or an NMOS transistor.

Abstract: A High Voltage Gate Driver IC (HVIC) having an internal ramp drive function for controlling a high power switch to produce ramp output voltage waveforms. The HVIC including a sensor for sensing a voltage across the power switch; a reference generator for generating a reference voltage signal in accordance with an external setting; and a feedback circuit to provide a feedback gain to control a gate of the power switch, the feedback circuit making voltage across the power switch follow to reference and stable, wherein the HVIC generates the ramp drive function with minimized circuit components external to the HVIC.

Abstract: A signal generating and switching apparatus and a method thereof are provided. According to a simple layout technique, the signal switching apparatus is formed in each layer of a plurality of metal layers in an integrated circuit. When there is a need to correct any one of the plurality of conductive layers in the integrated circuit, the changing of the signal switching apparatus in that conductive layer can be achieved by changing mask patterns of the conductive layer. As a result, the transmission path of signals in the conductive layer is changed, and the purpose to change output logic signals is achieved. Therefore, there is no need to change additional conductive layers, thereby significantly reducing the correcting cost of the integrated circuit.

Abstract: Systems, circuits, and methods for providing alternate polarity current pulses through a current transformer for operation of a thyristor are disclosed.

Abstract: A gate-on voltage generator that can enhance display quality at low temperatures, a driving device, and a display apparatus having the same, in which the gate-on voltage generator includes a temperature sensor having an operational amplifier configured to receive a driving voltage and produce a temperature-dependent variable voltage, the level of which varies according to the ambient temperature, and a charge pumping unit shifting the temperature-dependent variable voltage by the voltage level of a pulse signal and generating a gate-on voltage.

Abstract: A fuse circuit comprises at least one fuse circuit unit and a current blocking module. The fuse circuit unit comprises a voltage establishing module and a latch. The voltage establishing module is coupled to a first reference voltage source and includes a fuse that is capable of being selectively blown according to an initial setting signal. The fuse has a first terminal coupled to a node and a second terminal. The voltage establishing module establishes a voltage level on the node according to the blown-off status of the fuse. The latch is coupled to the voltage establishing module through the node for latching the voltage level of the node and generating the output signal. The current blocking module is coupled between a second reference voltage source and the second terminal of the fuse for blocking the current flowing through the fuse while initial setting.

Abstract: A body biasing control circuit capable of being shared by a plurality of macro blocks and can independently control body voltages of a plurality of macro blocks. The body biasing control circuit includes a lookup table for storing a plurality of indexes where each index is associated with a body voltage appropriate for an operating state of a corresponding macro block. A control unit receives a corresponding index from the lookup table and generates a plurality of body voltages appropriate for an operating state of a macro block corresponding to the index and supplies the body voltages to the macro block.

Abstract: A method for operating a plurality of charge pumps comprising: generating one or more phase-shifted clock signals; and coupling the one or more phased-shifted clock signals to the plurality of charge pumps, wherein the charge pumps are clocked at a different time to avoid excessive charging spikes caused by concurrent operation of the charge pumps.

Abstract: A booster circuit includes a pump circuit that boosts a voltage supplied from a power supply and outputs the boosted voltage, and a pump controlling circuit that outputs a first clock signal for operating the pump circuit to control the operation of the pump circuit. The pump controlling circuit controls the pump circuit to reduce a number of active charge pump circuits according to an output signal of one of a first comparator and a second comparator, controls the pump circuit to reduce a frequency of a second clock signal for operating the active charge pump circuits by reducing a frequency of the first clock signal according to the other output signal of one of the first comparator and the second comparator, and brings the pump circuit into an inactive state according to an output signal of a third comparator.

Abstract: A booster circuit of a two-step booster structure is manufactured by NMOS single channel processes and has two basic booster circuits to raise a gate voltage of a charge transfer transistor. The gate voltage of the transistor is first raised at one basic booster circuit, and this raised voltage is further raised at the other basic booster circuit.

Abstract: An amplifier power-down apparatus is provided for reducing transient signals in an audio circuit comprising a reference voltage generator circuit for generating a reference voltage. The reference voltage generator circuit comprises a capacitor for maintaining the reference voltage at a desired level. The amplifier power-down apparatus comprises a discharge control circuit for controlling the operation of the reference voltage generator circuit during power-down. The discharge control circuit comprises a switching device for controlling the discharging of the capacitor, wherein the switching device is controlled by a pulsed signal. The pulsed signal is a pulse width modulated (PWM) signal in which the pulse width is proportional to the voltage level of the reference voltage being discharged.

Abstract: An MOS device includes first and second source/drain regions of a first conductivity type formed in a semiconductor layer of a second conductivity type proximate an upper surface of the semiconductor layer, the first and second source/drain regions being spaced apart relative to one another. A non-uniformly doped channel region of the first conductivity type is formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions. An insulating layer is formed on the upper surface of the semiconductor layer. A first gate is formed on the insulating layer at least partially between the first and second source/drain regions and above at least a portion of the channel region, and at least a second gate formed on the insulating layer above at least a portion of the channel region and between the first gate and the second source/drain region.

Abstract: A programmable detection adjuster is disclosed. The programmable detection adjuster comprises a bandgap and an adjusting circuit. The bandgap comprises a power input terminal, a voltage output terminal, a main resistance and a plurality of resistors. The adjusting circuit comprises a plurality of adjusting resistors, a plurality of transistor switches, a logic controller and detection circuits; said adjusting resistors connected to the main resistance of the bandgap in series. The adjusting resistors are respectively connected to the transistor switch in parallel. The transistor switches are connected to the logic controller. The logic controller is respectively connected to the detection circuits. The detection circuit detects the corresponding resistances in the detection circuit and outputs a voltage level to the logic controller to enable the logic controller to control a conduction of the transistor switches according to a logic conversion table.

Abstract: Supply voltage level detectors are disclosed. The supply voltage level detector comprises a voltage source divider dividing a voltage source to generate a detection voltage, a bandgap reference voltage generator, a comparator comparing the detection voltage with a bandgap reference voltage generated by the bandgap reference voltage generator to determine if the voltage source is ready, a control circuit, and a forcing circuit. To ensure reliability of the comparison result, the control circuit disables the comparing device until the bandgap reference voltage is available. The forcing circuit is coupled to the output terminal of the comparing device and is controlled by the control circuit. When the comparing device is disabled, the forcing circuit forces the voltage level of the output terminal of the comparing device to a specific value indicating the voltage source is unready.

Abstract: A sawtooth wave generating apparatus includes a base frequency generating section and a frequency generating section for generating the frequency of a reference signal, a sawtooth wave forming section which forms a sawtooth wave based on the reference signal, a voltage comparator which compares the voltage value of the sawtooth wave formed by the sawtooth wave forming section with a predetermined voltage value, a phase comparator which compares the phase of the output signal from the voltage comparator with the phase of the reference signal, and a low-pass filter (LPF) which cuts out a high frequency component of the output signal from the phase comparator, and feeds back the resulting output signal to the sawtooth wave forming section.

Abstract: A driver integrated circuit for driving at least one high voltage half bridge stage. The driver including a filter circuit for filtering a signal provided to the half bridge stage, a minimum pulse width of the signal being near a constant time of the filter, wherein the filter circuit prevents distortions introduced when the signal is at its minimum pulse width from being passed to the half bridge stage.

Abstract: An input offset voltage corrector used in an operational amplifier includes a switch unit, a register unit, an offset voltage correction unit and a micro control unit. The micro control unit sets the register unit to control the switch unit to switch the input offset voltage corrector to different operating modes. If an input offset voltage corrector is set to the offset voltage correcting mode, the offset voltage correction unit will adjust the input offset voltage of the operational amplifier to output an exact signal. Furthermore, the input offset voltage corrector can adjust the input offset voltage anytime according to the operating conditions to maintain the best characteristic of the operational amplifier.

Abstract: An amplification apparatus that has a distortion detection loop that detects distortion components contained in an amplified signal to be amplified that is amplified by an amplifier 3, and a distortion removal loop that removes distortion components from the amplified signal, using the distortion components detected by the distortion detection loop, combines a reference signal (pilot signal) with the signal to be amplified, and performs control relating to distortion compensation, using said reference signal, to provide improved efficiency with respect to a configuration to perform control relating to distortion compensation, using a reference signal. A signal to be amplified is detected by amplification signal detection means 11˜13 and 21, and when it is detected by the amplification signal detection means that there is no input of a signal to be amplified, reference signal control means 21, 15 perform control to effect non-output of the reference signals.

Abstract: A power amplifying apparatus includes an input terminal configured to receive an input signal, a first power amplifier biased for class A or class AB operation which is configured to amplify the input signal, an output terminal connected to an output of the first power amplifier, a second power amplifier biased for class C operation which is configured to receive and amplify a part of the input signal, and a switch connected between an output of the second power amplifier and the output terminal.

Abstract: A radio frequency (RF) amplifier includes an RF drive adjust circuit adapted to receive an input signal and adjust at least one of the amplitude and phase thereof to output a drive-adjusted input signal; a gain element adapted to amplify the drive-adjusted input signal and to output an amplified signal; and a dynamic impedance transformer adapted to receive the amplified signal, to output an output signal, and to transform a load impedance presented to the gain element by a load in accordance with a desired amplitude of an envelope of the output signal.