Abstract: A semiconductor integrated circuit that has a quick response to changes in source/drain electrode voltage having an LDMOS transistor. The transistor has a second conduction type first well region formed in a first conduction type semiconductor substrate; a first conduction type second well region formed in the first well region; a second conduction type third well region formed in the second well region; a drain region formed in the second well region; a source region formed in the third well region; a gate electrode formed through a gate insulating film over the third well region between the drain region and the source region; and an insulating layer formed between the gate electrode and the drain region. Parasitic capacitances between the semiconductor substrate and the source region and those between the substrate and the drain region are respectively in series.

Abstract: High voltage semiconductor devices and methods for fabricating the same are provided. An exemplary embodiment of a semiconductor device capable of high-voltage operation, comprising a substrate comprising a first well formed therein. A gate stack is formed overlying the substrate, comprising a gate dielectric layer and a gate electrode formed thereon. A channel well and a second well are formed in portions of the first well. A source region is formed in a portion of the channel well. A drain region is formed in a portion of the second well, wherein the gate dielectric layer comprises a relatively thinner portion at one end of the gate stack adjacent to the source region and a relatively thicker portion at one end of the gate stack adjacent to and directly contacts the drain region.

Abstract: Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented.

Abstract: The present invention provides an integrated circuit and a method of manufacture therefore. The integrated circuit (100, 1000), in one embodiment without limitation, includes a dielectric layer (120, 1020) located over a wafer substrate (110, 1010), and a semiconductor substrate (130, 1030) located over the dielectric layer (120, 1020), the semiconductor substrate (130, 1030) having one or more transistor devices (140, 1040) located therein or thereon. The integrated circuit (100, 1000) may further include an interconnect (170, 1053) extending entirely through the semiconductor substrate (130, 1030) and the dielectric layer (120, 1020), thereby electrically contacting the wafer substrate (110, 1010).

Abstract: A semiconductor topography (10) is provided which includes a semiconductor-on-insulator (SOI) substrate having a conductive line (16) arranged within an insulating layer (22) of the SOI substrate. A method for forming an SOI substrate with such a configuration includes forming a first conductive line (16) within an insulating layer (22) arranged above a wafer substrate (12) and forming a silicon layer (24) upon surfaces of the first conductive line and the insulating layer. A further method is provided which includes the formation of a transistor gate (28) upon an SOI substrate having a conductive line (16) embedded therein and implanting dopants within the semiconductor topography to form source and drain regions (30) within an upper semiconductor layer (24) of the SOI substrate such that an underside of one of the source and drain regions is in contact with the conductive line.

Abstract: A CMOS semiconductor device having a triple well structure which can block latch-up by preventing parasitic thyristors from turning on is offered with reduced layout area. The CMOS semiconductor device includes a P-type silicon substrate, a first and a second deep N-type wells formed in a surface of the P-type silicon substrate and separated from each other, a P-type well formed in the first deep N-type well, a shallow N-type well formed in the second deep N-type well, an N-channel type MOS transistor formed on a surface of the P-type well and a P-channel type MOS transistor formed on a surface of the shallow N-type well.

Abstract: A semiconductor device having a field effect transistor formed on a semiconductor layer on an insulator, comprising: a drain electrode wiring formed over a drain region of the field effect transistor; a source electrode wiring formed over a source region of the field effect transistor; first contact plugs connecting the drain region and the drain electrode wiring; and second contact plugs which connect the source region and the source electrode wiring, and the number of which is greater than the first contact plugs.

Abstract: At an element formation surface side of a p-type Si substrate, a digital circuit and an analog circuit are provided. The analog circuit includes a p-type well and n-type wells formed at the element formation surface side of the p-type Si substrate. The analog circuit includes a deep n-type well located closer to the bottom side of the p-type Si substrate than the p-type well, so as to isolate the p-type well from a bottom-side region of the p-type Si substrate. The deep n-type well includes a first deep n-type well. The deep n-type well includes a second deep n-type well located closer to the bottom side of the p-type Si substrate than the first deep n-type well, and having an n-type impurity concentration, which is different from the first deep n-type well.

Abstract: A semiconductor device, comprising: a first transistor of a second electric conductivity type formed in a substrate including impurities of a first electric conductivity type; and a second transistor of the second electric conductivity type formed in the substrate, a source region of the second transistor being shared with a source region of the first transistor; wherein in a lower layer of a gate insulating film of the first transistor, a first offset layer of the second electric conductivity type is formed adjacent to a channel region of the first transistor, in a lower layer of a gate insulating film of the second transistor, a second offset layer of the second electric conductivity type is formed adjacent to a channel region of the second transistor, and in the source region, a first diffusion layer of the first electric conductivity type and a second diffusion layer of the first electric conductivity type in the upper layer of the first diffusion layer are formed, and wherein the second diffusion layer i

Abstract: A semiconductor substrate of a solid state imaging device is connected to a cover glass, and then a backgrind is performed so as to make the thickness smaller. On a first face of the semiconductor substrate is formed plural units which is constructed of image sensors and plural contact terminals. At positions of the contact terminals, plural through-holes are formed on the bottom side of the semiconductor substrate, and the contact terminals appear on a second surface of the semiconductor substrate. On an interconnection circuit pattern of the assembly substrate are formed stud bumps. When the semiconductor substrate is assembled onto the assembly substrate, the stud bumps enter into the through-holes to contact to the contact terminals. Thus the interconnection circuit pattern is electrically connected to the image sensors.

Abstract: A method for forming a conductive via in a semiconductor component is disclosed. The method includes providing a substrate having a first surface and an opposing, second surface. At least one hole is formed in the substrate extending between the first surface and the opposing, second surface. A seed layer is formed on a sidewall defining the at least one hole of the substrate and coated with a conductive layer, and a conductive or nonconductive filler material is introduced into the remaining space within the at least one hole. A method of forming a conductive via through a substrate using a blind hole is also disclosed. Semiconductor components and electronic systems having substrates including the conductive via of the present invention are also disclosed.

Abstract: The present invention relates to a coating composition for insulating film production, a preparation method of a low dielectric insulating film using the same, a low dielectric insulating film for a semiconductor device prepared therefrom, and a semiconductor device comprising the same, and more particularly to a coating composition for insulating film production having a low dielectric constant and that is capable of producing an insulating film with superior mechanical strength (elasticity), a preparation method of a low dielectric insulating film using the same, a low dielectric insulating film for a semiconductor device prepared therefrom, and a semiconductor device comprising the same. The coating composition of the present invention comprises an organic siloxane resin having a small molecular weight, and water, and significantly improves low dielectricity and mechanical strength of an insulating film.

Abstract: An insulating tube includes a underlying insulating film, a first sidewall insulating film disposed on the underlying insulating film, a second sidewall insulating film disposed on the underlying insulating film, opposite to the first sidewall insulating film so as to provide a cavity between the first and second sidewall insulating films having the same height as the first sidewall insulating film, and an upper insulating film provided over the first and second sidewall insulating films.

Abstract: An apparatus and method providing flexibility to a silicon chip carrier which, in at least one embodiment, comprises multiple chips and a silicon chip carrier having thinned regions between some adjacent chips, thus, allowing for increased flexibility and reduced package warpage.

Abstract: The present invention provides an varactor, a method of manufacture thereof. In an exemplary embodiment, the varactor includes a semiconductor substrate and well of a first and second conductivity type, respectively. A conductive region in the well has a same conductivity type as the well but a lower resistivity than the well. At least a portion of the well is between at least two sides of the conductive region and an area delineated by an outer perimeter of a conductive layer over the well. Such varactors have a lower series resistance and therefore have an increased quality factor.

Abstract: Methods are disclosed for forming ultra shallow junctions in semiconductor substrates using multiple ion implantation steps. The ion implantation steps include implantation of at least one electronically-active dopant as well as the implantation of at least two species effective at limiting junction broadening by channeling during dopant implantation and/or by thermal diffusion. Following dopant implantation, the electronically-active dopant is activated by thermal processing.

Abstract: Packages for an optical integrated circuit die and a method for making such packages are disclosed. The package includes a die, a die pad, a plurality of lead fingers, and an encapsulating dielectric material. The downward second pad surface of the die pad bearing an integrated circuit is encapsulated by a bottom encapsulating dielectric material. The top encapsulating dielectric material provides the function for protecting the leadframe from severe environment. The top encapsulating dielectric material can be neglected if there is no threat on the integrated circuit die and the leadframe. Multiple of lead fingers are mounted on the printed circuit board. A portion of the printed circuit board is removed in order to provide an optical path for the light beam transmitted from a light source through the transparent bottom encapsulating dielectric material into the integrated circuit die. The method of making a package includes forming a leadframe including a die pad and a plurality of lead fingers.

Abstract: An integrated circuit package having a die pad with a first face and a second face, a plurality of inner leads, and a plurality of sides between the first face and the second face. The plurality of inner leads is disposed substantially co-planer with and substantially around the die pad. The package also comprises a plurality of outer leads disposed substantially co-planar with and substantially around the plurality of inner leads and the die pad, so that the sides of each of the plurality of outer leads are offset from the sides of each of the plurality of inner leads. A first adhesive layer disposed on the first face of the die pad and a second adhesive layer disposed on the first faces of each of the plurality of inner leads. An IC chip is coupled to the first face of the die pad through the first adhesive layer and to the plurality of inner leads through the second adhesive layer. The package further comprises wires linking the inner leads and outer leads to the IC chip.

Abstract: An improved wire bond is provided with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductive lead of a TAB tape bond with the bond pad of a semiconductor device. More specifically, an improved wire bond is described wherein the bond pad on a surface of the semiconductor device comprises a layer of copper and at least one layer of metal and/or at least a barrier layer of material between the copper layer and one layer of metal on the copper layer to form a bond pad.

Abstract: Embodiments of the present invention include an apparatus, method, and/or system for an integrated circuit package with signal connections on the chip-side of the package structure.

Abstract: A multi-chip image sensor module includes a first substrate; a photosensitive chip arranged on an upper surface of the first substrate; a lens holder mounted on the upper surface of the first substrate to encapsulate the photosensitive chip; a lens barrel arranged within the lens holder and formed with a chamber and an opening communicating with the chamber; an aspheric lens and a transparent layer placed within the chamber; a second substrate mounted on the first substrate and electrically connected to the first substrate; and a lower chip located on a second surface of the second substrate.

Abstract: A system may include an integrated circuit die, an integrated circuit package coupled to the integrated circuit die, mold compound in contact with the integrated circuit die and the integrated circuit package, and an interconnect coupled to the integrated circuit package. A first portion of the interconnect may be in contact with the mold compound, a second portion of the interconnect might not contact the mold compound, and a third portion of the interconnect may be in contact with the integrated circuit package.

Abstract: An electronic component, in which a chip can be mounted on a certain predetermined place of the package at a high accuracy level, which package having a stepped level-difference in the inner wall of a cavity. The package is provided with a stepped level-difference in the inner wall surface, and an internal contact electrode formed on the upper surface of the stepped level-difference. At the bottom of the package is a shield electrode, on which a chip is mounted via an adhesion layer. The chip and the internal contact electrode are electrically connected by an interconnection wire. Location aligning for the chip and the interconnection wire, at least either one of these, is conducted by making use of a region, which is non-electrode portion, provided on the inner bottom surface of the package.

Abstract: A semiconductor device includes a plastic package, at least one semiconductor chip and a rewiring level. The rewiring level includes an insulating layer and a rewiring layer. The rewiring layer includes either signal conductor paths and ground or supply conductor paths arranged parallel to one another and alternately, or only signal conductor paths arranged parallel to one another. In the latter case, an electrically conducting layer of metal which can be connected to ground or supply potential is additionally provided as a termination of the rewiring level or in the form of a covering layer.

Abstract: A thermally conductive structure for a semiconductor integrated circuit and a method for making the structure. The structure comprises one or more vertical and/or horizontal thermally conductive elements disposed proximate a device for improving thermal conductivity from the device to a substrate of the integrated circuit. In one embodiment a heat sink is affixed to the integrated circuit for heat flow from the integrated circuit. The method comprises forming openings in material layers overlying the semiconductor substrate, wherein the openings are disposed proximate the device and extend to the substrate. A thermally conductive material is formed in the openings to provide a thermal path from the device to the substrate.

Abstract: An integrated chip package structure and method of manufacturing the same is by adhering dies on an organic substrate and forming a thin-film circuit layer on top of the dies and the organic substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.

Abstract: A multi-layered circuit board a built-in component including multiple terminals, at least one signal pad formed on a top surface of the multi-layered circuit board for signal transmission, each of the at least one signal pad corresponding to one of the multiple terminals, and at least one test pad formed on the top surface of the multi-layered circuit board, each of the at least one test pad corresponding to one of the at least one signal pad for testing an electric path extending from the one signal pad through the one terminal to the each of the at least one test pad.

Abstract: A magnetic memory device exhibits improved writing characteristics by providing a magnetic flux concentrator which efficiently applies the magnetic field, which is generated by the writing word line, to the memory layer of the TMR element. The magnetic memory device (1) is composed of the TMR element (13), the writing word line (the first wiring) (11) which is electrically insulated from the TMR element (13), and the bit line (the second wiring) (12) which is electrically connected to the TMR element (13) and intersecting three-dimensionally with the writing word line (11), with the TMR element (13) interposed therebetween. The magnetic memory device (1) is characterized as follows. The magnetic flux concentrator (51) of high-permeability layer is formed along at least the lateral sides of the writing word line (11) and the side of the writing word line (11) which is opposite to the side facing the TMR element (13).

Abstract: A semiconductor device has a semiconductor substrate having first and second surface, a first resin film formed on the first surface of the semiconductor substrate and a second resin film formed on the second surface of the semiconductor substrate. A projection electrode or an interconnection is formed on the first surface of the semiconductor substrate, the second resin film is made of low elastic resin which is capable of absorbing an impact applied to the second surface of the semiconductor substrate and the second resin film is thinner than the semiconductor substrate.

Abstract: A semiconductor device includes: a base member; a solder layer; and a semiconductor chip disposed on the base member through the solder layer. The chip has an in-plane temperature distribution when the chip is operated. The chip has an allowable maximum temperature as a temperature limit of operation. The in-plane temperature distribution of the chip provides a temperature of the chip at each position of a surface of the chip. The temperature margin at each position is obtained by subtracting the temperature of the chip from the allowable maximum temperature. The solder layer has an allowable maximum diameter of a void at each position, the void being disposed in the solder layer. The allowable maximum diameter of the void at each position becomes larger as the temperature margin at the position becomes larger.

Abstract: Conductive sidewall spacer structures are formed using a method that patterns structures (mandrels) and activates the sidewalls of the structures. Metal ions are attached to the sidewalls of the structures and these metal ions are reduced to form seed material. The structures are then trimmed and the seed material is plated to form wiring on the sidewalls of the structures.

Abstract: A solar-powered wind chime has a solar energy system for powering an electrical subsystem. The electrical subsystem may include lighting elements for illuminating the wind chime and the area around the wind chime in a decorative and functional manner.

Abstract: An electromechanical generator comprising an electromechanical device for converting mechanical vibrational energy into electrical energy, the electromechanical device having a vibratable mass adapted to resonate with an oscillation amplitude at a frequency and a regulator for regulating the oscillation amplitude to a value not greater than a maximum threshold.

Abstract: An exemplary embodiment includes a wind turbine system. The wind turbine system includes a wind turbine generator operable to supply wind turbine power to a utility system. A converter is coupled to the wind turbine generator and the utility system. The wind turbine system also includes a controller comprising an internal reference frame of the wind turbine generator, coupled to the converter, and configured for modulating flow of power through the converter in response to frequency disturbances or power swings of the utility system relative to the internal reference frame.

Abstract: A decorative windmill having a solar energy system for powering an electrical subsystem is disclosed. The electrical subsystem may include lighting elements for illuminating the windmill and the area around the windmill in a decorative and functional manner.

Abstract: Disclosed relates to a wind power generation apparatus and, more particularly, to a multi-direction wind power generation apparatus, which can be easily, solidly and largely manufactured and also repaired readily, for enhancing the efficiency of power generation by making most us of wind and by lessening the wind resistance. The object of the present invention is to provide the multi-direction wind power generation apparatus that can generate electricity against the wind blowing from various directions, enhance the efficiency of electric generator by lessening the wind resistance maximally, and increase the solidity of the apparatus by establishing separate supporters for supporting the upper/lower support frames.

Abstract: A wind turbine is provided that passively cools an electrical generator. The wind turbine includes a plurality of fins arranged peripherally around a generator house. Each of the fins being oriented at an angle greater than zero degrees to allow parallel flow of air over the fin. The fin is further tapered to allow a constant portion of the fin to extend beyond the air stream boundary layer. Turbulence initiators on the nose cone further enhance heat transfer at the fins.

Abstract: A wind-driven power source comprises a propeller-driven rotor structure and a stator structure carrying clusters of copper-wire wound ferromagnetic cores as voltage generators. The cores are arranged in pairs spaced apart by hard rubber rollers which engage the inside surface of a load ring forming part of the rotor structure. The overall rotor structure comprises the large diameter load ring, a smaller diameter root ring and a plurality of aerodynamic blades extending radially outwardly from the root ring and secured either by saddle blocks or integral bonding to the load ring. The load ring may be aluminum or plastic. Permanent magnets are arranged around the load ring to interact with the voltage generator structures to produce three-phase electricity.

Abstract: A power supply circuit contains a plurality of DC-DC converter control loops that provide respectively different control signals. A plurality of output driver stages of given current drive capabilities have their inputs programmably connectable via a set of switches to control signals that may be generated by any of the converter control loops. The output of each output driver stage is externally selectively connectable to any of plural output voltage ports, so that each output voltage port is capable of supplying any of the respectively different output voltages associated with the voltage control signals generated by the DC-DC converter control loops, and has an output current capability that depends upon which output driver stages are coupled to it.

Abstract: A power converter includes a steady-state controller for outputting a first voltage command such that a detected power value matches a power command, a transient controller for outputting a second voltage command such that a voltage detected before the occurrence of a fault is maintained when the fault occurs, and a voltage command selector for switching the voltage command in such a way that the first voltage command is output when no power fault is detected and the sum of the first and second voltage commands is output when any power fault is detected.

Abstract: A backup power supply system supplies power from a first ac power source in normal condition. Once the first ac power source is abnormal or fails, the system automatically turns off the first ac power source and turns on a second ac power source with null transfer time. When the first ac power source is normal, a dc/ac power inverter is controlled to supply an approximately null current such that a mechanical switch is allowed to be closed and no circulating current is generated between the first ac power source and the dc/ac power inverter. Since the mechanical switch is continuously closed, and requires no switching operation, the backup power supply system can supply the backup power with a null transfer time.

Abstract: A system comprises a converter to produce an output voltage from at least a first input voltage and a second input voltage, and a selector to select a first circuit path in the converter to produce the output voltage from the first input voltage, and to select a second circuit path in the converter to produce the output voltage from the second input voltage.

Abstract: A method and a small profile apparatus for generating high voltage impulses. Integration of the radiating antenna with the impulse source structure makes possible the small size of the present invention.

Abstract: A single state detector circuit can quickly detect short-circuit and open-circuit abnormalities of a load controlled by a power transistor. A DC power supply, the load and the power transistor are serially connected with one another, so that a switching terminal voltage of the power transistor is binarized into high and low levels by the state detector. The power transistor is linearly controlled by a constant-current control circuit so as to suppress an excessive current, and power supplied to the power transistor is interrupted by an overheat interruption circuit. Upon occurrence of a short-circuit in the load during generation of an energization command, a switching terminal voltage of the power transistor becomes stabilized at a high level without intermittent operation, which is detected by the state detector. Upon occurrence of an open-circuit during generation of a deenergization command, a low switching terminal voltage is detected by the state detector.

Abstract: In a linear motor, a can has a two-layer structure including an inner can 2 and an outer can 3, and an inner passage 7 formed between an armature winding 9 and the inner can 2 and an outer passage 8 formed between the inner can 2 and the outer can 3 are constituted by each can. Communicating portions 7A and 8A for causing the inner passage 7 and the outer passage 8 to communicate with each other are provided in the vicinity of a refrigerant supply port 5 in each of the cans 2 and 3 in such a manner that a refrigerant supplied from the refrigerant supply port 5 branches into the inner passage 7 and the outer passage 8 and thus flows. Consequently, it is possible to obtain a linear motor armature and a linear motor having a high cooling capability which can prevent the deformation of the can by using a conventional inactive refrigerant to improve the passage for the refrigerant.

Abstract: Certain exemplary embodiments comprise a system comprising: a motor stator comprising: a motor frame comprising a core shell adapted to surround a stator core comprising: a plurality of panels; a plurality of apertures located in one or more of said panels; and a first plurality of non-destructively removable plates adapted to effect a first direction of stator core air flow by impeding airflow through a first selectable sub-plurality of said plurality of apertures.

Abstract: An electric drive unit includes an electric motor for driving a fan. The motor has an electronic control module. An impeller wheel for producing a working air flow is mounted by bearings on an axle of the electric motor. The hub of the impeller wheel has at least one preferably two walls enclosing a cooling space or cooling space portions. At least one cooling surface of a cooling body is in contact with components of the electronic control module and projects into the cooling space. A gap formed between the hub of the impeller wheel and a carrier section communicates with an inner hub space. Holes (43, 322) communicating with the hub inner space are provided in at least one component of the electric drive unit. When the impeller wheel rotes a convection cooling air flow is established between the gap and the holes.

Abstract: An automotive alternator in which a fan rotating together with a rotor to direct air from a suction aperture into a case, blow the air centrifugally, and discharge the air externally through a discharge aperture has a blade including an interposed portion extending axially from an end surface of a pole core between an adjacent pair of claw-shaped magnetic poles. For this reason, cooling of a rotor coil and a stator coil is improved by improving capacity of the fan in a limited space, thereby enabling output to be improved.

Abstract: A brushless motor as an example of the invention has a stationary assembly 2 having a first housing member 10 made of a ferromagnetic material and a stator 20 held in the first housing member 10, and a rotor 6 having a rotor magnet 70 facing the stator 20. A annular shield plate 80 held by the rotor 6 is disposed between the rotor magnet 70 and the first housing member 10 and, further, an outer circumferential face 80a of the shield plate 80 is disposed between a magnetically neutral area 46 in the radial direction in the lower end of the rotor magnet 70 and the outer circumferential face of the rotor magnet 70.

Abstract: A motor includes a casing and a holder which support a rotation shaft. A concave groove is formed in the holder near the inner periphery of the holder. The concave groove accommodates a positive temperature coefficient thermistor functioning as an overcurrent protection device. A tapered cutout surface is formed on the outer wall of the holder so that the cutout surface is inclined at 45 degrees with respect to a line passing through the rotation shaft and the groove portion of the holder has a maximum length of the holder in its axis direction. A multi-direction input device includes these two motors functioning as driving sources to provide a force feedback to an operation lever. The first and second motors are disposed such that lines passing through their rotation shafts are orthogonal to each other and cutout surfaces are opposed to each other with an intersection of the lines therebetween.