Abstract: A method for calibrating a filter begins with the filter filtering a first signal having a first frequency to produce a first filtered signal, wherein the first frequency is in a known pass region of the filter. The processing continues by measuring signal strength of the first filtered signal to produce a first measured signal strength. The processing continues with the filter filtering a second signal having a second frequency to produce a second filtered signal, wherein the second frequency is at a desired corner frequency of the filter. The processing continues by measuring signal strength of the second filtered signal to produce a second measured signal strength. The processing continues by comparing the first measured signal strength with the second measured signal strength to determine whether the filter has attenuated the second signal by a desired attenuation value with respect to the first signal.

Abstract: A moisture sensing circuit for a clothes dryer in which clothes tumble during drying has a pair of spaced apart electrode sensors for sensing the electrical resistance of the clothes when the clothes contact the electrodes. The circuit has an active filter for suppressing noise related to the operating line frequency of the clothes dryer to provide a filtered voltage signal representative of voltage drop across the electrode sensors with the line frequency noise suppressed.

Abstract: Method and apparatus using a retention arrangement with a potting enclosure for holding a plurality of probes by their retention portions, the probes being of the type having contacting tips for establishing electrical contact with pads or bumps of a device under test (DUT) to perform an electrical test. The retention arrangement has a top plate with top openings for the probes, a bottom plate with bottom openings for the probes, the plates being preferably made of ceramic with laser-machined openings, and a potting enclosure between the plates for admitting a potting agent that upon curing pots the retaining portions of the probes. In some embodiments a spacer is positioned between the top and bottom plates for defining the potting enclosure. Alternatively, the retention arrangement has intermediate plates located in the potting enclosure and having probe guiding openings to guide the probes.

Abstract: Techniques for performing wafer-level burn-in and test of semiconductor devices include a test substrate having active electronic components such as ASICs mounted to an interconnection substrate or incorporated therein, metallic spring contact elements effecting interconnections between the ASICs and a plurality of devices-under-test (DUTs) on a wafer-under-test (WUT), all disposed in a vacuum vessel so that the ASICs can be operated at temperatures independent from and significantly lower than the burn-in temperature of the DUTs. The spring contact elements may be mounted to either the DUTs or to the ASICs, and may fan out to relax tolerance constraints on aligning and interconnecting the ASICs and the DUTs. Physical alignment techniques are also described.

Abstract: A tile used to hold one or more probes for testing a semiconductor wafer. The tile has one or more sites for inserting one or more probes to test the semiconductor wafer. Each site has one or more holes. Each hole is coupled with a slot forming an angle. A probe is inserted into the tile from a top of the tile through the hole and seated on the slot. The probe has a probe tip. The probe tip is in contact with the semiconductor wafer at one end of the slot at a bottom of the tile. The probe tip is aligned with an X and Y coordinates of a bond pad on the semiconductor wafer.

Abstract: The present application relates to apparatus and methods for burn-in and other diagnostics performed on integrated circuits. In one embodiment, the invention includes a plurality of sockets, each to hold an integrated circuit (IC), and coupling power to the respective IC from a remote power supply, a plurality of voltage detectors, each coupled to a socket to sense the voltage of the power coupled to the respective IC, and a plurality of remote voltage regulators, each coupled between the power supply and a respective socket, to receive the sensed voltage from the respective voltage detector and to adjust the voltage of the respective coupled power in accordance therewith.

Abstract: A semiconductor apparatus includes a reset terminal to input a reset control signal to reset an internal circuit, a reset detector to generate a reset clear signal to clear a reset of the internal circuit according to the input reset control signal and a mode capture unit to retain a test mode to test an operation of the internal circuit according to a signal input to the reset terminal.

Abstract: A protection circuit comprises: at least one shielded line arranged to cover an area to be protected over a semiconductor device, the at least one shielded line having only one route from a start point to an end point; a signal generator for applying a signal to the start point of the shielded line; a counter which starts measurement of time in response to application of the signal to the start point of the shielded line by the signal generator and which ends measurement of the time in response to arrival of the signal at the end point of the shielded line; and a comparator for comparing the time measured by the counter with a reference value to output a fraud detection signal according to a result of the comparison.

Abstract: A method for a burn-in test includes steps (a) and (b). In the step (a), an operation test of a first semiconductor device is executed through first probes provided on a probe card. In the step (b), a stress is applied to a second semiconductor device through second probes provided on the probe card while the operation test is executed.

Abstract: Regulating a direct current-to-direct current (DC-DC) converter, a semiconductor switch having an improved current sensing technique is used to switch a DC voltage input at a predefined frequency. The switch includes a control pin to receive a control signal for controlling a current flowing between an input pin and an output pin. The switch also includes a Kelvin sense pin electrically coupled to an output pad located on a semiconductor die of the device for sensing the current. An electrical path from the output pad to the output pin in the form of a conductive lead wire has a predefined resistance. The current is Kelvin current sensed using the predefined resistance to tightly control deviation in the current beyond a predefined range.

Abstract: A system and method for testing devices. The system includes a plurality of pads and a decoder coupled to a plurality of devices. The decoder is configured to receive a plurality of selection signals from the plurality of pads and select a device from the plurality of devices based on at least information associated with the plurality of selection signals. Additionally, the system includes one or more pads connected to the selected device. At least one of the one or more pads is not connected to any of the plurality of devices other than the selected device. The one or more pads are used for testing the selected device.

Abstract: An electro-optical device includes a first substrate that holds an electro-optical material, a first IC that is mounted on the first substrate and that has a plurality of first terminals, a plurality of second terminals that are formed on the first substrate to be connected to the plurality of first terminals, respectively, a plurality of wiring lines formed on the first substrate, first connection state diagnostic terminals that are included in the plurality of first terminals and that are used for diagnosing connection states between the first terminals and the second terminals, second connection state diagnostic terminals that are included in the plurality of second terminals and that are connected to the first connection state diagnostic terminals, respectively, a connection state diagnostic unit that is provided in the first IC to diagnose whether the first and second connection state diagnostic terminals are electrically connected to each other, and a connection state diagnosis result output unit that i

Abstract: Methods and structures for design security in configurable devices are described. In some embodiments, a configurable device may be placed in an unsecured mode allowing for access to configuration data and other diagnostic functions during development and production phases. Once the device is finalized, it may be placed in a secure mode that disables a configuration path and enables a bypass path, thereby securing the configuration data. In some embodiments, the configurable device may be a programmable logic device, such as a complex programmable logic device.

Abstract: A method for trimming impedance matching devices in high-speed circuits includes determining an electrical parameter associated with a first tantalum nitride (TaN) resistor used as an impedance matching device in the circuit under test, and comparing the determined electrical parameter associated with the first TaN resistor to a desired design value of the electrical parameter. The resistance value of the first TaN resistor is altered by application of a trimming voltage thereto, wherein the trimming voltage is based on a voltage-resistance characteristic curve of the first TaN resistor. It is then determined whether the altered resistance value of the first TaN resistor causes the electrical parameter to equal the desired design value thereof, and the altering of the resistance value of the first TaN resistor by application of a trimming voltage is repeated until the electrical parameter equals the desired design value thereof.

Abstract: An adjustable termination resistor includes a reference resistor, a current mirror circuit, a calibration transistor-resistor array, a digital code generator, a comparator, a decision and latch circuit and a termination resistor. The mirror current generated from the current mirror circuit flows through the calibration transistor-resistor array to result in a comparing voltage across the calibration transistor-resistor array. The resistance of the calibration transistor-resistor array is determined according to a digital code generated from the digital code generator. The voltage level outputted from the comparator is changed from a first state to a second state when the digital code generator up counts to a target digital code such that the comparing voltage is just greater than the reference voltage. The decision and latch circuit records the target digital code into therein. The resistance of the termination resistor is adjustable according to the target digital code.

Abstract: A highly economical alterable ASIC implements partitioned segments of an ASIC design in a smaller Silicon foot-print, each segment utilizing the entire IC. The device is able to switch quickly between the multiple segments with global control signals, without incurring long delays to reconfigure configuration memory. The alterable ASIC comprises programmable logic blocks and a configuration circuit with multiple sets of configuration memory, each set programmed to hold an optimized segment. Either random access memory (RAM) or mask configured read only memory (ROM) store the partitioned segments.

Abstract: A method and computer readable medium for implementing redundancy on a programmable logic device with improved interconnect efficiency. The method and medium includes: determining if a first wire segment of a first wire channel requires a programmed connection to a resource in the row furthest from the buffer driving the first wire segment and spanned by the first wire segment; reserving a next segment in the first channel if the first wire segment of the first wire channel requires a programmed connection to a resource in the row furthest from the buffer driving the first wire segment and spanned by the first wire segment; and assuming a maximum delay path including the programmable signal propagation delay of the reserved next segment and a stitching element coupled between the first segment and the reserved next segment of the first channel.

Abstract: A multi-product integrated circuit die includes at least two different portions, of which at least one portion can be deliberately rendered non-operational in some manner (e.g., non-functional, inaccessible, and/or non-programmable) within the package. A selection code storage circuit stores a product selection code. A first value of the product selection code selects the option where both the first and second portions of the first die are operational. A second value of the product selection code selects the option where only the first portion of the first die is operational. The selection code storage circuit can include non-volatile memory or a fuse structure, or the product selection code can be configured as a package bonding option. The product selection code can also enable boundary scan for the operational portion of the die, and omit from the boundary scan chain any portions of the die that are deliberately rendered non-operational.

Abstract: A PLD is configurable to efficiently implement a wide variety of user functions. The PLD includes a programmable interconnect circuit, programmable logic circuits, one-bit registers, selector circuits, and input/output blocks. The programmable interconnect circuit is configurable to connect the signal lines of its output ports to the signal lines of its input ports. The programmable logic circuits are configurable to implement a programmable function generating one-bit signal values from a respective output port of the programmable interconnect circuit. The one-bit registers store a respective one of these one-bit signal values. The programmable selector circuits are each coupled to output ports of a plurality of the one-bit registers, with each of these one-bit registers coupled to a respective one of the programmable logic circuits.

Abstract: Integrated circuit devices are provided that include power detection circuits that indicate whether power supplies have reached functional voltage levels. The power detection circuits include latches coupled to power supplies that can detect whether all the power supplies have reached functional voltage levels, logic circuits to provide appropriate output signals, and well bias circuits that supply current to the power detection circuits. Well bias circuits provide current from first power supplies to reach functional voltage levels so that indication may be provided from the power detection circuit without requiring functional voltage levels of all power supplies. Outputs from power detection circuits can be combined with control signals, for various applications. Applications include holding an integrated circuit device in reset until power supplies have reached functional voltage levels.

Abstract: An input signal is routed to a first logic one reference signal generator or alternatively routed to a second logic one reference signal generator based at least one a voltage level of the input signal. When the voltage level of the input signal is less than a threshold value, the first logic one reference signal generator selectively generates a first logic one reference signal. When the voltage level of the input signal is greater than or equal to the threshold value, the second logic one reference signal generator alternatively generates a second logic one reference signal. The first and second logic one reference signals may be used to control a first voltage scaling circuit that drives a scaled output signal having a logic one value corresponding to the voltage level of the first logic one reference signal.

Abstract: A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a first logic block, and a second logic block. The first logic block consists of a network of p-type transistors for implementing a predetermined logic function. The p-type transistor network has an outer diffusion connection, a first network gate connection, and an inner diffusion connection. The outer diffusion connection of the p-type transistor network is connected to the first dedicated logic terminal, and the first network gate connection of the p-type transistor network is connected to the first logic input. The second logic block consists of a network of n-type transistors which implements a logic function complementary to the logic function implemented by the first logic block. The n-type transistor network has an outer diffusion connection, a first network gate connection, and an inner diffusion connection.

Abstract: A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.

Abstract: A driver circuit is provided, which includes a differential amplifier whose output signal controls the driving input signal, a reference signal generator that supplies a reference input of the differential amplifier, an external feedback that applies a signal, which is dependent on the output signal, to a feedback input of the differential amplifier, an adapter circuit, and an internal feedback activated in a compensation mode as an alternative to the external feedback, which internal feedback provides a signal to both the feedback input and the adapter circuit even for input signals that do not exceed the first threshold. The adaptor circuit generates and stores a compensation signal that compensates an offset signal acting alone at the reference input when the reference signal generator is switched off, and feeds the stored compensation signal, together with a reference signal, to the reference input or feedback input when the external feedback is activated.

Abstract: An integrated circuit has circuitry and pins coupled to the circuitry. One of the pins is an internal reference voltage pin having a pin signal that is set at a level outside of a normal range for the pin signal so that the integrated circuit is indicated to reset and wherein the internal reference voltage pin is normally used by the integrated circuit for internally generating a reference voltage.

Abstract: A phase-lock loop generates an output clock signal from an input clock signal. The output clock signal is coupled through a clock tree and is fed back to a phase detector, which compares the phase of the output clock signal to the phase of the input clock signal. The output clock signal is generated by a voltage controlled oscillator having a control input coupled to receive an output from the phase detector, and a frequency multiplier coupled to the output of the voltage controlled oscillator. As a result, the CLKOUT signal generated by the frequency multiplier has a relatively high frequency while the voltage controlled oscillator, by operating at a relatively low frequency, uses relatively little power.

Abstract: A slew-rate adjusting apparatus for use in a semiconductor memory device includes: a slew-rate modulation signal generator for generating a slew-rate modulation signal according to the number of control codes having a first logic level among a plurality of control codes, which are programmable at an exterior; and a pre-driver for adjusting a slew rate of a data signal by changing the number of switching elements turned on in response to the slew-rate modulation signal.

Abstract: A digital storage element comprises a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a slave transparent latch coupled to the master transparent latch. The slave transparent latch comprises dedicated functional data and scan data output ports. The master and slave transparent latches have opposite transparent polarities when in a functional mode and have the same polarities (e.g., positive level sense) when in a scan mode. The transparent polarity of a transparent latch defines the state of a clock to that latch for which the transparent latch is transparent.

Abstract: A scan flip-flop circuit including an input section employing a dynamic circuit and an output section employing a static circuit, capable of latching in data within a period of a pulse width that is shorter than the clock cycle, wherein only three N-type transistors are connected in series in the input section employing a dynamic circuit. A data signal is input directly to one of the three N-type transistors. On the other hand, a test input signal is input to an AND/OR inverter circuit. The AND/OR inverter circuit receives, as a control signal, the potential of the node obtained as the clock signal passes through two inverter circuits. Therefore, there is required only a short hold time for the test input signal.

Abstract: In a circuit in which a signal arrival time with respect to a register is different in accordance with the change of a delay time of the circuit, a mechanism capable of adjusting a clock signal of the register is previously provided to deal with the case in which a set-up time in the register is not satisfied due to an increase of the delay time, and the delay time of the clock signal is changed in response to the change of the delay time of the circuit in respective modes. Thereby, the set-up time of data in the register can be satisfied, and an operation frequency of the circuit can be prevented from lowering.

Abstract: A high-frequency switch circuit has a plurality of high-frequency switches for passing and blocking a high-frequency signal between an input terminal and an output terminal depending on a control potential applied as a control signal, a high-frequency detecting terminal for detecting high-frequency signal passing through the high-frequency switch which is in ON-state, and a voltage boosting circuit for generating a potential for increasing the control potential applied to the high-frequency switch which is in ON-state in order to increase difference between the control potential applied to the high-frequency switch which is in an ON-state and the control potential applied to the high-frequency switch which is in an OFF-state, depending on an intensity or amplitude of the detected high-frequency signal.

Abstract: A method and apparatus for stabilizing the charge on a floating gate in a floating gate reference voltage generator. After an initial high voltage set mode, the method and apparatus allows for a controlled ramp down sequence to ramp down the voltages at the floating gate erase and program electrode generated by first and second bias sources coupled thereto, such that, when these bias sources are completely shut down in the generator, a more accurate voltage is set on the floating gate. The first bias source is preferably a voltage source and the second bias source is preferably a current source. The voltage at the erase electrode that is coupled to the floating gate is controlled during the ramp down sequence by shutting off the current source coupled thereto while allowing a feedback circuit in the generator to remain active.

Abstract: A floating gate circuit having a floating gate and a level shift circuit. A first tunneling device formed between a first and second tunnel electrode is included for removing electrons from the floating gate. Electrons are injected onto the floating gate without the use of a tunneling device, e.g., using avalanche injection. A first circuit is coupled to the floating gate for generating an output voltage at an output terminal. The level shift circuit has a second tunnel device coupled between the output terminal and the first tunnel electrode. The second tunnel device is for tracking changes in the characteristics of the first tunneling device connected to the floating gate. The level shift circuit level shifts the output of the floating gate circuit to a voltage that enables the tunnel device coupled to a floating gate to precisely set the floating gate to a desired voltage during a set mode.

Abstract: An integrated circuit includes a functional circuit module operating at a voltage range between a first voltage level and a second voltage level lower than the first voltage level. A power supply switch module, coupled between the functional circuit module and one or more power supplies, is controlled by one or more controlling biases of voltage levels outside the voltage range between the first and second voltage levels for more fully turning on and off the power supply switch module than biases that are within the range between the first and second voltage levels do.

Abstract: A voltage pumping device is disclosed. The device may include a voltage level detector for detecting a level of a voltage fed back thereto and generating a voltage pumping enable signal according to the detected voltage level, an oscillator for operating in response to the voltage pumping enable signal and generating a desired pulse signal in a normal operation mode, a clock supply controller for receiving an external clock signal, operating in response to the voltage pumping enable signal and outputting the external clock signal in a low-power operation mode, and a voltage pump for performing a voltage pumping operation in response to the pulse signal from the oscillator in the normal operation mode and performing the voltage pumping operation in response to the clock signal from the clock supply controller in the low-power operation mode.

Abstract: Linear-in-dB current generators having a maximum gain with least gain error. A first transistor is coupled between a first node and a first power voltage, and a first resistor is coupled between the first transistor and a second node. A second transistor is coupled between the second node and a second power voltage and comprises a control terminal coupled to the first node, and a third transistor comprises a first terminal coupled to the second power voltage, and a control terminal coupled to the first node. A second resistor is coupled between the third transistor and a third node, and a fourth transistor comprises a first terminal coupled to the first terminal, and a control terminal coupled to the third node. A first current source and the second current source are coupled to the second node and the third node respectively, and a reference current source is coupled to the first node.

Abstract: An ultra wideband filter is provided that filters an input signal using a pair of cross-coupled transistors with a small size and small power consumption. The ultra wideband filter includes a reference current generator unit generating a reference current using a bias signal of a predetermined level, a transconductor unit that is biased by the reference current and converts a predetermined input voltage into a current of a predetermined amount to output the current if the input voltage is applied thereto, and a filter unit that outputs a predetermined output voltage corresponding to the output current of the transconductor unit using a plurality of cross-coupled transistors and capacitors. The filter unit may include cross-coupled nMOS and pMOS transistors, and first and second capacitors respectively connected to respective drain terminals of the nMOS and pMOS transistors. Accordingly, the ultra wideband filter can be designed in a minimum size.

Abstract: A clock signal preamplifier comprises complementary pairs of differentially coupled transistors, with an output signal coupled to an inverter further comprising a totem-pole arrangement of complementary MOSFET transistors. The input signal to the preamplifier is typically sinusoidal, and the output signal is rectangular. Preferably, the differentially coupled transistors are bipolar, and a pair of diode clamper circuits with bipolar transistors is preferably coupled to the complementary pairs of differentially coupled transistors. A reference voltage source is coupled to the control terminals of the clamper transistors. A reference voltage source, which preferably comprises a totem-pole arrangement of complementary MOSFET transistors with its output node is coupled to its input node, provides a reference voltage for the diode clamper circuits.

Abstract: The chopper stabilized amplifier circuit includes: an amplifier; a first current mirror coupled to an output of the amplifier through a first switch; a second current mirror coupled to the output of the amplifier through a second switch, wherein the first switch is operated out of phase with the second switch; and a summing node for combining currents from the first and second current mirrors.

Abstract: A switched-capacitor amplifier circuit including first and second pairs of sampling capacitors for sampling a pair of input signals includes a voltage regulator coupled to receive a first reference voltage and generate a first regulated output voltage related to the first reference voltage and independent of a first power supply voltage; a clock signal generator generating first and second clock signals referenced to the first power supply voltage and third and fourth clock signals referenced to the first regulated output voltage; and a first set of switches coupling the bottom plates of the sampling capacitors to the amplifier, the first set of switches being controlled by the third and fourth clock signals. The circuit may further include a second set of switches coupling the top plates of the sampling capacitors to the input signals, the second set of switches being controlled by the first and second clock signals.

Abstract: The present invention is directed to a comparator circuit for use with in-phase and quadrature phase signals and a method of comparing a resultant vector of the in-phase and quadrature phase signals. In one embodiment, the comparator circuit includes a non-titled comparison circuit that compares a resultant vector of the in-phase and quadrature phase signals to vertical and horizontal comparison boundary member pairs. The comparator circuit also includes a tilted comparison circuit, coupled to the non-tilted comparison circuit, that compares the resultant vector to comparison boundary member diagonals coupled to the vertical and horizontal comparison boundary member pairs. The comparator circuit may still further include a combiner circuit that provides a comparison signal based on signals from the non-tilted and tilted comparison circuits.

Abstract: An improved PWM amplifier is disclosed that uses multiple integrators in the loop filter to provide high loop gain across the frequency band-of-interest. The frequency characteristics of the loop filter are optimized to distribute large loop gains across the entire band to provide large suppression of noise and distortions generated in the modulation and output stages.

Abstract: An improved PWM amplifier is disclosed that uses multiple integrators in the loop filter to provide high loop gain across the frequency band-of-interest. The frequency characteristics of the loop filter are optimized to distribute large loop gains across the entire band to provide large suppression of noise and distortions generated in the modulation and output stages.

Abstract: A system for efficient power amplification of an electromagnetic signal includes a switchplexer having at least two inputs and an output. The switchplexer may be configured to provide communication between a selected switchplexer input and the switchplexer output. The system also may include two or more amplifier stages, each having an input and an output, and one or more output matching circuits. Each of the output matching circuits may include an input in communication with one of the amplifier stage outputs, as well as an output in communication with one of the switchplexer inputs. A control unit may be configured to control selection of the selected switchplexer input and to selectively activate at least one of the amplifier stages.

Abstract: The present invention relates to a power amplification circuit of a mobile device for improving the efficiency and the linearity properties of the power amplifier. In one embodiment, the power amplifier improves these properties by controlling the input voltage of the supplemental amplifier so that the power amplifier operates as the Doherty mode in the low output power mode depending on the magnitude of the output power from the output unit and so that the input voltage of the supplemental amplifier may be increased up to satisfy the non-linear operational requirements of a power amplifier in the high output power mode. Moreover, because only the input voltage of the supplemental amplifier is controlled, the power amplifier can be implemented in a simple manner. Thus, the size of the power amplifier becomes small, which in turn reduces the cost of the power amplifier, among other things.

Abstract: An amplifier circuit which is connected to a sensor and variably sets an amplification property and a control method thereof are disclosed, the circuit having the capability of restricting the influence of change with time and temperature change. The amplifier circuit 1, which receives, as an input, a detection signal from the sensor and variably sets an amplification property, comprises: (1) a first reference value retaining unit 50 for retaining a first reference value K1 for setting an amplification property which makes an output signal be a specified detection reference output voltage when a reference input condition KJ is detected; (2) a correction signal generation unit 30 for generating a correction signal HS which reduces the difference between an amplification property actual measurement value and an amplification property set value; and (3) a first amplification property correction unit 40 for correcting the first reference value K1 based on the correction signal HS.

Abstract: A power amplifier stage has a first amplifier subsection and a second amplifier subsection coupled in a parallel configuration. The first amplifier subsection receives a signal to be amplified and the second amplifier subsection receives the signal to be amplified via a first delay line. The amplified output signal of the first amplifier subsection is passed through a second impedance inverter and is combined with the amplified output signal from the second amplifier subsection. In a low power mode, the first amplifier subsection operates as a linear amplifier and the second subsection is biased off. In a high power mode, both the first and second amplifier subsections operate as linear amplifiers. Selecting the impedances of the second delay element and the first amplifier to be equal is essential for high power mode operation and greatly improves the amplifier efficiency in the low power mode.

Abstract: A measuring circuit for the output of a power amplifier and a power amplifier comprising the measuring circuit comprises a first transistor (4f). The output current (27) of the first transistor (4f) is characteristic of the output current (28) of the amplifier (20), in particular, the above is essentially proportional to the output current (28) of the amplifier (20). The first transistor (4f) is controlled in parallel to at least one second transistor (4a-4e), driving the amplifier output (8).

Abstract: A Class-E load circuit topology suitable for switching mode Power Amplifiers (PAs). The inventive load includes a shunt inductive element coupled to an output of said amplifier; a series inductive element coupled to said output of said amplifier; and a series capacitive element coupled to said series inductive element. In the illustrative embodiment, the inventive load is operable at frequencies in the range of 8-10 GHz and the shunt inductive element is an inductive bias line for said amplifier. The invention enables an advantageous Class-E amplifier design comprising an input matching network; an active device coupled to the input matching network and a load coupled to the active device and implemented in accordance with the present teachings.

Abstract: An amplifier circuit includes a feedback loop; a former stage amplifier unit coupled to an input node of the amplifier circuit and the feedback loop for amplifying the difference between an input signal received from the input node and an output signal which comes back through the feedback loop, and outputting a first output signal; a compensating amplifier unit coupled to the former stage amplifier unit for amplifying the first output signal and outputting a second output signal; and an output stage amplifier unit coupled to the compensating amplifier unit and the feedback loop for outputting a third output signal according to the second output signal.