Abstract: A method and apparatus for controlling beam emittance by placing a lens array in a drift space of an illumination system component. The illumination system component may be an electron gun or a liner tube or drift tube, attachable to an electron gun. The lens array may be one or more mesh grids or a combination of grids and continuous foils. The lens array forms a multitude of microlenses resembling an optical “fly's eye” lens. The lens array splits an incoming solid electron beam into a multitude of subbeams, such that the outgoing beam emittance is different from the incoming beam emittance, while beam total current remains unchanged. The method and apparatus permit independent control of beam current and beam emittance, which is beneficial in a SCALPEL illumination system.

Abstract: The present invention is related to a device for irradiating a patient with a charged particle beam, comprising a number of beam channels attached to a vertical wall, wherein a deflection magnet is present at the end of each channel. This deflection magnet is able to deflect the beam in the vertical plane over a given angle range. The couch whereon the patient is reclining is mobile in the vertical plane, so that the combined movement of the patient, and the variable deflection of the beam allow one point in the patient to be irradiated from several angles in the vertical plane.

Abstract: A first manual input device for inputting an irradiation ready state is provided in each treatment room or a control room formed corresponding to the treatment room. A safety device confirms that preparations for generation of an ion beam in an accelerator are completed and preparations for transport of the ion beam in a beam transport system for introducing the ion beam to an irradiation unit in the treatment room selected in response to a ready signal from the first manual input device are completed, followed by outputting ready information. A ready state display unit for displaying the ready information is provided. In the treatment room or the control room, a second manual input device is provided for inputting an irradiation start instruction when the ready information is displayed by the ready state display unit.

Abstract: A piston-ring inspecting device includes a sensor unit (27) including a light emitting system (27a) that emits slit-like detection light toward an outer peripheral surface (Ps) of a piston (P) and an outer peripheral surface (2c) of a piston ring (2) and a light receiving image system (27b) that receives light reflected from the outer peripheral surfaces so as to form an image; an image calculating means that subjects image information obtained by the sensor unit to numerical processing and that calculates a tilt angle of the outer peripheral surface of the piston ring with respect to the outer peripheral surface of the piston; and a controller (30) including a judgment means that, based on arithmetical information obtained by the image calculating means and preset standard information, judges whether or not the piston ring has been fitted in a predetermined direction. Accordingly, an inspection can be performed without scanning, through a simple analysis process, in a short time, and with high accuracy.

Abstract: A solid state radiation detector having a sub-striped electrode is provided, which is capable of effectively erasing residual images accumulating in the region adjacent to the outer edge of the first conductive layer. The detector has a planar first conductive layer; a recording photoconductive layer; a charge transport layer; a reading photoconductive layer; a striped electrode composed of multitudes of linear elements; and a sub-striped electrode composed of multitudes of linear elements. The element partly lying in the image detection area is formed to have a greater width in the non-image-detection area than in the image detection area. In addition, the element entirely lying in the region outside of the image detection area is formed to have a greater width than the width in the image detection area of the element partly lying in the image detection area.

Abstract: The object of providing a non-volatile semiconductor memory that stands out by good scalability and a high retention time as well as ensures low switching voltages at low switching times and achieves a great number of switching cycles at good temperature stability is solved by the present invention with a semiconductor memory whose memory cells comprise at least one silicon matrix material layer with open or disturbed nanocrystalline or amorphous network structures and structural voids which has a resistively switching property between two stable states, utilizing the ion drift in the silicon matrix material layer. The memory concept suggested in the present invention thus offers an alternative to the flash and DRAM memory concepts since it is not based on the storing of charges, but on the difference of the electric resistance between two stable states that are caused by the mobility of ions in the amorphous silicon matrix material with an externally applied electric field.

Abstract: Single-walled carbon nanotube transistor and rectifying devices, and associated methods of making such devices include a porous structure for the single-walled carbon nanotubes. The porous structure may be anodized aluminum oxide or another material. Electrodes for source and drain of a transistor are provided at opposite ends of the single-walled carbon nanotube devices. A gate region may be provided one end or both ends of the porous structure. The gate electrode may be formed into the porous structure. A transistor of the invention may be especially suited for power transistor or power amplifier applications.

Abstract: A semiconductor device includes an active layer, an n-side contact layer, and a p-side contact layer. The nitride semiconductor device includes at least a first n-side layer, a second n-side layer, a third n-side layer and a fourth n-side layer formed in this order from the n-side contact layer between the n-side contact layer and the active layer, while at least the second n-side layer and the fourth n-side layer each contain an n-type impurity, and the concentration of the n-type impurity in at least the second n-side layer and the fourth n-side layer is higher than the concentration of the n-type impurity in the first n-side layer and the third n-side layer.

Abstract: A structure using integrated optical elements is comprised of a substrate, a buffer layer grown on the substrate, one or more patterned layers formed on the buffer layer and one or more active layers formed on or between the patterned layers, for instance by Lateral Epitaxial Overgrowth (LEO), and including one or more light emitting species. The patterned layer comprises a mask (made of insulating, semiconducting or metallic material) and material filling holes in the mask. The patterned layer, due to a large index difference with the active layer and/or variations of a refractive index between the mask and materials filling holes in the mask, acts as an optical confinement layer, a mirror, a diffraction grating, a wavelength selective element, a beam shaping element or a beam directing element.

Abstract: The invention includes non-volatile memory and logic devices associated with crystalline Si/Ge. The devices can include TFT constructions. The non-volatile devices include a floating gate or floating plate over the Si/Ge, and a pair of source/drain regions. The source/drain regions can extend into the Si/Ge. The memory or logic devices further include an insulative material over the floating gate or plate, and a control gate separated from the floating gate or plate by the insulative material. The crystalline Si/Ge can have a relaxed crystalline lattice, and a crystalline layer having a strained crystalline lattice can be formed between the relaxed crystalline lattice and the floating gate or plate. The devices can be fabricated over any of a variety of substrates. The floating plate option can provide lower programming voltage and orders of magnitude superior endurance compared to other options.

Abstract: The invention relates to a light emitting component with organic layers and emission of triplet exciton states (phosphorescent light) with increased efficiency, having a layer sequence with a hole injecting contact (anode), one or more hole injecting and transporting layers, a system of layers in the light emission zone, one or more electron transport and injection layers and an electron injecting contact (cathode), characterized in that the light emitting zone comprises a series of heterojunctions with the materials A and B (ABAB . . . ) that form interfaces of the type “staggered type II”, one material (A), having hole transporting or bipolar transport properties and the other material (B) having electron transporting or bi-polar transport properties, and at least one of the two materials A or B being mixed with a triplet emitter dopant that is able to efficiently convert its triplet exciton energy into light.

Abstract: The present invention describes new types of material mixtures composed of at least two substances, one serving as a matrix material and the other being an emission material capable of emission, the latter comprising at least one element of atomic number greater than 20, and the use thereof in organic electronic components such as electroluminescent elements and displays.

Abstract: The invention described herein includes a molecular switch, comprising: a donor subunit; an acceptor subunit; and an aromatic bridging subunit comprising one or more bridging groups for bonding the donor subunit to the aromatic bridging subunit and for bonding the acceptor subunit to the aromatic bridging subunit wherein the aromatic bridging subunit is conformable in a manner effective for polarizing and de-polarizing the molecular switch at a low electric field voltage.

Abstract: A novel barrier layer which protects electronic devices from adverse environmental effects such as exposure to light, especially white light, is described. The barrier layer comprises a copolymer having an acrylate unit and an acrylate unit with a pendant dye group. Also disclosed are processes for producing such electronic devices.

Abstract: An emitter has a plurality of types of light-emitting units with different changes in emission characteristics over time. In addition, the emitter includes a deterioration adjustment device which adjusts the deterioration of the emission characteristics over time in a predetermined type of light-emitting unit. The light-emitting units respectively include a light-emitting layer and a hole donor which supplies positive holes to the light-emitting layer, and the deterioration adjustment device may be the hole donor in which the thickness is adjusted based on the deterioration in emission characteristics over time in the predetermined type of light-emitting unit.

Abstract: A device, system and method for evaluating reliability of a semiconductor chip are disclosed. Strain is determined at a location of interest in a structure. Failures are evaluated in a plurality of the structures after stress cycling to determine a strain threshold with respect to a feature characteristic. Structures on a chip or chips are evaluated based on the feature characteristic to predict reliability based on the strain threshold and the feature characteristic. Predictions and design changes may be made based on the results.

Abstract: A method of measuring electrical characteristics of a gate dielectric. The gate dielectric is local annealed by directing a highly localized energy source at the measurement area, such that the measurement area is brought to an annealing temperature while surrounding structures are not significantly heated. While heating the measurement area, a flow of a gas containing a percentage of hydrogen, deuterium, or water vapor at a flow rate is directed to the measurement area. A charge is inducted on the measurement area and the electrical characteristics of the gate dielectric are measured using non contact electrical probing.

Abstract: The present invention is directed to thin film transistors using nanowires (or other nanostructures such as nanoribbons, nanotubes and the like) incorporated in and/or disposed proximal to conductive polymer layer(s), and production scalable methods to produce such transistors. In particular, a composite material comprising a conductive polymeric material such as polyaniline (PANI) or polypyrrole (PPY) and one or more nanowires incorporated therein is disclosed.

Abstract: A solid-state imaging device includes: a photoelectric conversion element; a pixel region including a modulation part formed adjacent to the photoelectric conversion element; and a peripheral region in which a peripheral circuit including a driving circuit driving the photoelectric conversion element and the modulation part is disposed, wherein the peripheral region includes a transistor that a sidewall is formed on a side of a gate electrode; and the pixel region includes a transistor that no sidewall is formed on a side of a gate electrode.

Abstract: A silicon carbide metal semiconductor field-effect transistor includes a bi-layer silicon carbide buffer for improving electron confinement in the channel region and/or a layer disposed over at least the channel region of the transistor for suppressing surface effects caused by dangling bonds and interface states. Also, a sloped MESA fabrication method which utilizes a dielectric etch mask that protects the MESA top surface during MESA processing and enables formation of sloped MESA sidewalls.

Abstract: A bipolar junction transistor (BJT) includes a silicon carbide (SiC) collector layer of first conductivity type, an epitaxial silicon carbide base layer of second conductivity type on the silicon carbide collector layer, and an epitaxial silicon carbide emitter mesa of the first conductivity type on the epitaxial silicon carbide base layer. An epitaxial silicon carbide passivation layer of the first conductivity type is provided on at least a portion of the epitaxial silicon carbide base layer outside the silicon carbide emitter mesa. The epitaxial silicon carbide passivation layer can be configured to fully deplete at zero device bias. Related fabrication methods also are disclosed.

Abstract: A semiconductor substrate comprises a semiconductor layer comprising a group III nitride as a main component. A scattering portion for scattering an incident beam of light incident on one plane of the semiconductor layer is provided on another plane or inside of the semiconductor layer.

Abstract: A solid-state light source includes a semiconductor light source for emitting light and an optical system having a fiber optic element. The fiber optic element has an input for receiving emitted light from the semiconductor light source. The fiber optic element also has an output for emitting light received from the solid-state light source. The semiconductor light source and the fiber optic element in aggregate form an illumination path.

Abstract: A nitride-based semiconductor component having a semiconductor body (1) with a contact metalization (4) applied thereon. The semiconductor body (1) is provided with a protective layer which, if appropriate, also covers partial regions of the contact metalization (4) and which has a plurality of recesses (5) arranged near to one another.

Abstract: An organic light emitting diode display includes an insulating layer, a stress buffer disposed on the insulating layer, a first electrode disposed on the stress buffer, an organic light emitting member disposed on the first electrode, and a second electrode disposed on the organic light emitting member.

Abstract: A manufacturing method and a thus produced light-emitting structure for a white colored light-emitting device (LED) and the LED itself are disclosed. The white colored LED includes a resonant cavity structure, producing and mixing lights which may mix into a white colored light in the resonant cavity structure, so that the white colored LED may be more accurately controlled in its generated white colored light, which efficiently reduces deficiency, generates natural white colored light and aids in luminous efficiency promotion. In addition to the resonant cavity structure, the light-emitting structure also includes a contact layer, an n-type metal electrode and a p-type metal electrode.

Abstract: An optical device package includes a substrate having an upper surface, a distal end, a proximal end, and distal and proximal longitudinally extending notches co-linearly aligned with each other. A structure is mounted to the substrate and has at least one recessed portion. The structure can be a lid or a frame to which a lid is bonded. An optical fiber is positioned within at least one of the proximal longitudinally extending notch and the distal longitudinally extending notch and within the recessed portion of the structure mounted to the substrate. The optical device package can also include conductive legs extending upwardly from bonding pads on the upper surface of the substrate to facilitate flip mounting of the optical device package onto a circuit board or other such platform.

Abstract: The light-radiating semiconductor component has a radiation-emitting semiconductor body and a luminescence conversion element. The semiconductor body emits radiation in the ultraviolet, blue and/or green spectral region and the luminescence conversion element converts a portion of the radiation into radiation of a longer wavelength. This makes it possible to produce light-emitting diodes which radiate polychromatic light, in particular white light, with only a single light-emitting semiconductor body. A particularly preferred luminescence conversion dye is YAG:Ce.

Abstract: An LED comprising a circuit board, a connecting electrode unit provided on the circuit board, a reflective cup provided within the circuit board, an LED element disposed in the reflective cup and connected to the connecting electrode unit, and a resin with which the reflective cup is filled, a fluorescent material contained in the resin absorbing one portion of light emitted from the LED element and changing the wavelength of the light.

Abstract: A light emitting device of the present invention includes an LED substrate and a sealing resin portion which seals the LED substrate, the sealing resin portion having a silicone resin having a refractive index n3 to which a fluorescent material having a refractive index n1 and fine particles having a refractive index n2 are added. In the light emitting device, a relationship of n2>n1>n3 holds in the refractive indexes n1 to n3, and a particle size of the fine particles is not more than 1/10 of a wavelength of light emitted from the LED substrate.

Abstract: The present invention provides a method and apparatus for using light emitting diodes for curing and various solid state lighting applications. The method includes a novel method for cooling the light emitting diodes and mounting the same on heat pipe in a manner which delivers ultra high power in UV, visible and IR regions. Furthermore, the unique LED packaging technology of the present invention utilizes heat pipes that perform very efficiently in very compact space. Much more closely spaced LEDs operating at higher power levels and brightness are possible because the thermal energy is transported in an axial direction down the heat pipe and away from the light-emitting direction rather than a radial direction in nearly the same plane as the “p-n” junction.

Abstract: A GaN-based LED structure is provided so that the brightness and luminous efficiency of the GaN-based LED are enhanced effectively. The greatest difference between the GaN-based LEDs according to the invention and the prior arts lies in the addition of a masking buffer layer and a roughened contact layer on top of the masking buffer layer. The masking buffer layer contains randomly distributed clusters made of a group-IV nitride SixNy (x,y?1), a group-II nitride MgwNz (w,z?1), or a group-III nitride AlsIntGa1?s?tN (0?s,t<1, s+t?1) heavily doped with at least a group-II and group-IV element such as Mg and Si. The roughened contact layer, made of AluInvGa1?u?vN (0?u,v<1, u+v?1), starts from the top surface of an underlying second contact layer not covered by the masking buffer layer's clusters, and then grows upward until it passes (but does not cover) the clusters of the masking buffer layer for an appropriate distance.

Abstract: An LED including a substrate having a pair of terminal electrodes, at least one LED element mounted on the substrate, a frame disposed on the substrate, holes provided in the substrate, concave portions provided in positions of the frame facing the holes, and a pair of conductive elastic members provided between the frame and the substrate, each of the conductive elastic members including a large diameter portion inserted in the corresponding concave portion and a small diameter portion inserted in the corresponding hole and electrically connected to the large diameter portion, the large diameter portions of the pair of conductive elastic members being electrically connected to the pair of terminal electrodes, respectively, and each of the large diameter portions having one end portion which is in contact with a bottom surface of the concave portion and each of the small diameter portions having one end portion which is disposed to project from the hole of the substrate.

Abstract: P-type layers of a GaN based light-emitting device are optimized for formation of Ohmic contact with metal. In a first embodiment, a p-type GaN transition layer with a resistivity greater than or equal to about 7 ? cm is formed between a p-type conductivity layer and a metal contact. In a second embodiment, the p-type transition layer is any III-V semiconductor. In a third embodiment, the p-type transition layer is a superlattice. In a fourth embodiment, a single p-type layer of varying composition and varying concentration of dopant is formed.

Abstract: A light emitting device in accordance with an embodiment of the present invention includes a first semiconductor layer of a first conductivity type having a first surface, and an active region formed overlying the first semiconductor layer. The active region includes a second semiconductor layer which is either a quantum well layer or a barrier layer. The second semiconductor layer is formed from a semiconductor alloy having a composition graded in a direction substantially perpendicular to the first surface of the first semiconductor layer. The light emitting device also includes a third semiconductor layer of a second conductivity type formed overlying the active region.

Abstract: An avalanche photodiode has improved low-noise characteristics, high-speed response characteristics, and sensitivity. The avalanche photodiode includes a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, a semiconductor multiplication layer interposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, and a semiconductor light-absorbing layer interposed between the semiconductor multiplication layer and the second conductivity type semiconductor layer. The avalanche photodiode further comprises a multiplication suppressing layer which suppresses multiplication of charge carriers in the semiconductor light-absorbing layer, located between the semiconductor light-absorbing layer and the second conductivity type semiconductor layer.

Abstract: An electric signal transmission line includes a signal electrode portion, a ground electrode portion and a dielectric portion formed on a semiconductor substrate. The signal electrode portion has a metal electrode through which an electric signals flows. The ground electrode portion has a grounded metal electrode. The metal electrode of the signal electrode portion and the metal electrode of the ground electrode portion are connected with a semiconductor PN junction. The dielectric portion is formed by using a dielectric to cover a region between the metal electrode of the signal electrode portion and the metal electrode of the ground electrode portion through which a line of electric force runs and is a region in which energy of transmitted electric signals exist.

Abstract: A semiconductor material which has a high carbon dopant concentration includes gallium, indium, arsenic and nitrogen. The disclosed semiconductor materials have a low sheet resistivity because of the high carbon dopant concentrations obtained. The material can be the base layer of gallium arsenide-based heterojunction bipolar transistors and can be lattice-matched to gallium arsenide emitter and/or collector layers by controlling concentrations of indium and nitrogen in the base layer. The base layer can have a graded band gap that is formed by changing the flow rates during deposition of III and V additive elements employed to reduce band gap relative to different III-V elements that represent the bulk of the layer. The flow rates of the III and V additive elements maintain an essentially constant doping-mobility product value during deposition and can be regulated to obtain pre-selected base-emitter voltages at junctions within a resulting transistor.

Abstract: A solid-state image pick-up device of a photoelectric converting film lamination type including a semiconductor substrate and at least three layers of photoelectric converting films each of which is interposed between a common electrode film and pixel electrode films. The pixel electrode films correspond to pixels respectively, and at least three layers of photoelectric converting films are laminated through insulating layers. The at least three layers of photoelectric converting films are above the semiconductor substrate. Sets of the pixel electrode films are provided on each of the at least three layers of photoelectric converting films, and electric charge storage portions formed on the semiconductor substrate are connected through sets of columnar contact electrodes. Resistance values of the sets of columnar contact electrodes are equal to each other.

Abstract: The first source and drain regions are formed in an upper surface of a SiGe substrate. The first source and drain regions containing an N type impurity. Vacancy concentration in the first source and drain regions are reduced in order to reduce diffusion of the N type impurity contained in the first source and drain regions. The vacancy concentration is reduced by an interstitial element or a vacancy-trapping element in the first source and drain regions. The interstitial element or the vacancy-trapping element is provided by ion-implantation.

Abstract: A self-aligned silicide (salicide) process is used to form a local interconnect for a CMOS image sensor consistent with a conventional CMOS image sensor process flow. An oxide layer is deposited over the pixel array of the image sensor. Portions of the oxide layer is removed and a metal layer is deposited. The metal layer is annealed to form a metal silicide. Optionally, a protective oxide layer is then deposited.

Abstract: A ferroelectric capacitor circuit for sensing hydrogen gas having a closed integrated circuit package, a ferroelectric capacitor within the closed integrated circuit package, the ferroelectric capacitor having a bismuth oxide based ferroelectric layer being able to absorb hydrogen gas that is within the closed integrated circuit package, absorbed hydrogen gas chemically reducing a portion of the bismuth oxide based ferroelectric layer into bismuth metal, the ferroelectric capacitor having a ferroelectric voltage, the ferroelectric voltage having a voltage strength, and means for measuring a decrease in the voltage strength of the ferroelectric voltage of the ferroelectric capacitor.

Abstract: The invention includes a method of forming a planarized surface over a semiconductor substrate. A substrate is provided which includes a memory array region and a peripheral region proximate the memory array region. The memory array region has a higher average elevational height than the peripheral region. Polysilazane is formed over the memory array region and over the peripheral region. The polysilazane is densified. A material is formed over the polysilazane. The material is planarized while using the densified polysilazane as a stop. The planarization forms a planarized surface which extends over the memory array and peripheral regions. The planarized surface comprises both the densified polysilazane and the material.

Abstract: A method used during the formation of a semiconductor device comprises providing a wafer substrate assembly comprising a plurality of digit line plug contact pads and capacitor storage cell contact pads which contact a semiconductor wafer. A dielectric layer is provided over the wafer substrate assembly and etched to expose the digit line plug contact pads, and a liner is provided in the opening. A portion of the digit line plug is formed, then the dielectric layer is etched again to expose the capacitor storage cell contact pads. A capacitor bottom plate is formed to contact the storage cell contact pads, then the dielectric layer is etched a third time using the liner and the bottom plate as an etch stop layer. A capacitor cell dielectric layer and capacitor top plate are formed which provide a double-sided container cell. An additional dielectric layer is formed, then the additional dielectric layer, cell top plate, and the cell dielectric are etched to expose the digit line plug portion.

Abstract: A semiconductor structure that may be a discrete capacitor, a Silicon On Insulator (SOI) Integrated Circuit (IC) including circuits with discrete such capacitors and/or decoupled by such discrete capacitors and an on-chip decoupling capacitor (decap). One capacitor plate may be a well (N-well or P-well) in a silicon bulk layer or a thickened portion of a surface silicon layer. The other capacitor plate may be doped polysilicon and separated from the first capacitor plate by capacitor dielectric, e.g., CVD or thermal oxide. Contacts to each of the capacitor plates directly connect and extend from the respective plates, such that direct contact is available from both plates.

Abstract: In a capacitor-containing semiconductor integrated circuit, a portion in which a plurality of capacitors are serially connected together is arranged so that at least part of the capacitors is formed as a well capacitor.

Abstract: A semiconductor memory device having a self-aligned charge trapping layer and a method of manufacturing the same in which a consistent length of an ONO layer is ensured. Here, an insulating stacked structure is self-aligned to a bottom surface of conductive spacers.

Abstract: A semiconductor apparatus comprises a gate electrode, a gate insulating layer, a drift region of a first conductivity type formed over a semiconductor substrate of the first conductivity type, a base region of a second conductivity type formed over the drift region, a source region of the first conductivity type formed on the base region and a column region formed in the drift region under the base region, the column region being divided into a plurality of divided portions in depth direction.

Abstract: A recess gate of a semiconductor device includes: a substrate having a bulb-shaped recess pattern formed therein, wherein the bulb-shaped recess pattern includes a first ball pattern and a second ball pattern formed therein, the first ball pattern having a different diameter than the second ball pattern; a gate insulation layer formed over the bulb-shaped recess pattern and the substrate; and a conductive layer formed over the gate insulation layer and filling the bulb-shaped recess pattern.

Abstract: A semiconductor device includes a body region, a drift region having a first part and a second part, and a trench gate electrode. The body region is disposed on the drift region. The first and second parts extend in an extending direction so that the second part is adjacent to the first part. The trench gate electrode penetrates the body region and reaches the drift region so that the trench gate electrode faces the body region and the drift region through an insulation layer. The trench gate electrode extends in a direction crossing with the extending direction of the first and second parts. The first part includes a portion near the trench gate electrode, which has an impurity concentration equal to or lower than that of the body region.