Abstract: A lighting device for a vehicle includes a lamp unit serving to irradiate a light forward, and an actuator having a single output shaft for tilting the lamp unit vertically and transversely. The lamp unit is disposed in a lamp housing formed by a lamp body and a transparent cover for covering a front surface of the lamp body. The lamp unit includes a body coupling portion to be coupled to the lamp body and an actuator coupling portion to be coupled to the actuator. The lamp body includes a lamp unit coupling portion coupled to the body coupling portion and serving to support the lamp unit tiltably in vertical and transverse directions. The actuator is supported on the lamp body and includes an output shaft for tilting the lamp unit vertically and transversely in engagement with the actuator coupling portion of the lamp unit.

Abstract: A lighting unit is provided with a cutoff line forming member disposed between a projection lens and a first light source and having a tip edge positioned in a vicinity of a rear focal point of the projection lens. The cutoff line forming member is capable of shielding a part of a light reflected by a reflector, thereby forming a cutoff line of a light distribution pattern for a low beam. An additional reflector is capable of collecting a light emitted from a second light source in a vicinity of the rear focal point of the projection lens. The light emitted from the second light source is collected in the vicinity of the rear focal point of the projection lens in a state in which the tip edge of the cutoff line forming member and the rear focal point of the projection lens are relatively separated from each other, and a light distribution pattern for a high beam is thus formed.

Abstract: An optical axis regulating device of a lighting device for a vehicle, which serves to vertically and transversely tilt a lamp unit supported on one fulcrum in a lamp housing formed by a lamp body having a concave portion and a transparent cover for covering an opening portion of the lamp body, includes a case, a slider movable in a longitudinal direction with respect to the case, an output portion rotatably supported on the slider and coupled to the lamp unit, a vertical regulating device for moving the slider in a longitudinal direction, and a transverse regulating device for rotating the output portion.

Abstract: A solid-state light source includes a semiconductor light source for emitting light and an optical system having a fiber optic element. The fiber optic element has an input for receiving emitted light from the semiconductor light source. The fiber optic element also has an output for emitting light received from the solid-state light source. The semiconductor light source and the fiber optic element in aggregate form an illumination path.

Abstract: A lighting device, comprising at least one solid state light emitter and one (or more) optical device(s) which (each) comprises at least first, second and third optical structures, first and second surfaces of the second structure being in contact with a surface of the first structure and a surface of the third structure, respectively. The third structure has at least one optical feature. The light emitter is positioned, the optical feature is positioned, and the regions of the structures have indices of refraction, such that if the light emitter is illuminated, at least a portion of the emitted light will enter into the second optical device structure and exit from the optical feature on the third structure. Also, a method of lighting comprising illuminating a light emitter in such a device.

Abstract: A directly illuminated display unit has a display panel and one or more light sources disposed behind the display panel. A diffuser is disposed between the one or more light sources and the display panel, and a light diverting layer is disposed between the one or more light sources and the diffuser. The light diverting layer has a first light-diverting surface facing the one or more light sources and a second light diverting surface facing the display panel. The light diverting layer diverts light passing from the one or more light sources to the diffuser, thus improving the uniformity of the light in the display unit.

Abstract: A back light unit, in which bright lines produced from point light sources, light emitting diodes, in an oblique direction are removed, so that brightness can be uniformly maintained at a liquid crystal panel. The back light unit includes a prism light guide plate, light emitting diodes provided on one side of the prism light guide plate, and a bright-line dead section provided to the prism light guide plate so as to uniformly scatter light of each light condensing section generated by light emitted from the light emitting diodes, to prevent a spectrum of the light in a specific direction, and to prevent bright lines from being produced.

Abstract: A display device is provided. The display device includes a display panel comprising a display surface configured to display an image thereon, the display surface having an edge; a light source spaced apart from the display panel to form a space therebetween and configured to emit light to the display panel, wherein the display panel is configured to generate image on the display surface using the light from the light source; and a reflective surface arranged so as to reflect light emitted from the light source and to direct the reflected light to the edge.

Abstract: A backlight unit can change the directional characteristics of exiting light by selectively turning on two light sources. The backlight unit includes a first prism sheet (4) having on a lower surface thereof a plurality of parallel prisms (3), a first lightguide plate (5) disposed underneath the first prism sheet (4), a second prism sheet (6) disposed underneath the first lightguide plate (5) and having on a lower surface thereof a plurality of parallel prisms (3), a second lightguide plate (7) disposed underneath the second prism sheet (6), a first light source (8) disposed adjacent to an edge surface of the first lightguide plate (5) to emit light into the first lightguide plate (5), and a second light source (9) disposed adjacent to an edge surface of the second lightguide plate (7) to emit light into the second lightguide plate (7).

Abstract: A diffusion plate of a backlight structure and a display device using the same are provided. The diffusion plate is used in the backlight structure having several light emitting diodes. The diffusion plate includes a main body with many depression structures positioned on a surface of the main body. The surface faces the light emitting diodes. Each depression structure is positioned above the corresponding light emitting diode and includes an inclined surface. An inclined angle is formed between each inclined surface and a central axis of the corresponding light emitting diode for refracting the light emitted by the corresponding light emitting diode.

Abstract: The invention provides an electro-optical device that includes: an electro-optical panel; light sources that emit light that enters the electro-optical panel; an optical waveguide board that guides the light emitted from the light sources toward the electro-optical panel; and a flexible printed circuit board on which the light sources are mounted, wherein the flexible printed circuit board is adhered to the optical waveguide board by adhesive members in such a manner that a part of the flexible printed circuit board is opposed to a surface of the optical waveguide board and that the light sources are positioned to be opposed to an edge face of the optical waveguide board, and concave portions are formed in the optical waveguide board at least at positions where the adhesive members are provided.

Abstract: A light guide plate is disclosed by the present invention. The light guide plate includes a first main body having a light-exiting surface and a second main body fixed to the first main body. The second main body has a light-entering surface, and the second main body is utilized to guide light received by the light-entering surface to the first main body, wherein there is a first recessed region positioned in one side of a joint portion between the first main body and the second main body, and the first recessed region is positioned at an edge of the light-exiting surface.

Abstract: A supporting frame has a frame body and at least one connecting post. The frame body has a connecting face and an edge. The at least one connecting post is formed on and extends from the connecting face at the edge. Each connecting post is hollow and conical and has an enlarged end, a reduced end and at least one slit. The enlarged end has a diameter and is formed on the connecting face of the frame body. The reduced end has a diameter smaller than that of the enlarged end and is away from the connecting face of the frame body. The at least one slit is longitudinally formed in the connecting post. Accordingly, the supporting frame can be easily and precisely combined with a circuit board.

Abstract: A switching power supply device has a drive circuit that can minimize a loss while being compact. The drive circuit turns on and off a high-side switching element (MOSFET) according to a positive or negative voltage developed at a tertiary winding of a transformer. The drive circuit includes a control unit that detects the development time, during which the negative voltage is developed at the tertiary winding, as the on time of a low-side switching element, and makes the on time of the high-side switching element nearly or substantially equal to the development time.

Abstract: A primary side sensing power control system and method for constant current control that utilizes a relationship that involves the measured reset-time from the previous cycle to determine the primary side peak current and off-time for the next cycle. This control mechanism does not need the knowledge of input voltage or magnetizing inductance. Therefore, it removes the sensitivities of input voltage and magnetizing inductance to the output current limit. Furthermore, it uses a time measurement instead of a voltage measurement for the current calculation which in many cases is easier to perform.

Abstract: The invention concerns control of a switched-mode power supply. A switched-mode power supply according to the invention comprises a secondary switch that enables a secondary side of the switched-mode power supply to charge magnetic energy into a transformer of the switched-mode power supply. The switched-mode power supply comprises also a control circuitry that controls the operation of the secondary switch. Due to the fact that the secondary side is able to return energy to a primary side of the switched-mode power supply the control of the switched-mode power supply can be fast. Furthermore, a need for an isolator circuit, e.g. an optical isolator, is avoided.

Abstract: A transforming circuit for power supplier includes a primary winding coil; a secondary winding coil and a secondary rectifier circuit, an AC power being transformed by the secondary winding coil in accordance with a winding turns ratio relative to the primary winding coil and converted by the secondary rectifier circuit into a first-potential DC power; N+1 sets of potential modifying circuits, connected in parallel with the first-potential DC power, each set of potential modifying circuits being based on the first-potential DC power and transformed thereof into N+1 sets of second-potential DC power at differential potential, N?1. Thereby, DC power at different potentials can be provides so that the power output can be more flexible and effective.

Abstract: A portable, variable power supply is provided according to the invention. The portable power supply will be a variable power supply comprised of at least one power unit which is further comprised of at least one power cell. Two or more power units will operably connect to configurable, control switches to enable selection of the various customizable configurations. The variable supply will have at least one operable connection to attach to devices.

Abstract: DC power for low power loads is provided for vehicles such as snowmobiles where the electrical system includes primarily AC power. DC voltage is provided for gauges and similar loads even though the peak value of the AC is below a desired level. Rectification and regulation of some energy from the alternator is used for supplying the DC power at a desired DC voltage that is above an alternator zero to peak value. A capacitor and a diode are connected in parallel from the alternator with rectifying circuit portions for supplying power to the DC load. A DC voltage monitor senses the DC voltage supplied to the DC load and prevents the DC voltage from rising above the desired voltage by controlling the first rectification, the second rectification, or both.

Abstract: A switching pre-regulator for a bulk capacitor filter followed by a series pass regulator has a switching element controller that relies upon a large desirable leakage inductance in a main secondary winding of a power transformer acting as a swinging choke input to the bulk capacitive filter. This desirable leakage inductance limits inrush current and supplies some filtering. However, the effective value of the swinging choke is a function of load conditions, and introduces a varying phase shift that would potentially disturb the zero crossing detection used in properly activating the switching element.

Abstract: An exemplary power supply circuit includes a transformer (21) having a primary coil (211) and a secondary coil (212); a rectification circuit and a transistor (26) respectively coupled to two terminals of the primary coil; a communicating and filter circuit (22) coupled to the secondary coil; a sampling circuit (13) having a first resistor (231) and a first capacitor (232) connected in series; and a pulse width modulation circuit (25) coupled between the transistor and the sampling circuit. Direct current (AC) voltage is applied to the rectification circuit and is converted into DC voltage via the transformer and the communicating and filter circuit. The DC voltage is fed back to the pulse width modulation circuit via a voltage applied to the first capacitor. The pulse width modulation circuit adjusts a gating time of the transistor so as to adjust the output DC voltage output by the power supply circuit.

Abstract: The present invention provides a three-level ac generating circuit and the control method thereof. The three-level ac generating circuit includes a three-level boosting circuit connected to an input source and including a positive boosting portion and a negative boosting portion; and a three-level inverting circuit connected to the three-level boosting circuit and including a positive inverting portion and a negative inverting portion, wherein while the input source is a relative low voltage, the relatively low voltage is boosted via the three-level boosting circuit, inverted and output via the three-level inverting circuit; while the input source is a relatively high voltage, the relatively high voltage is inverted and output via the three-level inverting circuit and wherein the output of the three-level ac generating circuit is power grid.

Abstract: A power converter unit comprises: a metal casing; a power module mounted in the metal casing and equipped with two or more power semiconductor devices; a metal plate disposed on the power module and fixed to the metal casing; a heat dissipating sheet disposed on the metal plate; and a drive circuit board disposed on the heat dissipating sheet and is equipped with a control circuit for controlling the power semiconductor devices.

Abstract: An adjustable compact high-frequency-high-voltage power supply utilizes an inverter to convert DC power to AC power so as to provide high frequency AC power at high voltages in a DC environment. Furthermore, the output voltage and frequency can be adjusted through adjustments of variable resistors during operation so as to provide high-frequency-high-voltage AC power at different frequencies and voltages.

Abstract: A power line layout for a semiconductor device includes a memory cell region, a plurality of wordline enable signal lines in the memory cell region, a plurality of first power lines arranged between the wordline enable signal lines in the memory cell region, and a plurality of second power lines arranged perpendicular to the first power lines in the memory cell region to form a mesh arrangement of first and second power lines.

Abstract: This invention discloses a circuit trimming system that includes a one-time programmable memory (OTP). The OTP further includes a forward biased trim device connected between a voltage supply Vcc and a ground voltage wherein the Vcc having a reduced voltage substantially lower than a trimming voltage for a reversed biased device at ten volts or higher. The OTP further includes a drive circuit provided to select the OTP at a low current operating condition and for turning on a high trim current through the forward biased trim device for trimming and programming the OTP. The trimming system further includes a sense circuit connected across the forward biased trim device is for sensing a current and voltage of the forward biased trim device.

Abstract: This invention discloses a system comprising a first comparator circuit configured to assert a first control signal in response to a first input number matching one of a first numbers stored therein, a second comparator circuit configured to assert a second control signal in response to: (i) at least one latched assertion of the first control signal; (ii) a second input number matching an intermediate number produced by incrementing the first input number; and (iii) an assertion of an input signal, and to de-assert the second control signal absent of either the matching between the second input number and the intermediate number or the de-assertion of the input signal, and a generator circuit configured to output a predetermined instruction data stored therein in response to the assertion of the first control signal, and to output a third number in response to the assertions of the second control signal.

Abstract: In a method of providing an operating characteristic of a resistive memory device, material of an electrode thereof is selected to in turn provide a selected operating characteristic of the device. The material of the electrode may be reacted with material of an insulating layer of the resistive memory device to form a reaction layer, the selected operating characteristic being dependent on the presence of the reaction layer.

Abstract: A solid electrolyte memory device includes at least one solid electrolyte memory cell, each of which including a reactive electrode, an inert electrode, and solid electrolyte positioned between the reactive electrode and the inert electrode, and at least one charge storing unit storing an electric charge, the at least one charge storing unit being electrically connected to the at least one solid electrolyte memory cell such that tuning voltages resulting from the charge stored in the at least one charge storing unit are applied across the solid electrolyte of each solid electrolyte memory cell connected to the at least one charge storing unit.

Abstract: A semiconductor memory device and a dummy line biasing method in which in the semiconductor memory device of a diode structure including a plurality of memory cells each having one variable resistance device and one diode device, the memory device includes a plurality of normal word lines, a plurality of normal bit lines, at least one or more dummy word lines and at least one or more dummy bit lines. The plurality of normal word lines are each arrayed in a first direction as a length direction. The plurality of normal bit lines are each arrayed in a second direction as a width direction, intersected with the first direction, so that the plurality of normal bit lines are intersected with the normal word lines. At least one or more dummy word lines are arrayed in the same structure as the normal word lines in the first direction, the at least one or more dummy word lines having a constant level of applied voltage.

Abstract: A semiconductor memory device includes a plurality of cell array layers including a plurality of word lines extending in a first direction, a plurality of bit lines extending in a second direction that intersects the first direction, and a plurality of memory cells disposed at intersections of the word lines and the bit lines. Each of the word lines has a word line position, each of the bit lines has a bit line position, and each of the memory cells includes a variable resistance device in series with a diode. The cell array layers are arranged in layers in a third direction that is perpendicular to the first and second directions. The bit lines of each of the cell array layers having a same bit line position are connected to a common column selector transistor, or the word lines of the cell array layers having a same word line position are connected to a common word line driver.

Abstract: A memory cell is constructed by connecting in series a variable-resistance element having a resistance which is varied by application of a positive voltage to one terminal (first node) thereof using a potential at the other terminal thereof as a reference and a diode which allows a current to flow therethrough by application of a positive voltage to the other terminal thereof using a potential at one terminal (second node) thereof as a reference. The first node is connected to the corresponding column select line and the second node is connected to the corresponding row select line. Then, to a non-selected row select line, a potential higher than when the row select line is selected is applied by using a row control circuit. By using column-select-line driver circuits, predetermined potentials corresponding to a non-selection period, a data write period, a reset period, and a data read period are applied to the column select line.

Abstract: A phase change memory device includes a substrate, a plurality of cell arrays stacked above the substrate and each including a matrix layout of a plurality of memory cells, each the memory cell storing therein as data a resistance value determinable by a phase change, a write circuit configured to write a pair cell constituted by two neighboring memory cells within the plurality of cell arrays in such a manner as to write one of the pair cell into a high resistance value state and write the other into a low resistance value state, and a read circuit configured to read complementary resistance value states of the pair cell as a one bit of data.

Abstract: A system and method for writing a SRAM cell coupled to complimentary first and second bit-lines (BLs) is disclosed, the method comprising asserting a word-line (WL) selecting the SRAM cell to a first positive voltage, providing a second positive voltage at the first BL, providing a first negative voltage at the second BL, and asserting a plurality of WLs not selecting the SRAM cell to a second negative voltage, wherein the writing margin of the SRAM cell is increased.

Abstract: This invention discloses an integrated circuit, which comprises a first and a second pull-down circuit controlled by a first and second signal, respectively, and coupled between a first node and a low voltage power supply (Vss), and a controllable pull-up circuit coupled between the first node and a complimentary high voltage power supply (Vcc), wherein when either the first or second signal is asserted to a predetermined logic state, the first node is pulled down to a logic LOW state.

Abstract: A method and assembly for sensing a voltage with a memory cell (88) is provided. The memory cell includes first and second electrodes (96,112), first and second ferromagnetic bodies (104,108) positioned between the first and second electrodes and an insulating body (94) positioned between the first and second ferromagnetic bodies. The first electrode is electrically connected to a first portion of a microelectronic assembly (47). The second electrode is electrically connected to a second portion of the microelectronic assembly. The voltage across the first and second portions of the microelectronic assembly is determined based on an electrical resistance of the memory cell. The memory cell may be a magnetoresistive random access memory (MRAM) cell. In one embodiment, the memory cell is a magnetic tunnel junction (MTJ) memory cell.

Abstract: A storage element and memory are provided. The storage element includes a storage layer that stores information based on a magnetic state of a magnetic material; and a fixed magnetization layer a magnetization direction of which is fixed and which is provided for the storage layer with a nonmagnetic layer in between. Information is recorded in the storage layer by applying a current in a stacking direction to change the magnetization direction of the storage layer. The fixed magnetization layer includes a plurality of ferromagnetic layers that are stacked with nonmagnetic layers in between, and the fixed magnetization layer includes magnetization regions having magnetic components in the stacking direction and magnetizations in respectively opposite directions. The magnetization regions are formed at both ends of at least one ferromagnetic layer that is disposed closest to the storage layer out of the plurality of ferromagnetic layers.

Abstract: There is provided a magnetic memory device including a first magnetoresistive element which takes a high-resistance-state when receiving a write current in a first direction, takes a low-resistance-state having a resistance value lower than that in the high-resistance-state when receiving a write current in a second direction opposite to the first direction, and receives a read current in a read operation, a second magnetoresistive element which takes one of the high-resistance and low-resistance-states in accordance with a magnetization state thereof, is fixed to the low-resistance-state when a direction of the read current is the same as the first direction, and is fixed to the high-resistance-state when the direction of the read current is the same as the second direction, and a control circuit which is connected to the first and second elements, and makes a read voltage applied to the first element equal to that applied to the second element.

Abstract: Using a shorter read pulse width may increase read window in some embodiments. This may allow the use of higher voltages with less likelihood of a read disturb where a bit unintentionally changes phase.

Abstract: A semiconductor memory device includes a plurality of word lines, a plurality of bit lines, a plurality of memory elements arranged at intersecting points between the word lines and the bit lines, respectively, a row selector selectively activating the word lines, a plurality of write drivers provided to correspond to the bit lines, and supplying a write current to the corresponding bit lines, respectively, a plurality of write control circuits controlling operations performed by the corresponding write drivers, respectively, and a column selector selecting the write control circuits. The column selector sequentially selects a predetermined write control circuit per one clock in a state of activating a predetermined word line, and the selected write control circuit activates one corresponding write driver over a period of one clock or more.

Abstract: A method and enhanced Static Random Access Memory (SRAM) redundancy circuit reduce wiring and the required number of redundant elements, and a design structure on which the subject SRAM redundancy circuit resides is provided. A bitline redundancy mechanism allows the swapping of a pair of bitlines for a redundant pair of bit columns. Two of the adjacent bitlines are swapped out at a time, one even and one odd. The swap is accomplished by steering the data around the bad columns and adding redundant columns on the end that are steered in when needed.

Abstract: A non-volatile semiconductor memory device may include a memory cell array that may include a plurality of memory transistors; a input circuit that may control a voltage level of an internal reference voltage and a delay time of an internal clock signal in response to an MRS trim code or an electric fuse trim code, and that may generate a first buffered input signal; a column gate that may gate the first buffered input signal in response to a decoded column address signal; and a sense amplifier that may amplify an output signal of the memory cell array to output to the column gate, and that may receive an output signal of the column gate to output to the memory cell array. The non-volatile semiconductor memory device may properly buffer an input signal of a small swing range.

Abstract: A flash memory device comprises an array of memory cells capable of storing different numbers of bits per cell. A page buffer circuit for the flash memory device comprises a plurality of page buffers, each operating during programming, erasing, and reading operations of the memory cells. A control logic unit controls functions of the page buffers in accordance with the number of bits stored in corresponding memory cells.

Abstract: A non-volatile semiconductor memory device includes: a memory chip configured to be electrically rewritable and store such multi-level data as being defined by n-bits/cell (where n?2); and a memory controller configured to control read and write of the memory chip, wherein the operation mode of the memory chip is changed from n-bits/cell to m-bits/cell (where m<n) when the number of late-generated defective areas is over a certain threshold value.

Abstract: A method and an apparatus for collecting data related to a status of an electrical power system, wherein data is continuously acquired from the electrical power system and is stored, at least temporarily, in a first volatile memory. Upon the occurrence of an event, the data stored in the first volatile memory is copied and permanently stored in a second non-volatile memory.

Abstract: A mini flash disk with data security function conforms to the hard disk specification of the Technical Committee T13 that describes the width of shell is 2.5 inches or 1.8 inches. The shell of the mini flash disk comprises a control chipset for connecting with the external connecting port, a plurality of connecting units connected with the control chipset, wherein the connecting units conform to the same interface specification with the control chipset. Consequently, the connecting units can connect with a flash device respectively for mirroring the data of the first flash device to be within the second flash device by control chipset, such that can ensure the data security for the mini flash disk.

Abstract: An EPROM cell includes a semiconductor substrate, having source and drain regions, a floating gate, including a semiconductive polysilicon layer electrically interconnected with a first metal layer, and a control gate, including a second metal layer. The floating gate is disposed adjacent to the source and drain regions and separated from the semiconductor substrate by a first dielectric layer, and the second metal layer of the control gate is capacitively coupled to the first metal layer with a second dielectric layer therebetween.

Abstract: A non-volatile memory having boost structures. Boost structures are provided for individual NAND strings and can be individually controlled to assist in programming, verifying and reading processes. The boost structures can be commonly boosted and individually discharged, in part, based on a target programming state or verify level. The boost structures assists in programming so that the programming and pass voltage on a word line can be reduced, thereby reducing side effects such as program disturb. During verifying, all storage elements on a word line can be verified concurrently. The boost structure can also assist during reading. In one approach, the NAND string has dual source-side select gates between which the boost structure contacts the substrate at a source/drain region, and a boost voltage is provided to the boost structure via a source-side of the NAND string.

Abstract: A non-volatile memory device includes a memory cell array and a voltage control unit. The memory cell array includes a plurality of memory blocks each including a plurality of cell strings. Each of the cell strings includes a first selection transistor, a second selection transistor, and at least one memory cell transistor serially connected between the first selection transistor and the second selection transistor.

Abstract: A first plane of memory cells is formed on mesas of the array. A second plane of memory cells is formed in valleys adjacent to the mesas. The second plurality of memory cells is coupled to the first plurality of memory cells through a series connection of their source/drain regions. Wordlines couple rows of memory cells of the array. Metal shields are formed between adjacent wordlines and substantially parallel to the wordlines to shield the floating gates of adjacent cells.