Abstract: A sense amplifier of a flash memory device maintains a bit line precharge level before a memory cell is sensed. The sense amplifier maintains the voltage of a bias signal sufficiently high using a second precharging circuit in a precharging operation to stably maintain the bit line precharge level set by a first precharging circuit. Accordingly, the sense amplifier can correctly sense an OFF cell using the stabilized bit line precharge voltage. Related methods and memory devices are also disclosed.

Abstract: A method for operating non-volatile memory having boost structures. The boost structures are provided for individual NAND strings and can be individually controlled to assist in programming, verifying and reading processes. The boost structures can be commonly boosted and individually discharged, in part, based on a target programming state or verify level. The boost structures assists in programming so that the programming and pass voltage on a word line can be reduced, thereby reducing side effects such as program disturb. During verifying, all storage elements on a word line can be verified concurrently. The boost structure can also assist during reading. In one approach, the NAND string has dual source-side select gates between which the boost structure contacts the substrate at a source/drain region, and a boost voltage is provided to the boost structure via a source-side of the NAND string.

Abstract: A method of operating a memory array includes providing an array of memory cells arranged in rows and columns. Each column comprises a NAND unit cell including a plurality of memory cells coupled together serially. The plurality of memory cells of each NAND unit cell share a common well. The common well of each column is separated from common wells of adjacent columns by an isolation region. Each NAND unit cell includes a select gate transistor coupled to a memory cell in the column. A source of the select gate transistor is coupled to the common well of the NAND unit cell. The method includes accessing a first memory cell in a column by biasing the common well of the NAND unit cell of the first memory cell differently than the common well of other NAND unit cells are biased.

Abstract: Methods and apparatuses are disclosed for programming a page of nonvolatile memory cells across multiple nonvolatile memory cells accessed by multiple word lines.

Abstract: An ODT circuit performs termination control on at least one pair of differential mode signals within a memory chip. The ODT circuit may include a switching unit. The switching unit may include a plurality of switching blocks. The switching blocks may include termination resistance devices connected in parallel between first and second differential signal lines, and connect the termination resistance devices with the differential signal lines during operation in response to an applied switching control signal.

Abstract: Methods and apparatus provide for controlling an SRAM memory, the SRAM memory including a plurality of memory cells arranged in an array of rows (word lines) and columns (bit lines), including: mirroring logic values of at least one of the bit lines to a global bit line; driving the global bit line to a pre-charge logic value in response to a clock signal that cycles at least one time during successive read and write operations to the memory cell; maintaining the global bit line at the pre-charge logic value during a write operation in which a logic value is written to the bit line that is opposite to the pre-charge logic value.

Abstract: A control signal training system in an integrated circuit comprises a signal transmitting unit, the signal transmitting unit outputting control signals and sampling clock signals, the control signals and the sampling clock signals having a predetermined time phase with respect to each other, a signal receiving unit, the signal receiving unit latching control signals in relation to the sampling clock signals, and an evaluation unit connected to a reading unit and the signal transmitting unit, the evaluation unit determining concordance of the control signals outputted by the signal transmitting unit and the control signals read out by the reading unit from the signal receiving unit, the evaluation unit adapting the time phase between the control signals and the sampling clock signals step-by-step until concordance of the control signals outputted by the signal transmitting unit and the control signals read out the reading unit from the signal receiving unit is determined by the evaluation unit.

Abstract: Systems and methods for reducing instability and writability problems arising from relative variations between a memory cell voltage (Vcell) and a logic voltage (Vdd) by inhibiting assertion of word line signals that enable accesses to the memory cells when the voltages are not within an acceptable operating range. One embodiment comprises a system having a critical condition detector configured to monitor the voltages and to determine whether the voltages are within an acceptable range. When the voltages are not within the acceptable range, the system inhibits assertion of the word lines to the memory cells. Memory accesses which fail because of the inhibited word line signals are retried by a memory controller when the critical conditions that caused the signals to be inhibited no longer exist.

Abstract: A method and enhanced Static Random Access Memory (SRAM) redundancy circuit reduce wiring and the required number of redundant elements. A bitline redundancy mechanism allows the swapping of a pair of bitlines for a redundant pair of bit columns. Two of the adjacent bitlines are swapped out at a time, one even and one odd. The swap is accomplished by steering the data around the bad columns and adding redundant columns on the end that are steered in when needed.

Abstract: A hybrid flash memory device includes an array including a first area and a second area having a larger number of stored bits per cell than the first area The device includes a hidden area including a first reserved block area and a second reserved block area, wherein the first reserved block area includes a plurality of first memory blocks having the same number of stored bits per cell as the first area, the second reserved block area includes a plurality of second memory blocks having the same number of stored bits per cell as the second area, and a flash translation layer configured to replace a bad block generated in the first main area with the first memory block and replace a bad block generated in the second main area with the second memory block, wherein the flash translation layer flexibly assigns functions of the first memory blocks or the second memory blocks depending on whether the first and second memory blocks are all used.

Abstract: A repair fuse circuit includes an address comparator, and a plurality of I/O bus select bit output units. The address comparator outputs repair signals for selecting a redundant column that will replace a fail column of a plurality of redundant columns according to a column address. The plurality of I/O bus select bit output units for outputting signals corresponding to respective bits of I/O bus repair signals for selecting an I/O bus to which the redundant column will be connected according to the repair signals.

Abstract: A memory device includes a main memory cell having a plurality of first memory cells for storing data, wherein a special block for storing a column address corresponding to a first memory cell having at least one failure is disposed in a part of area of the main memory cell; a start address block configured to store address information initiated by the special block of the main memory cell; and a repair information block configured to provisionally store the column address stored in the special block, and to output a repair controlling signal when operating the memory device.

Abstract: An integrated circuit device according to an embodiment of this invention includes: a memory having: a first port to which a first clock signal is input, and a second port to which a second clock signal is input; and a built-in self test circuit having: a first signal generating circuit to which the first clock signal is input, a second signal generating circuit to which the second clock signal is input, a clock selecting circuit to which the first and second clock signals are input and which selects and outputs one of the input clock signals, and a controlling circuit which outputs a clock requesting signal requesting one of the first and second clock signals to the clock selecting circuit, operates in accordance with the clock signal selected and output by the clock selecting circuit, and outputs a controlling signal for controlling one of the first and second signal generating circuits.

Abstract: A multichip and method of testing a multichip, the multichip including a control chip having a central processing unit (CPU) and a plurality of memories, each memory of the plurality of memories storing information related to testing the multichip, comprises connecting one of the memories to the control chip; reading, by the CPU, stored memory information from the connected one of the memories to confirm the connected one of the memories; generating a test pattern relating to the connected one of the memories confirmed by the CPU, and testing the connected one of the memories according to the test pattern.

Abstract: In a particular embodiment, a method is disclosed that includes receiving a first sense output and a second sense output of a sense amplifier at a first tri-state device coupled to a first bus, receiving the first sense output and the second sense output of the sense amplifier at a second tri-state device coupled to a second bus, and selectively activating one of the first tri-state device and the second tri-state device to drive the first bus or the second bus in response to a bus selection input.

Abstract: A semiconductor memory device includes a shared transistor controlling coupling between a bit line pair in a memory cell array and a bit line pair in a sense amplifier. After a word line is activated and the sense amplifier amplifies the potential difference between the bit lines of the bit line pair in the sense amplifier, the shared transistor is tuned OFF and precharge/equalizing circuit is activated to precharge the bit lines in the sense amplifier to a potential which is half the internal power source potential.

Abstract: A bit line dummy core-cell comprises at least a first inverter and at least a second inverter which are cross coupled to form a bistable flip-flop. The first inverter comprises a first PMOS transistor and a first NMOS transistor connected in series by means of a first internal storage node between a high reference potential and a low reference potential. The second inverter comprises a second PMOS transistor and a second NMOS transistor connected in series by means of a second internal storage node. The source of the second PMOS transistor and the second internal storage node are connected to the low reference potential so that the first internal storage node always stores a logic high level. A first access transistor is coupled between a dummy bit line providing a self-timing signal and the first internal node storing the logical high level.

Abstract: A calibration circuit for matching the output impedance of a driver by calibrating adjustments to the driver is described. The calibration circuit includes a driver circuit with a plurality of calibration transistors configured to receive a plurality of adjustment signals. The calibration circuit also includes a comparator circuit, and a binary searcher. The driver provides a signal corresponding to an output impedance to the comparator circuit. The output impedance signal is compared to a target impedance, and the comparator circuit then provides logic signals to the binary searcher representing whether the output impedance is greater than the target impedance. The binary searcher then selects a type of step size and count direction, in response to the logic signals, to count the number of steps for adjusting the calibration transistors of the driver.

Abstract: A data conversion circuit for a semiconductor memory apparatus includes a data conversion unit that has a plurality of latches for storing input data and outputting stored data as output data in response to a clock, and an operation mode selection unit that selects either a first operation mode to convert serial data to parallel data during a write operation or a second operation mode to convert parallel data to serial data during a read operation, to thereby drive the data conversion unit.

Abstract: A DRAM refresh period adjustment technique based on the retention time of one or more unused memory cell(s) having characteristics very similar to the characteristics of the memory cell(s) with the shortest retention time used in the DRAM array. In a particular implementation of the technique of the present invention, the refresh period of a DRAM array is adjusted through the use of one or more of the DRAM bits that fail to meet the retention time requirement and have, therefore, been replaced by redundant DRAM bits. These replaced bits are then used to indicate the refresh period for the DRAM is the maximum it can be for the DRAM under then current operating conditions.

Abstract: A circuit for generating a voltage of a semiconductor memory apparatus includes a control unit that outputs a driving control signal in response to an enable signal and a burn-in signal, a first voltage generating unit that generates and outputs a first voltage in response to the enable signal, and a voltage maintaining unit that maintains the first voltage in response to the driving control signal.

Abstract: A memory includes an input pad for receiving an input signal and a first circuit. The first circuit is configured to receive a first signal in response to the input signal and receive a second signal and provide a third signal in response to at least one of the first signal and the second signal indicating a request to enter a deep power down mode. The memory includes a second circuit configured to provide a fourth signal indicating an entry to the deep power down mode in response to the third signal.

Abstract: Multi-bank semiconductor memory devices are provided having optimized memory block layouts and data line routing to enable chip size reduction and increase operating memory access speed.

Abstract: A control apparatus of a GIO line includes a plurality of GIO line termination units, and a GIO control unit for generating a control signal to activate an operation of a specific one of the plurality of GIO termination units according to a data transmission method. Further, a method of controlling a GIO line through GIO termination includes the step of generating a control signal to activate an operation of a specific one of a plurality of GIO termination units according to a data transmission method.

Abstract: Semiconductor memory devices having hierarchical word line structures are provided in which sub-word line driver circuitry is designed with layout patterns that enable increased integration density and high performance operation.

Abstract: An integrated circuit device includes: a RAM block including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a wordline control circuit; and a data line driver block which drives a plurality of data line groups of a display panel based on data supplied from the RAM block. The data line driver block includes first to Nth (N is an integer larger than one) divided data line driver blocks, each of the first to Nth divided data line driver blocks driving a different data line group of the data line groups. The wordline control circuit drives an identical wordline N times from among the wordlines in one horizontal scan period of the display panel. The first to Nth divided data line drivers are disposed along a first direction in which the bitlines extend.

Abstract: Apparatus and method of training a data transfer channel between a memory controller and a memory device connected to each other via a data signal transfer channel and an address signal transfer channel. The method comprises reading test data from a latching circuit connected to both an address signal input and a data or control signal output of the memory device or from a read only memory in the memory device, transferring a read signal representing the test data via the data signal transfer channel, detecting data from the read signal with a delay relative to a read clock signal; repeating the transferring, detecting steps, each time detecting the data at a different value of the delay; selecting a value of the delay, preferably a value at which the detected data equal the test data; and setting the delay to the selected value.

Abstract: An adjustably supported mortar mixer includes a frame which supports the mixer for processing and mixing mixable components at selected vertical heights. The frame is supported by three or four adjustable supports with either two or four of the adjustable supports arranged in a substantially A-frame configuration. Adjustment of the supports in the A-frame configuration simultaneously effects, in a single action, both a vertical displacement and a horizontal displacement of the corresponding support base so as to automatically provide an increased mixer support width at an increased mixer height, and a decreased mixer support width at a decreased mixer height. By virtue of the ability to adjust simultaneously both the vertical and horizontal displacement with a single action, the method of adjustably supporting the mixer is easier, faster, and safer.

Abstract: A fluid mixing apparatus configured to be connected to a tub, a liquid supply, and a gas supply, includes: a 1st pressurable liquid-storing chamber for storing liquid and mixing gas into liquid; a 2nd pressurable liquid-storing chamber for storing liquid and mixing gas into liquid; and a connection path connecting the 1st and 2nd liquid-storing chamber for supplying liquid from the 1st liquid-storing chamber to the 2nd liquid-storing chamber where the pressure inside the 2nd liquid-storing chamber is lower than the pressure inside the 1st liquid-storing chamber. The 2nd liquid-storing chamber is disposed downstream of the 1st liquid-storing chamber with respect to liquid flow.

Abstract: A two-stage mixing system, apparatus, and method produces a solution including a first substance and a second substance in a predetermined ratio by first mixing the first substance with a first liquid to produce a first solution and then mixing the first solution with the second substance to produce a second solution. Multiple batches of second solution may be produced from a single batch of first solution. Multiple batches of second solution may be produced in parallel.

Abstract: A batter mixing apparatus and process is disclosed for mixing a dry batter mix with a predetermined amount of water is adapted to continuously measure the temperature and the viscosity, in centipoises, with an inline viscometer. The controls of the apparatus are fully automated using a programmable logic controller in conjunction with a touchscreen display that provides real-time data, process control parameters, and a choice of batter recipes. Once the batter has reached a desired viscosity, a variable speed feed pump is used to pump the batter to a batter applicator where a food product is coated. Excess batter from the applicator is collected and returned to the mixing apparatus via a pump. The viscosity and temperature of the returned batter is measured and adjusted automatically with dry batter mix or water in order to satisfy the set parameters.

Abstract: Seismic sensor systems and sensor station topologies, as well as corresponding cable and sensor station components, manufacturing and deployment techniques are provided. For some embodiments, networks of optical ocean bottom seismic (OBS) stations are provided, in which sensor stations are efficiently deployed in a modular fashion as series of array cable modules deployed along a multi-fiber cable.

Abstract: Seismic sensor systems and sensor station topologies, as well as corresponding cable and sensor station components, manufacturing and deployment techniques are provided. For some embodiments, networks of optical ocean bottom seismic (OBS) stations are provided, in which sensor stations are efficiently deployed in a modular fashion as series of array cable modules deployed along a multi-fiber cable.

Abstract: A method and apparatus for evaluating a bond between a formation and a bonding material. The method includes emitting a shear wave into the tubular, recording the response of the shear wave, and evaluating the response to obtain bond information. The bond information includes bond material thickness and efficacy of the bond between cement and formation. The method includes studying and utilizing the time lag of the direct wave and wave events, as well as the interference of these waves on a spectral graph. A calibration method is included as well.

Abstract: Disclosed is a method for locating a seismic event. The method includes processing seismic data from at least one seismic receiver to validate a potential seismic event, computing a signal travel time between at least one node in an area of interest and the at least one seismic receiver, adjusting the seismic data according to the travel time, and identifying a location of the seismic event based on the adjusted seismic data. Systems for locating a seismic event are also disclosed.

Abstract: Seismic sensor systems and sensor station topologies, as well as corresponding cable and sensor station components, manufacturing and deployment techniques are provided. For some embodiments, networks of optical ocean bottom seismic (OBS) stations are provided, in which sensor stations are efficiently deployed in a modular fashion as series of array cable modules deployed along a multi-fiber cable.

Abstract: The disclosed embodiments include a method, system, and device for conducting ultrasound interrogation of a medium. The novel method includes transmitting a non-beamformed or beamformed ultrasound wave into the medium, receiving more than one echoed ultrasound wave from the medium, and converting the received echoed ultrasound wave into digital data. The novel method may further transmit the digital data. In some embodiments, the transmitting may be wireless. The novel device may include transducer elements, an analog-to-digital converter in communication with the transducer elements, and a transmitter in communication with the analog-to-digital converter. The transducers may operate to convert a first electrical energy into an ultrasound wave. The first electrical energy may or may not be beamformed. The transducers also may convert an echoed ultrasound wave into a second electrical energy.

Abstract: A seabed resource exploration system includes: a vibrator 1 for transmitting a sound wave into the sea and receiving a scattered wave in which the sound wave is reflected on a boundary surface between seawater and a mixture of methane gas and methane hydrate, which exists in the seawater; and an analyzer 17 for determining that the methane hydrate exists in a seabed immediately under the mixture when backscattering strength, calculated by the transmitted sound wave and the received scattered wave, is in a predetermined relationship. The predetermined relationship satisfies a relationship that a maximum value of the backscattering strength is ?60 to ?30 dB and an average value of the backscattering strength is ?70 to ?50 dB. The backscattering strength is on a grid obtained by cutting the mixture into round slices in the depth direction by a predetermined width, in a range from the seabed to a predetermined height.

Abstract: Seismic sensor systems and sensor station topologies, as well as corresponding cable and sensor station components, manufacturing and deployment techniques are provided. For some embodiments, networks of optical ocean bottom seismic (OBS) stations are provided, in which sensor stations are efficiently deployed in a modular fashion as series of array cable modules deployed along a multi-fiber cable.

Abstract: Seismic sensor systems and sensor station topologies, as well as corresponding cable and sensor station components, manufacturing and deployment techniques are provided. For some embodiments, networks of optical ocean bottom seismic (OBS) stations are provided, in which sensor stations are efficiently deployed in a modular fashion as series of array cable modules deployed along a multi-fiber cable.

Abstract: An electronic time switch for switching a power source to a load, such as a lighting circuit, is disclosed, as well as a method for its use. An electric switch has an on and an off position for either connecting or disconnecting the power source to the load. A switch actuating means controlled by a microcontroller is connected to the electric switch and is adapted for actuating the switch into either its on or off positions according to a schedule. The microcontroller includes a clock means, a time update means, and a memory means for storing the schedule. The time update means includes a receiver for receiving a time signal from a time signal source, such as a WWVB radio broadcast, or from an earth orbiting satellite, such as a GPS satellite or the like.

Abstract: A water-proof watch case and a method for manufacturing the same are disclosed. First, a design of a case and a bottom lid is decided, and a mold according to the design is fabricated accordingly. Next, a hard plastic material is injected into the mold to form the case and the bottom lid. Next, a soft plastic material is injected at an outer rim of the case to form at least one button, and a soft plastic material is injected at a conjunction between the case and the bottom lid to form a water-proof gasket. Finally, the hard and soft plastic materials are heated to adhere the button and the water-proof gasket to the outer rim of the case and the conjunction between the bottom lid and the case respectively.

Abstract: A time projection clock comprises an operating circuit including a clock circuit for time keeping and producing a time signal, and a projection unit incorporating a projection circuit for receiving the time signal from the clock circuit and, in response, projecting a corresponding time image onto an external surface, based on the time signal. The projection circuit comprises a super-bright LED for emitting a light beam, a driver for driving the super-bright LED, and an LCD panel located in front of the super-bright LED and intersected by the light beam to produce the time image.

Abstract: The alarm watch includes a mechanical movement which drives time display means including at least a first hour hand (17) and a first minute hand (13) mounted above a first dial. The alarm watch also includes an alarm mechanism able to release an alarm at a predetermined alarm time, manually determined every twenty-four hours, and means for displaying the predetermined alarm time. The alarm time display means include at least a second hour hand (33) provided for displaying the alarm time in twelve hours, and an indicator (52) with two positions provided for specifying whether the alarm time is comprised between midnight and midday (AM) or comprised between midday and midnight (PM).

Abstract: The invention concerns a timepiece movement of the type including a fixed support (23), fitted with a display module (24) including a central bridge (26) secured to said support (22) and an annular display member (28) with an axis AA, mounted to rotate freely substantially around the bridge (26), abutting on the support (22). The display member (28) includes a contact surface (37) and the bridge (26) includes at least one positioning surface (40) cooperating with the contact surface (37) so as to position the display member (28) axially on the support (22).

Abstract: Assembly element (18) made in a plate of brittle material, such as silicon, in particular for a timepiece (10), including an aperture (32) provided for the axial insertion of an arbour (26), the inner wall (33) of the aperture (32) including elastic structures (34) which are etched into the plate and which each include at least one support surface (36, 38) for gripping the arbour (26) radially in order to secure the assembly element (18) relative to the arbour (26). Each elastic structure (34) is formed by a fork which is connected to the inner wall (33) of the aperture by a bridge of material (40) and which includes two branches (42, 44) extending, on either side of the bridge of material (40), generally towards the arbour (26). Each branch (42, 44) includes a support surface (36, 38) in proximity to the free end (46, 48) thereof. The invention also proposes a timepiece fitted with an assembly element (18) of this type.

Abstract: The magnetic control device (1) for a timepiece comprises a sealed tube (3) which comprises a blind end inserted into an opening of the timepiece, whereas the other end of the tube opens towards the outside. A control stem (12) is provided in order to slide inside the tube (3). It carries a magnet (21) which is displaced integrally with the stem inside the tube. By manipulating the end of the stem which emerges from the tube (3), the wearer of the watch can make the magnet selectively occupy three positions. A first and a second magnetic sensor (22, 23) with two states are disposed inside the timepiece along the sealed tube so that three different combinations of a state of the first sensor (22) with a state of the second sensor (23) are respectively associated with three predefined positions of the first magnet (21).

Abstract: Assembly element (18) made in a plate of brittle material, including an aperture (32) provided for the axial insertion of an arbour (26). The inner wall (33) of the aperture (32) includes elastic structures (34), which are etched into the plate and which each include at least one support surface (36) for gripping the arbour (26) radially in order to secure the assembly element (18) relative to the arbour (26). The assembly element (18) includes a first series (S1) of elastic structures (34) etched in a top layer (39) of the plate and a second series (S2) of elastic structures (34) etched in a bottom layer (41) of the plate. A timepiece may be fitted with this assembly element.

Abstract: An information storage medium has user data areas and additional data areas, and sync patterns to distinguish the additional data areas from the user data areas. The information storage medium includes a user data area in which user data is recorded and an additional data area located in at least one of areas before and after the user data area. Second sync patterns used in the additional data area are different from first sync patterns used in the user data area.

Abstract: A write-once disc includes: a plurality of update areas in which a predetermined kind of updated information is recorded; at least one main access information area in which main access information is recorded, the main access information indicating a final update area in which finally updated information is recorded among the plurality of update areas; and at least one sub access information area in which sub access information is recorded, the sub access information indicating a location of the finally updated information recorded in the final update area. Accordingly, an access time for reading a predetermined kind of information required to use the write-once disc can be reduced.