Abstract: In order to provide a semiconductor IC unit such as a microprocessor, etc., which satisfies both fast operation and lower power consumption properties with its high quality kept, the semiconductor IC unit of the present invention is composed so as to include a main circuit (LOG) provided with transistors, which is formed on a semiconductor substrate, and a substrate bias controlling circuit (VBC) used for controlling a voltage to be applied to the substrate, and the main circuit includes switching transistors (MN1 and MP1) used for controlling a voltage to be applied to the substrate and control signals output from the substrate bias controlling circuit is entered to the gate of each of the switching transistors and the control signal is returned to the substrate bias controlling circuit.

Abstract: Certain aspects of a method and system for a process sensor to compensate SoC parameters in the presence of IC process manufacturing variations are disclosed. Aspects of one method may include determining an amount of process variation associated with at least one transistor within a single integrated circuit. The determined amount of process variation may be compensated by utilizing a process dependent current, a bandgap current, and a current associated with a present temperature of the transistor. The process dependent current, the bandgap current and the current associated with the present temperature of the transistor may be combined to generate an output current. A voltage generated across a variable resistor may be determined based on the generated output current.

Abstract: A low-voltage band-gap reference voltage bias circuit according to the present invention can provide a stable reference voltage at a supply voltage of about 1V or lower irrespective of a power supply voltage or temperature variation by flowing a PTAT mirror current into diodes and resistors and obtaining the average of voltages at two nodes. Furthermore, the low-voltage band-gap reference voltage bias circuit has simple configuration, reduces the resistance of a resistor that occupies a large chip area, uses small-sized diodes, and thus increases the integration density of the band-gap reference voltage bias circuit.

Abstract: The invention relates to electronic integrated circuits capable of operating either in active mode or in standby mode and to have, in standby mode, a very low current consumption. According to the invention, the leakage current of a power transistor inserted in series between a supply terminal and an active circuit is controlled by a gate reverse overbias in the following manner: a first reference transistor, and a second reference transistor identical to the first, are biased with the same gate reverse overbias voltage as the power transistor, the first transistor having its source linked to the supply terminal, and the second reference transistor having its source linked to its drain. The leakage currents in these two transistors are compared, and it is considered that the optimal bias of the gate is obtained when the leakage currents are equal. Applications to circuits supplied by a battery or a cell (portable telephones, cameras, portable computers, etc.).

Abstract: An output circuit for a bus whose output node is connected to a bus, including a first current source connected to a first reference potential, a first semiconductor switching element connected between the first current source and the output node, a current control circuit for controlling the first semiconductor switching element such that the first current source and the output node are connected when a voltage of the output node is lower than a reference voltage, and the first current source and the output node are disconnected when a voltage of the output node is higher than the reference voltage, and a voltage generating circuit which is connected between the output node and a second reference potential, and includes a second semiconductor switching element turned on/off based on an output control signal.

Abstract: In some embodiments, an array of sleep transistors is provided, wherein a combination of said transistors may be enabled during an active mode to reduce leakage depending on the leakage characteristics of a chip or associated chip.

Abstract: A semiconductor integrated circuit device for fast and low power operations, comprising a plurality of circuit blocks of a chip, each of which has a plurality of states with different power consumption values. A power management circuit determines the state of each of the circuit blocks so as not to exceed a maximum power consumption value of the semiconductor integrated circuit device by considering the power consumption of each circuit block and by each state transition in each circuit block. The maximum power consumption value may be preset or adjustable after fabrication.

Abstract: A diode connected P-type CMOS transistor is operated in the sub-threshold area and, with a bypass capacitor, operates as a low pass audio filter. The equivalent resistance of the CMOS transistor in the sub-threshold range is very high—in the gigaOhm range. With this size resistor, a capacitor in the 1-25 pF range may be used to provide filtering capabilities with break points in the 1-10 Hz frequency range. Such a filter provides an effective low pass filter that attenuates audio frequency signals. The 1-25 pF capacitors use little chip area making the arrangement practical for integrating on an IC with the audio signals. In one embodiment, a digital signal and the audio signals share one pin, where the audio signal appears only when the digital signal is high. In this case, the audio signal filtered out from the digital high signal. The filtered digital signal drives digital circuitry while the audio signal is directed to other audio circuitry.

Abstract: A reception device that receives a modulation signal being a result of digital modulation of a carrier is disclosed. The device includes: a demodulation section that demodulates the modulation signal into a demodulation signal including an I component and a Q component; a numerically controlled oscillation section that generates a signal of predetermined phase; a phase error detection section that detects a phase error between a phase of a symbol of the demodulation signal and the predetermined phase of the signal generated by the numerically controlled oscillation section; a phase rotation section that rotates the phase of the symbol of the demodulation signal in accordance with the phase error; a loop filter that filters the phase error, and controls the numerically controlled oscillation section; and a gain control section that controls a gain of the loop filter based on a modulation technique of the modulation signal.

Abstract: Methods and systems for fast calibration to cancel phase feedthrough are disclosed and may comprise individually activating each of n binary-weighted cells utilizing a control signal in a power amplifier driver (PAD) and measuring the output signal, or offset, in response to a null signal applied to an input of each binary-weighted cell. This offset may be fed back, summed, and adjusted until the measured PAD output may be minimized. This calibrated offset may cancel phase feedthrough of the PAD, and the calibrated offset for each binary-weighted cell may be stored in a lookup table. The control signal may also be utilized for controlling the output power of the PAD by activating appropriate binary-weighted cells. For each of the 2n output powers, a calibrated offset is calculated utilizing a weighted sum of the stored offsets for the activated binary-weighted cells.

Abstract: A radio frequency (RF) amplifier has a driver device, an output device, and first and second impedance transformation networks. In a first operating mode the output device is turned on and the first impedance transformation network presents a first load impedance to the output device. In a second operating mode, the output device is turned off and the second impedance transformation network connects an output of the driver device to the first impedance transformation network and presents a second load impedance to the driver device. The second load impedance is greater than the first load impedance.

Abstract: A multi-stage amplifier configured for processing a received baseband signal comprises a plurality of fixed-gain amplifier stages and an automatic gain control (AGC) module. Each amplifier stage further comprises a switch and a bypass circuit. The AGC module is configured for controlling the switch for bypassing at least one of the amplifier stages. The multi-stage amplifier may be configured to perform fine gain adjustment and coarse gain adjustment, wherein fine gain adjustment may comprise adjusting a load-resistor value in at least one amplifier and coarse gain adjustment may comprise bypassing one or more fixed-gain amplifier stages.

Abstract: A radio frequency integrated circuit (RFIC) includes a silicon substrate, CMOS processing circuitry, and a bipolar power amplifier module. The CMOS processing circuitry is on the silicon substrate. The bipolar power amplifier module is on the silicon substrate and is operable in a 5 GHz frequency band.

Abstract: Aspects of a method and system for enhancement of power amplifier (PA) efficiency through controlled variation of gain in a power amplifier driver are presented. Aspects of the system may comprise an envelope detector that enables detection of an amplitude of an analog input signal. The envelope detector may enable computation of a first gain value based on the detection. A second gain value may be computed based on the first gain value. A PA may enable generation of an analog output signal based on the analog input signal, the first gain value and the second gain value.

Abstract: A radio frequency (RF) front-end includes a plurality of power amplifier modules and a plurality of impedance matching circuits. Each of the plurality of impedance matching circuits includes an input connection and an output connection, wherein outputs of the plurality of power amplifier modules are coupled to corresponding input connections of the plurality of impedance matching circuits to provide a desired loading of the plurality of power amplifier modules and wherein the output connections of the plurality of impedance matching circuits are coupled together to add power of the plurality of power amplifiers.

Abstract: A system for cyclical noise removal from a transient signal is employed with a transient sensor for a signal. A signal conditioner is connected to the transient sensor for processing the signal. A transient digitizer captures the processed signal including capture of a sufficient period of time before the transient to accurately analyze the cyclic noise, capture of a period of time to be sure the transient is not effecting the ambient and capture of the period of the transient. A signal processor is employed for filtering of a non-cyclic transient signal. An embedded computer with associated software performs an analysis of the ambient background just prior to the time that the transient signal of interest is detected, performs an analysis of the signal of interest, extends the analyzed ambient background signal through the period of time during which the transient signal is occurring and subtracts the background from the transient signal.

Abstract: There is provided a feed-forward amplifier which enables a predistortion circuit to obtain sufficient distortion compensation effects even if ambient temperature or the like changes.

Abstract: A smart protection circuit to prevent possible circuit malfunction or damage due to sudden power source voltage fluctuation is introduced. In case of quick and large voltage fluctuation in power supply, a control signal is activated to stop power transistor switching. When power supply is stable at a lower or higher operating voltage, the switching circuit is able to return to normal operation.

Abstract: Methods and systems for digitally controlling transmitter gain compensation are disclosed. Aspects of one method may include applying an effective negative resistance to differential outputs of amplifying circuitry to compensate for gain changes that may be due to temperature changes. The effective negative resistance may be provided via a plurality of load circuits coupled in parallel to the differential outputs. The plurality of load circuits may have similar effective negative resistances, or the plurality of load circuits may be binary weighted. Each load circuit may be selected via digital control signals that may enable the load circuit. This may allow adjusting of the effective negative resistance by selecting different load circuits.

Abstract: Aspects of a method and system for a low power fully differential noise canceling low noise amplifier (NC LNA) are provided. The NC LNA may receive signals via a single ended input and may generate an amplified symmetric differential output from the received signals. The NC LNA may utilize capacitor dividers, such as a capacitor bank, in the single ended input in order to provide impedance transformation that enables low power operation and matching to an input port. The NC LNA may generate one portion of the amplified symmetric differential output via a voltage divider, which may comprise a plurality of capacitors, such as a capacitor bank. The NC LNA may be implemented utilizing one or more circuits.

Abstract: An amplifier includes a differential amplifier stage, a voltage amplification stage and a power output stage. The bias level of the output stage is proportional to current through the voltage amplification stage. The voltage amplification stage includes a current mirror whereby controlled current through a first leg of the current mirror controls current through the remaining, second leg, which, in turn, determines the bias level of the power output stage. Control circuitry senses a parameter of the amplifier, such as DC bias or input signal level to generate a control signal which is applied to the first leg of the current mirror to thereby control bias level of the power output stage.

Abstract: A variable bias current is provided for the differential pair of an operational transconductance amplifier to improve the gain performance, especially to overcome the slew rate limit of the operational transconductance amplifier. The bias current is adjusted according to the differential input to the differential pair, the difference between the currents of the differential pair, or any one of the currents of the differential pair.

Abstract: An amplifier circuit including a plurality of CMOS (Complementary Metal Oxide Semiconductor) inverter circuits connected in parallel with each other. The CMOS inverter circuits each include a first PMOS (P-channel Metal Oxide Semiconductor) transistor, a first NMOS (N-channel Metal Oxide Semiconductor) transistor, gates of the first PMOS and NMOS transistors, a second PMOS transistor, a first switch connected to a gate of the second PMOS transistor, a second NMOS transistor, and a second switch connected to a gate of the second NMOS transistor.

Abstract: The invention relates to a current pre-amplifier (11) with an input (N1) capable of receiving or supplying an input current (i3) with at least one pulse, wherein the pre-amplifier comprises a regulated cascode stage comprising an input transistor (M1) and a first current generator (S1) as well as an output transistor (M2) and a second current generator (S2), wherein said pre-amplifier comprises: detection means (M5, M6) capable of detecting an input current pulse (i3), and feedback means (M3, M6, M4, M5, R1, C1, M3, M7, M8, R2, C2) capable of increasing the current supplied by the first and/or the second current generator during the entire detection of the input current pulse.

Abstract: Aspects of a method and system for a highly efficient power amplifier (PA) utilizing dynamic biasing and predistortion are presented. Aspects of the system may include a processor that enables computation of a value of a variable bias component of a bias current based on a bias slope value and an amplitude of an envelope input signal. The processor may enable computation of a value of the bias current based on the selected constant bias current component value and the variable bias current component value. A PA may enable generation of an output signal in response to a generated baseband signal by utilizing the bias current to amplify an amplifier input signal. The bias current may be generated based on the envelope input signal. A feedback signal may be generated based on the output signal, which may be used to predistort a subsequent baseband signal.

Abstract: A signal amplifier circuit comprises a signal amplifier having an input for receiving an ac signal to be amplified and an amplifier biasing arrangement coupled between the signal input and a dc voltage line, the arrangement comprising a diode means and a bootstrapping amplifier connected across the diode means.

Abstract: An RF amplifier can include a differential inductor for single-ended-to-differential signal conversion. With a center tap of the differential inductor coupled to signal ground and the RF input signal coupled to one of the end taps of the inductor, the negative of the RF input signal is obtained at the other end tap of the inductor. The differential RF signal produced can be coupled to a differential transistor amplifier that has cross-coupling capacitances, improving the signal balance of the differential output signal.

Abstract: A power amplifier amplifying an input signal is provided, comprising a power amplifier circuit, a bias circuit, and a compensation circuit. The power amplifier circuit has an input impedance responsive to the input signal, and amplifies the input signal to generate an output signal. The bias circuit is coupled to the power amplifier circuit, generates a DC bias signal to the power amplifier so that the power amplifier amplifies the input signal. The compensation circuit is coupled to the power amplifier circuit, provides a compensation impedance responsive to the input signal such that a combination of the input impedance and the compensation impedance is substantially constant regardless of the input signal.

Abstract: A circuit for broadband amplification is provided. The circuit includes an input HF_IN and an output HF_OUT, a first 90° hybrid coupler being connected to the input HF_IN of the circuit and a second 90° hybrid coupler being connected to the output HF_OUT of the circuit, and two amplifier stages being connected in parallel between the first and the second 90° hybrid coupler, the 90° hybrid couplers being hybrid couplers having an operating range of 1/n octaves between a lower frequency value and an upper frequency value, n?N\{0}, i.e., n is an element of the natural positive whole numbers in such a way that the upper frequency value is greater than the lower frequency range and simultaneously less than two times the value of the lower frequency range, and the amplifier stages being based on transistors having a III-nitride, or SiC, or diamond basis.

Abstract: In some embodiments, a chip includes first and second sub phase lock loops (sub-PLLs) including first and second voltage controlled oscillators (VCOs) to provide first and second VCO output signals and first and second feedforward divider circuits to divide first and second frequencies of the first and second VCO output signals by first and second division factors. The chip also includes phase locked loop control circuitry to select the first and second division factors. Other embodiments are described and claimed.

Abstract: An adaptive phase-locked loop (PLL) circuit produces an output signal having a frequency in reference to the frequency of a reference signal. The PLL circuit includes an oscillator configured to generate the output signal according to a frequency control signal, and a processing circuit configured to generate a feedback signal deriving from the output signal. An adjustable shift circuit is provided to time-shift the feedback signal. The PLL further includes a phase comparison circuit configured to generate a phase error signal indicating a phase error between the time-shifted feedback signal and the reference signal, and a control circuit configured to generate the frequency control signal based on the phase error signal. The adjustable shift circuit adjusts a time-shift amount to time-shift the feedback signal according to the phase error signal.

Abstract: Aspects of a method and system for a fast phase-locked loop (PLL) close-loop settling after an open-loop voltage controlled oscillator (VCO) calibration are provided. A fractional-N PLL synthesizer may comprise a VCO, a phase-frequency detector (PFD), a D flip-flop, a divider, a charge pump, and a loop filter. The synthesizer may disable the PFD based on a control signal indicating the start of VCO open-loop calibration. After open-loop calibration, the synthesizer may subsequently enable a PLL closed-loop settling and may enable the PFD to control the charge pump when the input reference signal phase lags a phase of a divider signal generated by the divider. The D flip-flop may enable and disable the PFD. During open-loop calibration, the loop filter may be discharged via a leakage current in the charge pump. During closed-loop settling, the loop filter may be charged by the charge pump via control of the PFD.

Abstract: Aspects of a method and system for implementing a low power, high performance fractional-N PLL synthesizer are provided. The synthesizer comprises a reference generator/buffer, a charge pump, a divider, a VCO, a loop filter, and a phase-frequency detector (PFD). The reference generator/buffer may increase the frequency of the input reference signal to the PFD. The PFD may generate a single signal for controlling the charge pump utilizing the increased frequency input reference signal and a divider signal generated by the divider whose input frequency may be substantially the same as that of a VCO output signal. The single signal charges a charge up portion of the charge pump and a charge down portion is charged by a leakage current. The VCO signal may be generated based on a filtered output of the charge pump generated by the loop filter. The divider may utilize true single phase clock (TSPC) logic.

Abstract: A phase locked loop with improved lock time is achieved using a controller coupled to receive a reference signal and operable to generate a frequency divider control signal based upon the reference signal to control operation of a frequency divider. The PLL further includes a phase frequency detector for producing an error signal indicative of a difference in phase or frequency between the reference signal and a feedback signal, a charge pump for generating a current pulse proportional to the error signal, a loop filter for filtering the current pulse to produce a control voltage and a voltage controlled oscillator for producing an oscillation based upon the control voltage. The frequency divider is coupled to receive the oscillation and is operable to divide the oscillation by a divide ratio to produce the feedback signal.

Abstract: An integrated circuit radio transceiver and method therefor includes capacitive loop filter with selectable capacitive elements that are operable to adjust a signal level provided to a voltage controlled oscillator to control a frequency of an output signal of the oscillator. A plurality of switches are controlled by logic to define a discharge mode, a charge mode and charge sharing mode in which a plurality of capacitive elements share charge while generating the input voltage to the oscillator.

Abstract: A voltage-controlled ring oscillator comprises a ring oscillator having a plurality of differential delay stages for generating signals having a common programmable oscillation frequency with different phases, and a pair of single-sideband mixers coupled to the differential delay stages for producing in-phase and quadrature phase signals having a frequency that is higher than the oscillation frequency.

Abstract: A programmable reference-less oscillator provides a wide range of programmable output frequencies. The programmable reference-less oscillator is implemented on an integrated circuit that includes a free running controllable oscillator circuit such as a voltage controlled oscillator (VCO), a programmable divider circuit coupled to divide an output of the controllable oscillator circuit according to a programmable divide value. A non-volatile storage stores the programmed divide value and a control word that controls the output of the controllable oscillator circuit. The control word provides a calibration capability to achieve a desired output frequency in conjunction with the programmable divider circuit. Open loop temperature compensation is achieved by adjusting the control word according to a temperature detected by a temperature sensor on the integrated circuit. Additional clock accuracy may be achieved by adjusting the control word for process as well as temperature.

Abstract: In a voltage controlled oscillation circuit including a cascade connection of a voltage-to-current conversion circuit (310) for generating an input voltage converted current which is a current corresponding to an input voltage and a current controlled oscillation circuit (120) of which an oscillation frequency varies according to the input voltage converted current, the voltage-to-current conversion circuit (310) includes a first current source for outputting a current in proportion to the input voltage and a plurality of second current sources for outputting a current in proportion to a voltage obtained by shifting the input voltage. Then, a current obtained by adding a current output from the first current source and currents output from the plurality of current sources is output as the input voltage converted current to the current controlled oscillation circuit (120).

Abstract: Aspects of a method and system for use of true single phase clock (TSPC) logic for a high-speed multi-modulus divider in a phase locked loop (PLL) are provided. A fractional-N PLL synthesizer may comprise a divider that generates a divider signal from a VCO output reference signal. The divider may comprise at least one divider stage that utilizes true single phase clock (TSCP) logic D flip-flops. The first divider stage may operate at substantially the same frequency as that of the VCO signal. The divider may also re-synchronize the VCO signal and the divider signal by using at least two re-synchronization stages that utilize a TSCP logic D flip-flop and a stage for adjusting duty-duty cycle of the divider signal. The TSCP logic D flip-flops circuitry may be integrated with a two-input NAND gate or a three-input NAND gate to speed up the operation of the divider.

Abstract: This invention is directed to achieve the oscillator circuit with a shorter oscillation stabilizing period and a lower consumption of the electric current. The oscillator circuit 10 has the amplifier circuit (inverter circuit 11), and the clock signal CLK is outputted from the output terminal of the inverter circuit 11. The inverter circuit 11 is configured from the first inverter 12 and the second inverter 13. The inverter circuit 11 is connected to the control circuit 30 and the control signal Ctrl controls the driving capacity of the inverter circuit 11. For example, high level control signals Ctrl 1 (H) and Ctrl 2 (H) are supplied to the first and the second inverters 12, 13 for a certain period of time right after the oscillator circuit 10 starts its operation until the oscillation is stabilized, operating both inverters. Then, either the first inverter 12 or the second inverter 13 continues its operation and the other inverter stops the operation.

Abstract: There is provided a resonance circuit using piezoelectric vibrator such as a quartz resonator, a coil, a capacitor, or an element equivalent to them in combination. When two resonance circuits having different resonance frequencies are combined, it is possible to configure an oscillation circuit and a filter capable of freely adjusting the frequency characteristic by utilizing the phenomenon that by changing the excitation current or voltage of the respective resonance circuits independently from each other, antiresonance frequency of the entire composite resonance circuit can be changed.

Abstract: An nth-order oscillator system for providing a resonating signal, a method of generating a resonating signal and a communications system. In one embodiment, the nth-order oscillator system, n being greater than two, includes (1) an amplifier configured to provide an intermediate signal and (2) a feedback loop including an nth-order complex LC tank and configured to generate the resonating signal by feeding back a complex-filtered form of the intermediate signal to the amplifier.

Abstract: A programmable varactor apparatus may include multiple binary weighted varactors controlled by multiple digital varactor bits. A programmable varactor apparatus may include a plurality of binary weighted varactors, and a control to selectively disable one or more of the plurality of binary weighted varactors to decrease an effective capacitance of the programmable varactor apparatus. A method for changing an effective capacitance of a programmable varactor apparatus may include providing a plurality of binary weighted varactors, and disabling one or more of the plurality of binary weighted varactors to decrease the effective capacitance of the programmable varactor apparatus.

Abstract: Disclosed herein are embodiments of controllably variable capacitor loads that may be used with delay stages or other elements, for example, in a voltage controlled oscillator.

Abstract: A mixer circuit accumulates I signal (digital signal of first channel) having its band limited by low-pass filter and first carrier signal to perform two-phase shift keying modulation thereon. An adder adds fundamental-wave component of bit clock signal BCK into Q signal (digital signal of second channel) having its band limited by the another low-pass filter to obtain a resultant added-up signal. Another mixer circuit accumulates the added-up signal and second carrier signal to perform two-phase shift keying modulation thereon. Output signals of the mixer circuits are input to another adder so that they may be added up to obtain a QPSK signal as a modulated quadrature signal. The QPSK signal contains frequency signals whose frequencies are a sum of bit clock frequency and carrier frequency and a difference between them. When demodulating, the carrier signal and the bit clock signal are reproduced using the frequency signals.

Abstract: A filtering apparatus includes a main filter, a variation detection circuit, and a variation correction circuit. The variation detection circuit includes a reference filter having at least one resistor and at least one capacitor, detects a variation of CR-product based on the resistor and the capacitor of the reference filter in response to each of a plurality of reference signals having different frequencies from each other, and then outputs a variation detection signal indicating a detected result. The variation correction circuit corrects frequency characteristics of the main filter on the basis of the variation detection signal.

Abstract: Provided are an impedance matching device of a sensor node and an impedance matching method of a sensor node. The impedance matching device comprises: a variable impedance matching unit disposed between a transmission unit, which is used for modulating a received signal to a radio frequency (RF) signal and outputting the RF signal, and an antenna and including a plurality of impedance matching circuits which have different impedance values from each other; a signal intensity measuring unit which measures the intensity of an output signal that is output through the variable impedance matching unit; and a control unit which controls one of the impedance matching circuits of the variable impedance matching unit to have an impedance value that maximizes the intensity of the output signal.

Abstract: An apparatus and method relating to a rectangular waveguide cavity launch are disclosed that enable coupling an electromagnetic wave from the top surface of a waveguide distribution network formed into a conductive plate with the narrow wall of a rectangular waveguide facing the top of the conductive plate. A resonant cavity structure is formed into a conductive plate and coupled to a waveguide also formed into the plate, the resonant cavity structure having a cavity width wider than the narrow wall dimension of the waveguide. The resonant cavity structure includes a conductive block within it having a block width substantially equal to a difference between the cavity width of the resonant cavity structure and the narrow wall dimension. The cavity launch excites and rotates a dominant waveguide mode entering the structure such that the dominant waveguide mode enters the waveguide substantially parallel to the narrow wall dimension.

Abstract: A line transition device that includes a waveguide and a microstrip line. The microstrip line is substantially orthogonal to an electromagnetic wave propagation direction in the waveguide. A choke groove crosses the microstrip line. A coupling conductor provided at a tip of the microstrip line is positioned at a terminal end of and inside the waveguide. A slit-like region where a ground conductor is not formed is substantially orthogonal to the electromagnetic wave propagation direction in the waveguide. A longitudinal length of the slit-like region is substantially equal to a quarter of the wavelength of electromagnetic waves. The slit-like region is provided such that it extends from an end of a ground conductor near a boundary between the coupling conductor and the microstrip line to reach the choke groove.

Abstract: An upper frequency-range circuit (160) includes a load element (168) exhibiting a capacitive load impedance. A first matching network (166) includes at least one nano-scale Litz wire (100) inductor. The first matching network (166) exhibits an inductive reactance that nominally matches the capacitive load reactance. An electrical conductor for providing connections for radio-frequency signals includes a plurality of nano-scale conductors (120) that are arranged in the form of a Litz wire (100). In one method of making a Litz wire (142), a plurality of carbon nanotubes (144) is placed on a substrate (146). The carbon nanotubes (144) are woven according to a predefined scheme so as to form a Litz wire (142). An inductor may be formed by manipulating the Litz wire (100) to form a coil (150).