Abstract: An integrated circuit includes a data node, an output node, and set logic coupling to the data node to the output node. The set logic changes a state of the output node in response to a change in state of the data node. The integrated circuit also includes a reset transistor, coupled to the data node, that resets the data node to a first state in response to a transition in a timing signal, an input transistor, coupled to the data node, that asserts the data node to a second state in response to receipt of a data signal, and reset logic coupled between the output node and the data node. The first reset logic resets the output node to an original state in response to resetting of the data node if the output node achieves a set state. The integrated circuit further includes feedback logic coupled between the output node and a reset input node of the reset logic that limits a duration of operation of the reset logic.

Abstract: A digital temperature detecting system for detecting a working temperature of a chip. The digital temperature detecting system includes a clock generator, for generating a first clock signal having a constant frequency; an oscillating circuit having a plurality of Not gates coupled in series, for generating a second clock signal, wherein a total number of the Not gates is an odd number; a command issuing unit connected to the clock generator, for generating a reference command signal according to the first clock signal, wherein a counting duration and a recovery duration are generated periodically in the reference command signal; and a command processing unit connected to the command issuing unit and the oscillating circuit, for generating a counting number through counting the clocks generated in the second clock signal in the counting duration and determining a working temperature according to the counting number.

Abstract: A quantum well is formed in a substrate to define a hub, ports extending from the hub, and a deflective structure in the hub. Electrons move through the hub and ports according to the ballistic electron effect. Gates control the movement of the electrons, causing them to be incident on the deflective structure on one side or the other, thus controlling the direction in which they are deflected and the port through which they pass.

Abstract: An electronic device is presented which is configured to operate as at least one logic gate. The device comprises an electrodes arrangement of one or more basic units, the basic unit being configured to define at least one vacuum space for free charged particles' propagation and comprising an input assembly for supplying an input signal, and a floating electrode assembly accommodated proximal said input assembly and serving for reading an output signal therefrom, the floating electrode arrangement being configured to define at least one source of the free charged particles and at least one target toward which the charged particles are directed and is chargeable and dischargeable in response to the input signal thereby creating the output of the basic unit.

Abstract: A sampling circuit includes a sampling unit, a first delay chain, an inverter, and a second delay chain. The sampling unit detects edge triggers of a first delayed signal and a second delayed signal for sampling input data to generate output data signal; the first delay chain is coupled to the sampling unit for delaying a sampling clock signal to output the first delayed signal; the inverter inverts the sampling clock signal to generate an inverted sampling clock signal; and the second delay chain is coupled to the inverter and the sampling unit for delaying the inverted sampling clock signal to output the second delayed signal.

Abstract: A serial interface circuit for a single logic input pin of an electronic system, comprising a decoder for converting a pulse width modulated input signal applied to the pin to a sequence of logic low and logic high values. The decoder comprises an up/down counter with a count input connected to a clock source, an edge detection circuit detecting rising and falling edges of the input signal. The edge detection circuit is connected to the up/down counter to start up counting from a reset value upon detection of an edge in a first direction and to start down counting from a current count upon detection of an edge in a second direction. The decoder further comprises a bit value deciding circuit that delivers a first logic value when the count of the up/down counter is above the reset value on detection of an edge in the second direction and delivers a second logic value when the count of the up/down counter is at or below the reset value on detection of an edge in the second direction.

Abstract: Aspects of a method and system for wide range amplitude detection are provided. In this regard, many electronic systems may require amplitude detection of a variety of signals with widely varying amplitudes. Aspects of the invention may comprise suitable logic, circuitry, and/or code to perform amplitude detection and may be easily configured to accommodate a wide range of amplitudes. In this regard, the configuration of the amplitude detector may be performed via simple design changes and/or may be dynamically configured by suitable logic, circuitry, and/or code. Accordingly, multiplexing a single instance of the wide range amplitude detector and/or multiplexing multiple instances of the wide range amplitude detector may result in reduced design time, reduced circuit size, and/or reduced cost.

Abstract: A data amplifying circuit for a semiconductor integrated circuit including a controller configured to generate a control signal for adjusting an amplification step in response to a test signal, and a data amplifier configured to amplify an input signal one time or two or more times in response to the control signal and to output an output signal.

Abstract: A comparator has: an offset setting portion adapted to set an offset voltage; an offset subtracting portion adapted to subtract the offset voltage from a non-inverting input voltage; and a comparing portion adapted to shift the output logic level thereof according to which of the output voltage of the offset subtracting portion and an inverting input voltage is higher.

Abstract: Techniques pertaining to a comparator circuit with reduced power consumption are disclosed. According to one aspect of the present invention, the comparator unit has a pair of input signal pins VIP and VIN, a pair of output signal pins VOR and VOS, and a clock signal pin CLK. In operation, when the CLK signal is at an idle voltage level, the comparator unit comes into an idle state. At the idle state, the comparator unit does not compare the two input signals VIP and VIN so that the output signals are identical. When the CLK signal is at a busy voltage level, the comparator comes into a busy state. At the busy state, the comparator compares the input signals VIP and VIN, and determines the values of the output signals VOR and VOS depending on the comparing result, e.g., if the input signal VIP is larger than the input signal VIN, the output signal VOR is high and the output signal VOS is low; otherwise, the output signal VOR is low and the output signal VOS is high.

Abstract: An apparatus for generating a DBI signal in a semiconductor integrated circuit includes a full adder that includes data input terminals and a carry input terminal, each of which receives data, performs an operation on the received data, thereby outputting a sum and a carry. A half adder includes data input terminals, each of which receives data, performs an operation on the received data, thereby outputting a sum and a carry. A DBI determining unit determines a logic value of each of the data according to the sums and the carries that are transmitted from the full adder and the half adder, thereby outputting a DBI signal.

Abstract: Aspects of a method and system for an integrated LC resonant current gain boosting amplifier may include amplifying within a chip, via an on-chip LC current gain circuit, an alternating current (AC) generated by an on-chip voltage-to-current converter, and converting within the chip, via an on-chip current-to-voltage circuit; the amplified alternating current to an output voltage. The on-chip LC current gain circuit comprises only passive components, which may include one or more resistors, one or more capacitors, and one or more inductors.

Abstract: Provided is a differential signal driver capable of operating at a high speed at a low voltage of 1.8V. The differential signal driver includes: a differential-signal driving circuit for switching input differential signals and outputting a common mode voltage through first and second output nodes; and a common-mode feedback circuit for providing a predetermined current to the differential-signal driving circuit or receiving a predetermined current from the differential-signal driving circuit in response to the common mode voltage. The differential-signal driving circuit includes a common-mode voltage output circuit for connecting the first output node to the second output node and generating the common mode voltage of the differential-signal driving circuit. The differential input signals are received through two bipolar transistors.

Abstract: A semiconductor integrated circuit is disclosed, which includes a current output buffer circuit including a differential circuit, a variable impedance circuit, and a constant current source, wherein the current output buffer circuit is driven by a constant current supplied by the constant current source, an output impedance of the current output buffer circuit is controlled in accordance with a bit rate of differential transmission signal inputs inputted to the differential circuit so that a waveform of a signal output from the current output buffer circuit to a signal transmission line is controlled in accordance with the bit rate of the transmission signal inputs.

Abstract: A semiconductor integrated circuit includes: a switching control circuit having a first transistor and a second transistor coupled to an FET, and turning on and off the FET by turning on and off each of the first transistor and the second transistor, the FET attaining an OFF state when the first transistor is in an ON state and the second transistor is in an OFF state; a bias circuit supplying the FET with a bias voltage for turning off the FET when the first transistor and the second transistor are in an OFF state; and a protection control circuit turning off the FET by turning on the first transistor and turning off the second transistor when an abnormality is detected, and turning off the first transistor and the second transistor after a lapse of a predetermined time.

Abstract: A buffer chain driver has two similar signal paths formed by series-connected buffer cells, each comprising two series connected inverter stages in each signal path. The output of the first inverter stage in each signal path is coupled to the output of the last inverter stage in the other signal path. Cross-coupling between the two signal paths results in an interpolation in the sense that each signal path has a 50% contribution to each of the complementary output signals, thereby compensating for any mismatch between the signal paths.

Abstract: Aspects of a method and system for signal processing are disclosed and may include using a frequency doubler to double the frequency of a reference signal utilized by a phase-frequency detector (PFD) in a fractional-N phase-locked-loop (PLL) synthesizer. Detecting and correcting a digital reference signal connected to the input of the frequency doubler. The digital reference signal may be generated by amplifying the difference between a low slew-rate reference signal and a reference voltage through a comparator. The reference voltage signal may be generated based on the detected duty-cycle of the digital reference signal. The duty-cycle of the digital reference signal may be adjusted by varying the generated reference voltage signal. The reference voltage may be generated by using difference of DC level of the digital reference signal and half rail. The reference voltage signal may be generated using a voltage digital-to-analog converter (DAC).

Abstract: One object of the present invention is to provide an LSI that can dynamically perform appropriate adjustment for a power voltage to be supplied to an internal circuit, not only at the time of the occurrence of the initial change of a performance due to a variation or variety factors through a manufacturing process, but also at the time of the occurrence of the time elapsed change.

Abstract: Circuits and methods for aligning two or more signals including a first and second signal. In one embodiment, a shift register generates two or more shifted copies of the second signal, and each of a plurality of phase detectors receives the first signal and one of the shifted copies of the second signal, each phase detector providing an output indicating whether the first signal is substantially aligned with the shifted copy of the second signal. A multiplexer may also be provided for receiving each of the shifted copies of the second signal, the multiplexer having a plurality of select lines coupled with the output signals of the phase detectors. Some embodiments may include a power saving mode.

Abstract: Generating an output signal having a frequency of 1/(M+F) of the frequency of the input signal, wherein M represents an integer and F represents a non-zero fraction. Assuming F equals (Q/R) in one embodiment, wherein Q and R are integers, R intermediate signals phase shifted by equal degree (relative to the one with closest phase shift) in one clock period of the input signal are generated. A selection circuit may select one of the intermediate signals in one clock cycle, select the successive signals with increasing phase shift in Q clock cycles, and leave the intermediate signal with the same shift as in the previous clock cycle in the remaining ones of the M clock cycles. A counter counts a change of state in the output of the selection circuit, and generates a pulse representing an edge of the output signal at the time instance when counter counts M.

Abstract: A power supply circuit includes a first voltage regulator to generate a first supply voltage for a first circuit of a phase-locked loop and a second voltage regulator to generate a second supply voltage for a second circuit of the phase-locked loop. The first and second supply voltages are independently generated by the first and second voltage regulators based on the same reference signal. The first circuit may be a charge pump and the second circuit may be a voltage-controlled oscillator. Different circuits may be supplied with the independently generated supply voltages in alternative embodiments.

Abstract: A filter circuit arrangement for filtering of a radio-frequency signal has a first tunable filter and a phase regulation loop in order to hold the first tunable filter to a transmission phase constant relative to the frequency of the radio-frequency signal. The filter circuit arrangement has a second tunable filter arranged parallel to the first tunable filter in the phase regulation loop. The first tunable filter and the second tunable filter exhibit different attenuation characteristics and are fashioned and connected within the phase regulation loop so that: a capture range of the filter circuit arrangement, in which a tuning of the phase regulation loop to a radio-frequency signal to be filtered is possible is dominated by the attenuation characteristic of the second tunable filter, and so that the transmission behavior of the filter circuit arrangement in operation is dominated by the attenuation characteristic of the first tunable filter, given a tuned phase regulation loop.

Abstract: A phase locked loop (PLL) circuit including a phase comparator for comparing a phase of a reference signal with a phase of a feedback signal, an oscillator for outputting an output signal at a frequency in accordance with an output of the phase comparator, a feedback loop for returning the output signal of the oscillator and supplying the output signal as the feedback signal, and a delay circuit for delaying the phase of the output signal output from the oscillator to a load circuit, wherein the delay circuit is provided outside the feedback loop.

Abstract: Disclosed herein is a VDL/DLL architecture in which the power supply to the VDL, VccVDL, is regulated at least as a function of the entry point of the input signal (ClkIn) into the VDL. Specifically, VccVDL is regulated to be higher when the delay through the VDL is relatively small (when the entry point is toward the right (or minimum delay) edge of the VDL) and is reduced when the delay is relatively high (when the entry point is toward the left (or maximum delay) edge of the VDL). This provides for graduated delays across the stages of the VDL, but without the need to design each stage separately. Other benefits include a VDL/DLL design operable over a wider range of frequencies, and a reduced number of stages, including a reduced number of buffer stages. Moreover, when the disclosed technique is used, buffer stages may be dispensed with altogether.

Abstract: A semiconductor memory device includes a delay locked loop for achieving a delay locked state by correcting a phase difference between a reference clock and an internal delayed clock and for indicating the state that a larger delay amount than a maximum delay amount of a delay line is required, or a smaller delay amount than a minimum delay amount of delay line is required. A control unit resets the delay locked loop according to the state of the delay line.

Abstract: A delay apparatus for a delay locked loop includes a plurality of delay devices that are formed by modeling a plurality of signal processing structures through which a delay locked loop clock output from a delay locked loop reaches an output circuit of a semiconductor memory apparatus from an output terminal of the delay locked loop. At least one of the plurality of delay devices is composed of a variable delay device in which a delay time varies according to a change in operation voltage.

Abstract: A frequency multiplier increases the frequency of an external clock and outputs a high-frequency external clock. A period determinator determines whether or not a predetermined period of the external clock elapses and outputs a period determination signal. A frequency selector selectively transmits the external clock or the high-frequency external clock to a clock input buffer under the control of a power-up signal and the period determination signal.

Abstract: A semiconductor memory device includes a first clock buffer for outputting a first internal clock signal in response to an inverted signal of the system clock signal and for correcting a duty cycle ratio of the first internal clock signal in response to a control signal; a second clock buffer for outputting a second internal clock signal in response to the system clock signal and for correcting a duty cycle ratio of the second internal clock signal in response to the control signal; an analog duty cycle correction circuit for outputting the control signal corresponding to the duty cycle ratio of the first and second internal clock signals; a mixing circuit for mixing the first and second internal clock signals and for outputting a third internal clock signal whose duty cycle is corrected; and a DLL circuit for outputting a delay-locked clock signal by using the third internal clock signal.

Abstract: An apparatus for extracting a maximum pulse width of a pulse width limiter is provided. The apparatus performs such extraction using a circuit that is configured to eliminate a majority of delay cells. The elimination of delay cells is made possible by replacing an OR gate in the circuit configuration with an edge triggered re-settable latch. The replacement of the OR gate with the edge triggered re-settable latch reduces the amount of chip area used in addition to the power consumption of the circuit.

Abstract: An edge triggered flip-flop circuit is disclosed with a clock signal, an input signal, a switch module using the clock signal for defining a data passing window, and a latch module for receiving the input signal during the data passing window.

Abstract: A latch includes: an amplifying circuit, for receiving a first bias current in a first state for amplifying an input signal to generate an amplified signal; a latching unit, for latching the amplified signal and receiving a second bias current in a second state to output the amplified signal; and a biasing circuit, for providing a biasing current to the amplifying circuit, and providing the second biasing current to the latching unit. The biasing circuit includes: a first biasing module for providing a third biasing circuit to the amplifying circuit in the first state; and a second biasing module, for providing a fourth biasing current to the amplified circuit; wherein the first biasing circuit is equal to a sum of the third biasing current and the fourth biasing current.

Abstract: A latch circuit (1) comprising, a differential input with an inverting input (D+) and a non-inverting input (D?). The latch further comprises a differential output with an inverting output (Q+) and a non-inverting output (Q?). One of the outputs (Q?) is coupled to one of the inputs input (D+) having an opposite polarity. The latch further comprises a control input for receiving a control signal (VCM) for determining a threshold for an input signal (In) such that if the input signal is at larger than the threshold the non-inverting output in a HIGH logic state and in a LOW state if the input signal is smaller than the threshold, respectively.

Abstract: A sense amplifier control signal generating circuit of a semiconductor memory apparatus is provided. The sense amplifier control signal generating circuit includes a timing control unit that models a transmission path of data from a memory cell to a sense amplifier through a bit line and generates a timing control signal at a sensing timing when the sense amplifier starts a sensing operation. A sense amplifier control signal generating unit receives the timing control signal and generates a sense amplifier control signal.

Abstract: A delay circuit includes a first delay line circuit having a plurality of stages of delay units, a second delay line circuit having a plurality of stages of delay units, a plurality of transfer circuits provided in association with respective stages of the delay units of the first delay line circuit, the transfer circuits controlling the transfer of the outputs of the delay units of the first delay line circuit to associated stages of the delay units of the second delay line circuit. The delay units of respective stages of the first delay line circuit inverting input signals. Each stage delay unit of the second delay line circuit includes a logic circuit receiving an output signal of the transfer circuit associated with the delay unit in question and an output signal of a preceding stage to send an output signal to a following stage. The duty ratio is rendered variable by independently selecting the rising edge of the input signal and a propagation path of the falling edge.

Abstract: A circuit for generating a clock of a semiconductor memory apparatus. A reference voltage generator is configured to generate a reference voltage. A reference current generator is configured to generate a reference current that has a constant current value regardless of a change in temperature. An oscillator is configured to receive the reference voltage and the reference current to generate a clock that has constant frequency.

Abstract: A level shifter including a first boost circuit, an inverter, a second boost circuit and a level shift circuit is disclosed. The first boost circuit receives an input signal, and a first amplification factor for the input signal is determined based on a control signal. The inverter receives the input signal to generate an inverted input signal. The second boost circuit is coupled to an output terminal of the inverter to receive the inverted input signal, and a second amplification factor for the inverted input signal is determined based on the control signal. The level shift circuit has a first input terminal and a second input terminal respectively coupled to output terminals of the first boost circuit and second boost circuit to change the voltage level of output signals from the first boost circuit and second boost circuit to a first voltage level.

Abstract: A drive circuit in power electronic systems comprising a half-bridge circuit of two power switches, a first so-called TOP switch and a second so-called BOT switch, which are arranged in a series circuit. The drive circuit has a BOT level shifter for transmitting an input signal from a drive logic to a BOT driver. The BOT level shifter is formed as an arrangement of an UP and a DOWN level shifter branch and a signal evaluation circuit connected downstream thereof. In the inventive method for transmitting the input signal, the signal evaluation circuit transfers an output signal to the BOT driver at least one of the UP and DOWN level shifter branches outputs a signal to the respectively assigned input of the signal evaluation circuit.

Abstract: In a level shifter, OFF leakage currents flow through two N-type transistors for signal input even when they are OFF. However, another N-type transistor serving as an OFF leakage generation circuit and three P-type transistors serving as current mirrors, which constitute a current conversion circuit, supply to the signal-input transistors a current equivalent to or greater than the OFF leakage currents flowing through the signal-input transistors when they are OFF, thereby canceling the OFF leakage currents. Therefore, one of nodes which is at H level is surely fixed to a potential equal to a higher voltage supply. Thus, the level shifter surely operates with a high speed even when large OFF leakage currents flow through the signal-input transistors.

Abstract: A voltage integrator, comprising a resistor (4) and a capacitor (5) connected in series between an input voltage (V) and ground, wherein the resistance (R) of said resistor and the capacitance (C) of said capacitor are adapted such that a voltage (Vc) across said capacitor approximates the integral of said input voltage (V). Means are provided for preventing said capacitor voltage (Vc) from falling below a lower limit, preferably zero, thereby ensuring automatic initialization of the integrator after each integration cycle.

Abstract: A square cell comprises first and second bipolar transistors each having an emitter, collector and base, the bases of the transistors being connected for receiving an input voltage, and first and second resistors in series with the first and second bipolar transistors respectively and with a source of reference voltage. The collectors are commonly connected to an output node to supply an output current having a component proportional to the square of the input voltage. Enhanced square law conformance may be produced by adding further pairs of bipolar transistors to the cell, with offset voltage elements coupled between bases of successive transistors on each side of the cell.

Abstract: The leakage compensation circuit includes: a replica circuit of a circuit to be compensated, the replica circuit provides a replica leakage current equal to a leakage current of the circuit to be compensated; an amplifier having a first input coupled to the replica circuit and a second input coupled to a node to be compensated; a first resistance coupled between an output of the amplifier and the replica circuit; a second resistance coupled between the output of the amplifier and the node to be compensated; and wherein the replica leakage current is subtracted from the node to be compensated.

Abstract: In an electronic device according to the present invention, a source of the first signal-wire drive transistor is connected to a first power supply, a drain of the first signal-wire drive transistor is connected to a signal wire, and a control circuit controls a gate voltage so that a current flowing in the signal wire is amplified toward a voltage to which a potential of the signal wire transits during the potential transition in the signal wire and further controls the gate voltage so that a voltage value obtained after the potential transition in the signal wire is retained after the potential transition in the signal wire.

Abstract: A switching circuit includes switching transistors connected to one of an input terminal and an output terminal of the switching circuit, and a control bias supply circuit that supplies a control bias for cutting off all the switching transistors to the switching transistors when all of the switching transistors are in a non-selected state.

Abstract: A circuit is disclosed, including a transistor switch having a first terminal to receive an input voltage, a second terminal to output an output voltage and a gate terminal; a determination circuit, coupled to the first terminal and the second terminal of the transistor switch, to determine a lower or higher voltage between the input voltage and the output voltage; a voltage generator, coupled to the determination circuit, to generate a sum voltage or difference voltage using the lower or higher voltage; and a control circuit, coupled to the voltage generator and the gate terminal of the transistor switch, to apply the sum voltage or difference voltage to the gate terminal of the transistor switch during a first time interval.

Abstract: An embodiment of the present invention is a technique to program a fuse. A program circuit generates first and second currents to program the fuse. The second current is higher than the first current. A control circuit controls generating the first and second currents in succession.

Abstract: The present invention provides a tunable voltage controller for use with a sub-circuit. In one embodiment, the tunable voltage controller includes a diode-connected MOS transistor contained in a doped well of a substrate and configured to provide a voltage for the sub-circuit. Additionally, the tunable voltage controller also includes a biasing unit configured to adjust the voltage by selectively connecting the doped well to one of a plurality of voltage sources or to a variable voltage source.

Abstract: A method and system for buffering a clock signal is provided. The method may include self-biasing a PMOS transistor of a buffer, utilized for amplifying an in-phase/quadrature phase signal, to produce a first bias voltage at the gate of a PMOS transistor, and biasing an NMOS transistor of the buffer via a controllable current source to produce a second bias voltage at the gate of the NMOS transistor. The gain of the buffer may be controlled by varying a controllable current source coupled to a second NMOS transistor configured as a diode. Two coupling capacitors may be utilized to remove a DC component of the signal. Multiple buffers may be coupled end-to-end to increase the overall drive capability, where the channel width of the transistors within the transistors may be doubled in each successive buffer.

Abstract: An integrated circuit device having a body bias voltage mechanism. The integrated circuit comprises a resistive structure disposed therein for selectively coupling either an external body bias voltage or a power supply voltage to biasing wells. A first pad for coupling with a first externally disposed pin can optionally be provided. The first pad is for receiving an externally applied body bias voltage. Circuitry for producing a body bias voltage can be coupled to the first pad for coupling a body bias voltage to a plurality of biasing wells disposed on the integrated circuit device. If an externally applied body bias voltage is not provided, the resistive structure automatically couples a power supply voltage to the biasing wells. The power supply voltage may be obtained internally to the integrated circuit.

Abstract: A charge pump circuit for generating a plurality of voltages in excess of a supply voltage includes a first group of cascaded charge-pump stages, the input of a first charge pump stage in the first group being driven from the supply voltage. A first output stage has an input driven from the output of a last charge pump stage of the first group and an output coupled to a first voltage node. A second group of cascaded charge-pump stages is provided, the input of the first charge pump stage of the second group being driven from the output of the last charge pump stage of the first group. A second output stage has an input driven from the output of the last charge pump stage in the second group and an output coupled to a second voltage node.

Abstract: A voltage generating circuit includes: a pumping circuit configured to boost a power supply voltage in accordance with a charge transfer operation; a voltage detection circuit configured to detect the output voltage of the pumping circuit; a first pumping control circuit configured to control the pumping circuit in accordance with the output of the voltage detection circuit; and a second pumping control circuit configured to control the pumping circuit in place of the first pumping control circuit when the output voltage of the pumping circuit is in a certain range.