Abstract: A method for integrating an electronic component or the like into a substrate includes following process steps: formation of a dielectric insulating layer on the front side of a substrate; complete back-etching of an area of the substrate from the back of the substrate to form a cavity; formation of a photoresistive layer with a homogeneous thickness over the back of the substrate; placement of an electronic component on the photoresistive layer formed in the cavity for adhesion of the electronic component to the photoresistive layer; removal of the formed photoresistive layer except for the area on which the electronic component adheres to the photoresistive layer in the cavity; and formation of a fixing layer over the back of the substrate to fix the electronic component in the cavity of the substrate.

Abstract: A method of producing a device with a movable portion spaced apart from a support wafer comprises a step of providing the support wafer having a structured surface and a further step of providing a device wafer with a backing layer and a device layer disposed thereon. Further, the method comprises the step of generating a first planarization layer from a first starting material on the support wafer with a first method to fill in the structures of the structured surface of the support wafer, whereby a surface with a first degree of planarization is obtained. Further, the method comprises a step of generating a second planarization layer from a second starting material on the planarized surface of the support wafer with a second method to obtain a surface with a second degree of planarization, which is higher than the first degree of planarization, wherein the first and second planarization layers can be removed together.

Abstract: A process for joining substrates having electrical, semiconducting, mechanical and/or optical components, and to a composite element is provided. The process is to be suitable for substrates that are to be joined substantially irrespective of material and for sensitive substrates. According to the process, a raised frame, in particular formed from anodically bondable glass, is applied by evaporation coating to one of the two substrates in order to serve as a joining element.

Abstract: A laser beam machining method and a laser beam machining device capable of cutting a work without producing a fusing and a cracking out of a predetermined cutting line on the surface of the work, wherein a pulse laser beam is radiated on the predetermined cut line on the surface of the work under the conditions causing a multiple photon absorption and with a condensed point aligned to the inside of the work, and a modified area is formed inside the work along the predetermined determined cut line by moving the condensed point along the predetermined cut line, whereby the work can be cut with a rather small force by cracking the work along the predetermined cut line starting from the modified area and, because the pulse laser beam radiated is not almost absorbed onto the surface of the work, the surface is not fused even if the modified area is formed.

Abstract: A method of preparing a clean substrate surface for blanket or selective epitaxial deposition of silicon-containing and/or germanium-containing films. In addition, a method of growing the silicon-containing and/or germanium-containing films, where both the substrate cleaning method and the film growth method are carried out at a temperature below 750° C., and typically at a temperature from about 700° C. to about 500° C. The cleaning method and the film growth method employ the use of radiation having a wavelength ranging from about 310 nm to about 120 nm in the processing volume in which the silicon-containing film is grown. Use of this radiation in combination with particular partial pressure ranges for the reactive cleaning or film-forming component species enable the substrate cleaning and epitaxial film growth at temperatures below those previously known in the industry.

Abstract: A method of fabricating a semiconductor thin film is provided, comprising: forming an insulation layer on a semiconductor substrate; etching the insulation layer to form a plurality of openings exposing the substrate at the bottom of the openings; filling the openings with a semiconductor seed layer; forming an amorphous layer on the seed layer and the insulation layer; transforming the amorphous layer to a polycrystalline layer by exposing the amorphous layer to a first laser irradiation at a first energy level; and forming a single semiconductor crystalline film by annealing the polycrystalline layer and the semiconductor seed layer with a second laser irradiation at a second energy level.

Abstract: Method of forming one or more doped regions in a semiconductor substrate and semiconductor junctions formed thereby, using gas cluster ion beams.

Abstract: A method for plasma ion implantation of a substrate includes providing a plasma ion implantation system having a process chamber, a source for producing a plasma in the process chamber, a platen for holding a substrate in the process chamber, an anode spaced from the platen, and a pulse source for generating implant pulses for accelerating ions from the plasma into the substrate. In one aspect, a parameter of an implant process is varied to at least partially compensate for undesired effects of interaction between ions being implanted and the substrate. For example, dose rate, ion energy, or both may be varied during the implant process. In another aspect, a pretreatment step includes accelerating ions from the plasma to the anode to cause emission of secondary electrons from the anode, and accelerating the secondary electrons from the anode to a substrate for pretreatment of the substrate.

Abstract: The present invention provides semiconductor structures and a method of fabricating such structures for application of MOSFET devices. The semiconductor structures are fabricated in such a way so that the layer structure in the regions of the wafer where n-MOSFETs are fabricated is different from the layer structure in regions of the wafers where p-MOSFETs are fabricated. The structures are fabricated by first forming a damaged region with a surface of a Si-containing substrate by ion implanting of a light atom such as He. A strained SiGe alloy is then formed on the Si-containing substrate containing the damaged region. An annealing step is then employed to cause substantial relaxation of the strained SiGe alloy via a defect initiated strain relaxation. Next, a strained semiconductor cap such as strained Si is formed on the relaxed SiGe alloy.

Abstract: A semiconductor device comprising a semiconductor substrate and a MOSFET provided on the semiconductor substrate, the MOSFET including a gate insulating film and a gate electrode provided on the gate insulating film, wherein the gate insulating film has a higher dielectric constant in a side contacting the semiconductor substrate than in a side contacting the gate electrode.

Abstract: The invention relates to a method for contacting parts of a component integrated into a semiconductor substrate (1). According to the inventive method, a first contact hole is produced in an insulating layer (2), said contact hole being then filled with contact material (16) and connected to a line. The aim of the invention is to minimise the processes required for contacting parts of a component integrated into a semiconductor substrate. To this end, the hard mask (3) used to produce the contact hole is also used to structure the line.

Abstract: A method and a structure are provided for improving the contact of two adjacent GMR memory bits. Two adjacent bit ends are connected by utilizing a single via.

Abstract: A method for manufacturing a semiconductor device includes forming a second storage node contact hole with a mask for storage node and securing an overlay margin between a storage node contact hole and a storage node with a hard mask layer that serves as a hard mask as well as an anti-reflection film to reduce contact resistance, prevent reduction of a line-width of a lower interlayer insulating film and eliminate processes for depositing the interlayer insulating film and a polysilicon layer and etching the polysilicon layer to reduce a production period and cost of products.

Abstract: An electronic device is disclosed with solder bumps treated to improve coplanarity and reduce the effects of poor solder bump surface quality, and a method of constructing same. An electronic device is placed against a flat plate and a controlled amount of force is applied to press together the electronic device and flat plate. The taller solder bumps are compressed, reducing non-coplanarity of the solder bumps. The controlled amount of force exposes the bulk material of a solder bump coated with a foreign material. A layer of abrasive, electroconductive particles that is harder than the foreign material, dispersed on the surface of the flat plate and firmly held in place, may also puncture the foreign material and expose the solder bump bulk material when the controlled amount of force is applied.

Abstract: A semiconductor package substrate is provided having a plurality of bonding pads on at least one surface thereof and covered by a conductive film. A photoresist layer formed over the conductive film has a plurality of first openings for exposing portions of the conductive film corresponding to the bonding pads. The exposed portions of the conductive film is removed to expose the bonding pads respectively via the first openings. The exposed bonding pads are plated with a metal layer respectively. Then, the photoresist layer and the remainder of the conductive film covered by the photoresist layer are removed. A solder mask having a plurality of second openings may be formed on the surface of the substrate, and allows the plated metal layer on the bonding pads respectively to be exposed via the second openings.

Abstract: A manufacturing technique that involves embedding one or more semiconductor die into a support substrate and forming conductive traces that lead from die contact pads to redistributed contact pads on the support substrate. Active surfaces of the dice and a working surface of the support substrate are substantially coplanar and the conductive traces are formed on the coplanar surfaces. The redistributed contact pads are sufficiently spaced apart from each other so that conductive balls can be formed thereon. Individual semiconductor device packages are singulated from the support substrate.

Abstract: The present invention provides a method of forming a metal seed layer 100. The method includes physical vapor deposition of seed metal 200 within an opening 140 located in a dielectric layer 135 of a substrate 110. The method also includes a RF plasma etch of the seed metal 200 deposited in the opening 140 simultaneously with conducting the physical vapor deposition of the seed metal 200.

Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Abstract: An interconnect structure with improved performance and capacitance by providing air gaps inside the dielectric layer by use of a multi-phase photoresist material. The interconnect features are embedded in a dielectric layer having a columnar air gap structure in a portion of the dielectric layer surrounding the interconnect features. The interconnect features may also be embedded in a dielectric layer having two or more phases with a different dielectric constant created. The interconnect structure is compatible with current back end of line processing.

Abstract: Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition SivNwCxOyHz, where 0.05?v?0.8, 0?w?0.9, 0.05?x?0.8, 0?y?0.3, 0.05?z?0.08 for v+w+x+y+z=1; a via level interlayer dielectric that is directly below said buried etch stop layer; a line level interlayer dielectric that is directly above said buried etch stop layer; and conducting metal features that traverse through said via level dielectric, said line level dielectric, and said buried etch stop layer.

Abstract: Methods of protecting exposed metal damascene interconnect surfaces in a process for making electronic components and the electronic components made according to such methods. An integrated circuit structure having damascene regions with exposed metal surfaces is provided into a closed processing chamber, whereby a first reactant is contacted to the exposed metal surfaces to transform a top portion of the metal layer into a protective self-aligned buffer layer. Reacting molecules of the first reactant with metal atoms of this metal layer forms the protective self-aligned buffer layer entirely within such metal layer. Alternatively, adsorbing surface-active reactant molecules onto the exposed metal surface forms the protective self-aligned buffer layer. A second reactant may be contacted to the protective self-aligned buffer layer to form a self-aligned dielectric cap layer directly over the protective self-aligned buffer layer.

Abstract: The present invention is directed to a method and system of intelligent dummy filling placement to reduce inter-layer capacitance caused by overlaps of dummy filling area on successive layers. The method and system treats each consecutive pair of layers together so as to minimize dummy filling overlaps between each layer. In particular, dummy fill features on each layer may be placed in a checkerboard pattern to avoid overlaps. As such, the present invention may eliminate large overlap area of the dummy patterns on consecutive layers by utilizing intelligent dummy filling placement.

Abstract: In a semiconductor device and a method of manufacturing the semiconductor device, a plug and a channel structure are formed. The plug fills an opening and the channel structure extends upwardly from the plug. The channel structure has a substantially vertical sidewall. The opening is formed through an insulation structure located on a substrate. The plug and the channel structure comprise a material in a single crystalline state that is changed from an amorphous state by an irradiation of a laser beam. The channel structure is doped with impurities such as boron, phosphorus or arsenic.

Abstract: Interconnect structures that include a conformal liner repair layer bridging breaches in a liner formed on roughened dielectric material in an insulating layer and methods of forming such interconnect structures. The conformal liner repair layer is formed of a conductive material, such as a cobalt-containing material. The conformal liner repair layer may be particularly useful for repairing discontinuities in a conductive liner disposed on roughened dielectric material bordering the trenches and vias of damascene interconnect structures.

Abstract: A semiconductor package and a method of manufacturing the same: The package includes a substrate, an external connection terminal portion on at least one edge thereof; a semiconductor chip bonded to the substrate, the semiconductor chip including a plurality of bonding pads; and a flexible film, which electrically connects the semiconductor chip to the external connection terminal portion.

Abstract: The technology which can improve the performance of a MOS transistor in which all the regions of the gate electrode were silicided is offered. A gate insulating film and a gate electrode of an nMOS transistor are laminated and formed in this order on a semiconductor substrate. A source/drain region of the nMOS transistor is formed in the upper surface of the semiconductor substrate. The source/drain region is silicided after siliciding all the regions of the gate electrode. Thus, silicide does not cohere in the source/drain region by the heat treatment at the silicidation of the gate electrode by siliciding the source/drain region after the silicidation of the gate electrode. Therefore, the electric resistance of the source/drain region is reduced and junction leak can be reduced. As a result, the performance of the nMOS transistor improves.

Abstract: A method of fabricating a liquid crystal display device according to an embodiment of the present invention includes forming first and second conductive layers on a substrate, wherein the first layer is transparent; patterning the second conductive layer and the first conductive layer using the photo-resist pattern as a mask; etching at least one lateral part of the patterned second conductive layer using the photo-resist pattern as a mask; and removing the remaining photo-resist pattern.

Abstract: A low-temperature chemical vapor deposition process for depositing of a low-resistivity ruthenium metal layers that can be used as barrier/seed layers in Cu metallization schemes. The method includes providing a substrate in a process chamber of a deposition system, forming a process gas containing a ruthenium carbonyl precursor vapor and a CO-containing gas, and exposing the substrate to the process gas to deposit a low-resistivity ruthenium metal layer on the substrate by a thermal chemical vapor deposition process, where the substrate is maintained at a temperature between about 100° C. and about 300° C. during the exposing. A semiconductor device containing the ruthenium metal layer formed on a patterned substrate containing one or more vias or trenches, or combinations thereof, is provided.

Abstract: A method of forming a silicided gate on a substrate having active regions, comprising the steps of: forming a first silicide in the active regions from a first material; and forming a second silicide in the gate from a second material, wherein the first silicide forms a barrier against the second material forming a silicide in the active regions during the second silicide forming step, wherein said second silicide is thicker than said first silicide.

Abstract: In one method and embodiment of the present invention, at least one coil layer is formed in a write head, using a two-slurry step of copper damascene chemical mechanical polishing method with a first slurry step removing the undesirable copper that is on top of the tantalum barrier layer and on top of the trenches and a second slurry step removing the remainder of the undesirable copper, the tantalum barrier layer, the silicon dioxide hard mask layer, the hard baked photoresist layer, the magnetic alloy such as NiFe, CoFe, or CoNiFe, and alumina insulating layer for better thin film magnetic head performances.

Abstract: A method of forming a feature in a low-k (k<3.0) dielectric layer is provided. A low-k dielectric layer is placed over a substrate. A patterned photoresist mask is placed over the low-k dielectric layer. At least one feature is etched into the low-k dielectric layer. A stripping gas comprising CO2 is provided. A plasma is formed from the stripping gas comprising CO2. The plasma from the stripping gas comprising CO2 is used to strip the patterned photoresist mask.

Abstract: To smooth silicon sliders that have been parted from each other on a wafer by DRIE, an isotropic etch using fluorine either in a gas or in an aqueous solution is performed prior to separating the individual sliders from the wafer.

Abstract: A plasma etching apparatus includes a processing chamber in which a specimen is subjected to plasma processing, a specimen holder for holding the specimen, the specimen holder including a temperature controller for controlling temperatures at at least 2 positions of the specimen, at least two gas supply sources for supplying processing gases, at least two gas inlets for introducing the processing gases into the processing chamber, a regulator for independently controlling the compositions or the flow rates of the processing gases introduced from the at least two gas inlets and the temperatures controlled with at least two temperature controllers in the specimen holder, and an electromagnetic wave supply unit for sending an electromagnetic wave into the processing chamber, wherein the compositions or the flow rates of the processing gases introduced from the gas inlets and the temperature controlled with the temperature controllers in the specimen holder are independently controlled.

Abstract: A method for fabricating a semiconductor device includes: providing a substrate structure including a bit line and a capacitor formed apart from each other at a different level; forming first, second, and third insulation layers over the bit line, the second insulation layer being a first etch stop layer; forming a second etch stop layer over a top electrode of the capacitor; forming a fourth insulation layer over the third insulation layer and the second etch stop layer; and performing a plurality of etch steps to expose an upper surface of the bit line and an upper surface of the capacitor.

Abstract: A method of making a semiconductor structure, comprises cleaning a gate stack with a cleaning solution. The gate stack comprises a gate layer, a metallic layer on the gate layer, and a etch-stop layer on the metallic layer. The gate layer is on a semiconductor substrate, the cleaning solution is a non-oxidizing cleaning solution, and the metallic layer comprises an easily oxidized metal.

Abstract: Methods of forming a metal oxide surface that is enriched with metal oxide in its higher oxidation state are provided. A metal oxide surface that is enriched with metal oxide in its higher oxidation state is also provided.

Abstract: The present invention discloses improved method for manufacturing semiconductor device wherein the gate oxide films in the cell region, VPP peripheral circuit region and VDD peripheral circuit region are formed to have different thicknesses from one another so that the threshold voltage of the cell transistor may be increased to a desired value as well as increasing the operation speed of the transistor and suppress the short channel effect.

Abstract: A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer.

Abstract: Methods of fabricating high-k dielectric layers having reduced impurities for use in semiconductor applications are disclosed. The methods include the steps of: forming a stacked dielectric layer having a first dielectric layer and a second dielectric layer formed on a semiconductor substrate using an ALD method, in combination with a post-treatment step performed to the stacked dielectric layer. The steps of forming the stacked dielectric layer and performing the post-treatment are repeated at least once, thereby fabricating the high-k dielectric layer.

Abstract: A Lewis acid-base reaction is caused, in a solution, between a first monomer corresponding to a Lewis acid and a second monomer corresponding to a Lewis base, so as to generate a monomer adduct in which the first monomer and the second monomer are bonded to each other through weak electric interaction. Next, the solution including the monomer adduct is applied on a substrate so as to form a supramolecular solid thin film made of the monomer adduct. Then, the supramolecular solid thin film is heated so as to cause a polymerization reaction between the first monomer and the second monomer within the supramolecular solid thin film, thereby forming a polymer thin film.

Abstract: An electronic apparatus includes an insulative substrate containing an aluminum-based glass and a layer containing a semiconductive material over the substrate. The insulative substrate can include aluminum oxycarbide. The insulative substrate can exhibit a CTE sufficiently close to a CTE of the semiconductive material layer such that a strain of less than 1% would exist between a 1000 Angstroms thickness of the semiconductive material layer and the insulative substrate. The semiconductive material layer can include monocrystalline silicon. The electronic apparatus can be a silicon-on-insulator integrated circuit. An electronic apparatus fabrication method includes forming an insulative substrate containing an aluminum-based glass and forming a layer containing a semiconductive material over the substrate.

Abstract: A method of carrying out the laser processing of a wafer with a laser beam processing machine comprising a chuck table for holding a wafer, a laser beam application means for applying a laser beam to the wafer held on the chuck table and a processing-feed means for processing-feeding the chuck table and the laser beam application means relative to each other, comprising the steps of a wafer affixing step for putting the wafer on the surface of a protective tape mounted on an annular frame, a wafer holding step for holding the wafer put on the protective tape on the chuck table, and a laser beam application step for applying a laser beam having a predetermined wavelength from the laser beam application means to the wafer held on the chuck table and processing-feeding the wafer with the processing-feed means, wherein the protective tape is made of a material which transmits the laser beam having a predetermined wavelength applied from the laser beam application means.

Abstract: Variations in the pitch of features formed using pitch multiplication are minimized by separately forming at least two sets of spacers. Mandrels are formed and the positions of their sidewalls are measured. A first set of spacers is formed on the sideswalls. The critical dimension of the spacers is selected based upon the sidewall positions, so that the spacers are centered at desired positions. The mandrels are removed and the spacers are used as mandrels for a subsequent spacer formation. A second material is then deposited on the first set of spacers, with the critical dimensions of the second set of spacers chosen so that these spacers are also centered at their desired positions. The first set of spacers is removed and the second set is used as a mask for etching a substrate. By selecting the critical dimensions of spacers based partly on the measured position of mandrels, the pitch of the spacers can be finely controlled.

Abstract: The present invention is generally directed to adhesive compositions comprising selected ratios of crystalline and amorphous polymers. In some versions of the invention, polymers capable of existing in different configurations (e.g., a polymer such as polypropylene which can exist in an atactic, syndiotactic. or isotactic configuration) are used to prepare adhesives of the present invention. As an example, a selected amount of isotactic polypropylene is blended with a selected amount of atactic polypropylene to prepare an adhesive composition having one or more performance properties (e.g., bond strength) that are superior to the performance properties of a conventional hot-melt adhesive. The adhesive compositions of the present invention are suitable for use in the preparation of laminated disposable absorbent products.

Abstract: A fibrous structure testable in a series of run-off tests, wherein each run-off test includes exposing the fibrous structure to a volume of a test solution and the fibrous structure initially is hydrophobic and has been treated to be hydrophilic, wherein the fibrous structure exhibits a run-off level that is less than 5 percent by weight throughout a series of run-off tests, and wherein the series starts with a first run-off test and ends with a fifth run-off test.

Abstract: This material is remarkable in that it is made by weaving or knitting, in such a manner as to form a structure comprising two superposed faces (1, 2) intermittently interconnected to each other so as to form pockets, and in which: one of the layers shrinks under the effect of heat; and the linking between the layers is implemented by intermittently linking selected yarns so as to form said pockets.

Abstract: A ceramic substrate composition is provided which can be co-fired with a low-melting metal and exhibits excellent dielectric characteristics at high frequencies, particularly tens of gigahertz. The ceramic substrate composition mainly contains a glass represented by aB2O3-bRe2O3-cZnO, wherein the molar ratios (a, b, and c) fall within a region defined in a ternary composition diagram by Point A (0.4, 0.595, 0.005), Point B (0.4, 0.25, 0.35), Point C (0.52, 0.01, 0.47), Point D (0.9, 0.005, 0.095), and Point E (0.9, 0.09, 0.01).

Abstract: A glass containing 5 to 25 mass % of P2O5, 0 to 15 mass % of B2O3, 0 to 5 mass % of SiO2+GeO2, 21 to 50 mass % of BaO+SrO, 0 to 3 mass % of Li2O+Na2O+K2O, and 35 to 65 mass % of Nb2O5, not substantially containing PbO, satisfying Nb2O5/(BaO+SrO)=0.85 to 2.20, having a dielectric constant of 15 or greater, a dielectric loss of 10.0×10?4 or less, and a resistivity of 1.0×1016 ?·cm or more.

Abstract: The lead-free, preferably lithium-free, optical glass is useful in imaging, projection, telecommunications, optical communication and/or laser technology, particularly for making precise-pressed optical elements. It has a refractive index nd of 1.50 to 1.57, an Abbé number ?d of 61 to 70. It also has a low transformation temperature of about or below 400° C., good production and processing properties and crystallization resistance. It has a composition, in percent by weight, based on oxide content of P2O5, 40 to 60; Al2O3, 1 to 20; B2O3, 0 to <5; Na2O, 0 to 30; K2O, 0 to 30; Li2O, 0 to <1; ?M2O, >15 to 40; BaO, 1 to 20; ZnO, 1 to 20; SrO, 0 to 5; CaO, 0 to 5; MgO, 0 to 5; and ?MO, 5 to 25. In addition, it may contain standard refining agents, although it is preferably free of arsenic and fluorine.

Abstract: A glass substrate for use as the substrate of an information recording medium such as a magnetic disk, magneto-optical disk, DVD, or MD or of an optical communication device, and a glass composition for making such a glass substrate, contains the following glass ingredients: 45 to 75% by weight of SiO2; 1 to 20% by weight of Al2O3; 0 to 15% by weight, zero inclusive, of B2O3; SiO2+Al2O3+B2O3 accounting for 65 to 90% by weight; a total of 7 to 20% by weight of R2O compounds, where R=Li, Na, and K; and a total of 0 to 12% by weight, zero inclusive, of R?O compounds, where R?=Mg, Ca, Sr, Ba, and Zn. Moreover, the following conditions are fulfilled: B2O3=0% by weight, or Al2O3/B2O3?1.0; and (SiO2+Al2O3+B2O3)/(the total of R2O compounds+the total of R2O compounds)?3.