Abstract: Disclosed herein are transgenic plants and seed having an exogenous DNA which expresses a GB1 protein that imparts increased glycine-betaine content in plants.

Abstract: The present invention relates to a process of obtaining recombinant lambdoid bacteriophage with high density display of functional peptides and proteins on surface of said phage comprising of: constructing a donor plasmid having a nucleotide sequence that defines the elements for replication of the vector in bacteria, a selectable marker, a nucleotide sequence flanked by two non-compatible recombination sequences, and an inducible cistron for expression of a capsid protein and a fusion protein; constructing a recipient phage having a nucleotide sequence that defines the lambdoid elements for replication and packaging of the vector into an assembled bacteriophage and encodes an inducible cistron for expression of a selectable marker flanked by two non-compatible recombination sequences; transferring the said donor plasmid to said recipient plasmid to obtain cointegrates; growing said cointegrates in selective liquid medium; harvesting phages displaying protein encoded by the foreign DNA encapsulated in said ha

Abstract: Methods and kits for simultaneously measuring both members of a binding pair are described.

Abstract: A coupling system can utilize a first receptacle and a second receptacle to couple syringes together. Syringes can be used to mix viscous material and/or dispense the viscous material. Furthermore, a kit can be provided that contains parts used in mixing and/or dispensing viscous material.

Abstract: A process of forming an array of powder samples arranged in predefined locations where all samples have a flat surface in a common plane has been developed. A main support having at least N perforations from a first surface of the main support through a second surface of the main support in predefined locations. The main support is equipped with a flat support temporarily attached to its first surface. All samples are loaded simultaneously. A flat surface of each sample, where the flat surfaces are a common plane, is formed by forcing the samples within the perforations against the flat support. The samples are retained in position within the perforations against the flat support using at least one cover. The flat surfaces of the samples are in predefined locations and are all in a common plane.

Abstract: A system to detect and identify various aerosol agents, such as biological agents which have been aerosolized, is disclosed. The system generally includes a mechanism to collect a selected sample of atmosphere which may include the aerosol agent, a sub-system to detect the presence and type of agent, and a sub-system to communicate the type of agent detected.

Abstract: The invention relates to a compound suitable for inhibiting the influx of polymorphonuclear leukocytes (PMNs) into a tissue involved in a chronic inflammatory disease. The compound according to the invention is capable of forming a complex with N-acetyl-Pro-Gly-Pro. The invention also relates to a method of selecting such a compound, a pharmaceutical composition and an application of the compound.

Abstract: A method of testing an animal for pregnancy or sex identification comprising the steps of first, providing a first vessel containing a liquid and having a removable surface wherein said removable surface is at least partially coated with an antibody and then introducing a bodily fluid from the female animal into said first vessel so that said bodily fluid contacts the liquid and then manipulating the first vessel so that the liquid contacts the antibody. Then, a second vessel containing a reporter hormone solution is provided and the removable surface from the first vessel is displaced to the second vessel and manipulating the second vessel so that the reporter hormone solution contacts the removable surface. Then, a third vessel containing an indicating solution which has an appearance which is related to the amount of the reporter hormone contacted is provided, and the removable surface is displaced from the second vessel to the third vessel.

Abstract: Embodiments described herein include methods and assays for detecting an analyte in a sample using a plurality of control zone capture agents. Some embodiments include detection of multiple analytes in a sample utilizing a plurality of analyte binders and a control zone containing multiple control zone capture agents. In some embodiments, the multiple control zone capture agents capture a plurality of binders within one control zone. Test results are determined by comparison of the control zone signal to a test zone signal.

Abstract: A particle analyzer in which tagged particles to be analyzed are drawn through a suspended capillary tube where a predetermined volume in the capillary tube is illuminated. The illumination scattered by said particles is detected by a detector to count all particles. The fluorescent illumination emitted by tagged particles is detected and the output signals from the fluorescent detectors and scatter detector are processed to provide an analysis of the particles.

Abstract: The invention relates to an assay based on resonance energy transfer (RET), comprising a first molecule grope A, which is marked with at least one energy donor, and at least one second molecule group B which is marked with at least one energy acceptor, the donor comprising a molecule or particle which can be energetically excited by an external radiation source and which is fluorescence enabled and the acceptor comprising a molecule or particle which can be excited by energy transfer via the donor with partial or complete quenching of the donor fluorescence, and the donor and/or acceptor comprise luminescing inorganic dope nanoparticles having an expansion of ?50 nanometers, emitting electromagnetic radiation with stokes or anti-stokes scattering after energetic excitation.

Abstract: The present invention relates to an analytical method and device utilizing magnetic materials and acoustics sensor. The invention employs a magnetic material modified with specific recognizable molecules to capture a substance in a sample and provides an external magnetic field to draw the magnetic material to an sensing region of an acoustics sensor, and then converts an effect occurred on a surface of the sensing region to an amount of the substance in the sample, wherein the effect is caused by a contact of the surface with the magnetic material and the substance.

Abstract: A method contains the steps of (a) heating a silicon substrate in a reaction chamber; and (b) supplying film-forming gas containing source gas, nitridizing gas, and nitridation enhancing gas to a surface of the heated silicon substrate, to deposit on the silicon substrate an Hf1-xAlxO:N film (0.1<x<0.3) having a higher specific dielectric constant than that of silicon oxide, and incorporating N, by thermal CVD. The method can form an oxide film of Hf1-xAlxO (0<x<0.3) having desired characteristics, as a gate insulation film.

Abstract: In a lapping process for lapping away layers from a semiconductor device, where the region of interest is located near an edge or corner of the device, the method includes adding additional semiconductor material adjacent the region of interest.

Abstract: An effective electropurge process and apparatus for wet processing of semiconductor wafers applies electrical charges to the wafer surface with an ample voltage sufficient to provide an effective field intensity which can substantially eliminate intolerable sub-0.05 micron “killer” defects when making highly advanced microchips with a feature size or line width less than 0.15 micron. The process can be used with frequent voltage reversal for automated wet-batch cleaning operations using cassettes that hold 10 to 50 wafers at a time and in various other operations involving megasonic transducers, mechanical brush scrubbers, laser cleaners and CMP equipment. The electropurge process is primarily intended for Fab plants where large wafers with a diameter of 200 to 400 mm require 250 to 350 steps including many dry layering, patterning and doping operations and at least 30 wet processing steps.

Abstract: Methods and apparatus for assessing a constituent in a semiconductor substrate. Several embodiments of the invention are directed toward non-contact methods and systems for identifying an atom specie of a dopant implanted into the semiconductor substrate using techniques that do not mechanically contact the substrate with electrical leads or other types of mechanical measuring instruments. For example, one embodiment of a non-contact method of assessing a constituent in a semiconductor substrate in accordance with the invention comprises obtaining an actual reflectance spectrum of infrared radiation reflected from the semiconductor substrate, and ascertaining a plasma frequency value (?p) and a collision frequency value (?) for the semiconductor substrate based on the actual reflectance spectrum. This method can further include identifying a dopant type based on a relationship between dopant types and (a) plasma frequency values and (b) collision frequency values.

Abstract: A method is disclosed for forming a chamber in an electronic device, including the steps of preparing an outer surface on a solidified core material, the solidified core material in a depression formed in a substrate. The method further includes establishing a layer on the prepared outer surface of the solidified core material and a portion of the substrate surrounding the depression. The established layer and the substrate define a chamber.

Abstract: A method of fabricating an array substrate structure for a liquid crystal display device includes defining a display area and a non-display area on a substrate, the display area having a pixel TFT portion and a pixel electrode area, and the non-display area having an n-type driving TFT portion and a p-type driving TFT portion; forming a first gate electrode in the display area, a second and a third gate electrodes and a first capacitor electrode in the non-display area; an amorphous silicon layer on the substrate; crystallizing the amorphous silicon layer to a polycrystalline silicon layer and doping specific portions of the polycrystalline silicon layer with plurality of impurity concentrations; and forming a first semiconductor layer in the display area, a second and a third semiconductor layers and a second capacitor electrode in the non-display area.

Abstract: A semiconductor film, which is located over a gate electrode for forming a channel region between a source electrode and a drain electrode, has a width greater than a width of the source electrode and a width of the drain electrode located over the gate electrode. Irregularities are formed in a width direction of the semiconductor film on both edge portions in the channel region.

Abstract: In a method for producing a nitride semiconductor light-emitting device according to the present invention, first, a nitride semiconductor substrate having groove portions formed is prepared. An underlying layer comprising nitride semiconductor is formed on the nitride semiconductor substrate including the side walls of the groove portions, in such a manner that the underlying layer has a crystal surface in each of the groove portions and the crystal surface is tilted at an angle of from 53.5° to 63.4° with respect to the surface of the substrate. Over the underlying layer, a light-emitting-device structure composed of a lower cladding layer containing Al, an active layer, and an upper cladding layer containing Al is formed. According to the present invention, thickness nonuniformity and lack of surface flatness, which occur when accumulating a layer with light-emitting-device structure of nitride semiconductor over the nitride semiconductor substrate, are alleviated while inhibiting occurrence of cracking.

Abstract: Phosphonate surfactants are employed to passivate the surfaces of MEMS devices, such as digital micromirror devices. The surfactants are adsorbed from vapor or solution to form self-assembled monolayers at the device surface. The higher binding energy of the phosphonate end groups (as compared to carboxylate surfactants) improves the thermal stability of the resulting layer.

Abstract: A substrate having a sacrificial layer and a structural layer disposed on the front surface of the substrate is provided. Thereon an opening is formed on the back surface of the substrate and the sacrificial layer is exposed partially. A wet etching process is performed to etch the sacrificial layer via the opening to form a suspended structure. Finally, a gas injection process is performed. The gas injection process comprises blowing a gas on the suspended structure via the opening and consequently preventing the suspended structure from sticking to the substrate.

Abstract: A method for forming a color filter is provided. The method comprises steps of providing a substrate having a passivasion layer formed thereon. The substrate has at least one complementary metal-oxide semiconductor formed therein and the passivasion layer has at least trench formed therein in a peripheral region of the substrate. At least two adjacent color filter blocks are sequentially formed over the passivasion layer and the color filter blocks comprises a first color filter block and a second color filter block. The first color filter block and the second color filter block are disposed within a display region of the substrate. Moreover, the material for forming the first color filter, which is formed prior to the formation of the second color filter block, further fills the trench in the peripheral region simultaneously with a formation of the first color filter block.

Abstract: An image sensor includes a substrate region of a first conductivity type, a photodiode region of a second conductivity type located in the substrate, a hole accumulated device (HAD) region of the first conductivity type located at a surface of the substrate and over the photodiode region, and a transfer gate located over the surface of the substrate adjacent the HAD region. The image sensor further includes a first channel region of the first conductivity type located in the substrate and aligned below the transfer gate, a second channel region of the second conductivity type located in the substrate between said transfer gate and the first channel region, and an floating diffusion region which is located in the substrate and which electrically contacts the second channel region.

Abstract: A method for solder bumping provides a substrate and forms a film on the substrate. The film has openings therethrough. A stencil is aligned on the film. The stencil has openings therethrough over the openings through the film. Solder paste is printed onto the substrate and into the openings through the stencil and the openings through the film. The solder paste is reflowed to form solder balls therefrom. The stencil and the film are then removed.

Abstract: The invention relates to a donor laminate comprising in order, a substrate, an electronically conductive polymer layer in contact with said substrate, and a metal layer.

Abstract: A mounting zone and a reflow zone are arranged in parallel between a loader and an unloader, and mounting and reflow processes are performed simultaneously.

Abstract: A method of fabricating a semiconductor device, including: preparing a wiring board on which is mounted a first semiconductor chip having a plurality of first pads; electrically connecting each of the first pads to an interconnecting pattern of the first semiconductor chip by a wire; providing resin paste on the first semiconductor chip; mounting a second semiconductor chip having a plurality of second pads on the first semiconductor chip with the resin paste interposed therebetween; and forming a spacer by hardening the resin paste to fix the first and second semiconductor chips together, wherein the spacer is formed to extend under the second pads and further outward; and wherein the highest portion of the wire is disposed on the outer side of the first semiconductor chip.

Abstract: A method of creating a predefined internal pressure within a cavity of a semiconductor device, the method including providing the semiconductor device, the semiconductor device including a semiconductor oxide area which is continuously arranged between the cavity of the semiconductor device and an external surface of the semiconductor device, exposing the semiconductor device to an ambient atmosphere with a noble gas at a first temperature for a predetermined time period, and setting a second temperature, which is different from the first, after the predetermined time period has expired, the semiconductor oxide area exhibiting a higher permeability for the noble gas at the first temperature than at the second temperature.

Abstract: A semiconductor chip package includes a first semiconductor chip, that is an MEMS chip having a movable structure. The movable structure has a movable section. The first semiconductor chip includes a plurality of first electrode pads, and a first sealing section. The first sealing section is a closed loop formed on the top face of the frame section surrounding the movable structure. The first semiconductor chip also includes a thin plate member for sealing the movable structure. The semiconductor chip package also includes a second semiconductor chip. The second semiconductor chip has a plurality of second electrode pads. The semiconductor chip package also includes a substrate. The substrate has third electrode pads. The first and second semiconductor chips are mounted on the substrate. First bonding wires connect the first electrode pads to the second electrode pads. Second bonding wires connect the second electrode pads to the third electrode pads.

Abstract: A process for fabricating a leadless plastic chip carrier includes providing a leadframe including a plurality of contacts circumscribing a void; fixing a heat sink to the contacts of the leadframe using an intermediate non-electrically conductive adhesive such that the heat sink spans the void; mounting a semiconductor die to the heat sink in the void; wire bonding ones of the contacts to the pads of the semiconductor die; encapsulating the semiconductor die and the wire bonds in a molding material and singulating the leadless plastic chip carrier.

Abstract: In a method and an apparatus for dividing a plate-like member related to the present invention, multiple substrates are obtained by forming a linear modified region on a surface of a plate-like member formed from a hard and brittle material or in the interior of the plate-like member and dividing the plate-like member along this modified region. The method for dividing a plate-like member includes a tape sticking step which involves sticking tape on the surface of the plate-like member, a modified region forming step which involves forming a modified region on surface of the plate-like member or in the interior of the plate-like member, and an expanding step which involves elongating the tape by applying a tension thereto after the modified region forming step. In the expanding step, the tape is irradiated with UV rays. As a result of this, it is possible to positively manufacture an ultrathin chip with a good end-face shape in which uncut portions, chipping and breakage do not occur.

Abstract: The invention provides a semiconductor chip package, and a means of forming such a semiconductor chip package, in which one or more semiconductor chips are electrically connected to a mounting substrate by wire bonding in which an adhesive tape is provided on the active surface of the semiconductor chips for encapsulating at least an upper portion of the bonding wires adjacent the active surfaces to improve the stability of the bonding wires during subsequent processing.

Abstract: An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting composition including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.

Abstract: A semiconductor device improved in packaging reliability is disclosed. Each of leads used in the semiconductor device has a first surface positioned between a main surface of a resin sealing body and a back surface opposite to the main surface of the resin sealing body, a second surface positioned on the side opposite to the first surface and exposed from the back surface of the resin sealing body, a first end face positioned on a semiconductor chip side, a second end face positioned on the side opposite to the first end face and exposed from a side face of the resin sealing body, and a recessed portion depressed from the second surface to the first surface side and contiguous to the second end face, the second surface and an inner wall surface of the recessed portion being covered with a plating layer which is higher in solder wettability than the second end face of each of the leads.

Abstract: A short-prevented lead frame and a method for fabricating a semiconductor package with the lead frame are proposed, wherein each lead of the lead frame is formed with a thickness-reduced portion at a peripheral position of the lead frame, allowing thickness-reduced portions of adjacent leads to be arranged in a stagger manner. This stagger arrangement significantly increases pitches between the neighboring thickness-reduced portions of leads. Therefore, during a singulation process as to cut through the leads, lead bridging and short-circuiting between adjacent leads caused by cut-side burrs can be prevented from occurrence, whereby singulation quality and product yield and reliability are effectively improved.

Abstract: A photosensitive semiconductor package, a method for fabricating the same, and a lead frame thereof are proposed. The lead frame has a die pad and a plurality of leads, wherein at least one recessed portion is formed at an end of each lead close to the die pad, and at least one recessed region is formed on the die pad. An encapsulant fills the recessed portions, the recessed region, and between the leads and the die pad, and is formed on the lead frame to define a chip receiving cavity. A photosensitive chip is mounted in the chip receiving cavity, wherein at least partially a non-active surface of the chip is attached to the encapsulant filling the recessed region and is not in contact with the recessed region. A light-penetrable unit is attached to the encapsulant formed on the lead frame to seal the chip receiving cavity.

Abstract: A method for manufacturing a mounting substrate on which a semiconductor chip is mounted includes: forming a wiring section by electrolytic plating on a first face of a supporting substrate which is made of an insulating material, by supplying electric power from a first power supply layer through a via plug piercing through the supporting substrate, the first power supply layer being formed on a second face of the supporting substrate; performig patterning on the first power supply layer so as to form a first conductive pattern which is connected to the wiring section through the via plug; performing a connection test of the wiring section by using the conductive pattern; mounting the semiconductor chip on the wiring section; and removing the supporting substrate.

Abstract: A memory cell and a method of fabricating the same. A first conductive layer on a substrate is provided and a first type doped semiconductor layer is then formed on the first conductive layer. The first type doped semiconductor layer and the first conductive layer are patterned into a first line. A dielectric layer is formed on the substrate with an opening exposing the first line. A column comprising a second diode component, a buffer layer, and an anti-fuse layer is formed in the opening. A second line is formed connecting the column on the dielectric layer running generally perpendicularly to the first line.

Abstract: The present invention provides a thin film transistor in which a substantial length of a channel is shortened to miniaturize a semiconductor device and a manufacturing method thereof. In addition, the present invention provides a semiconductor device which realizes high-speed operation and high-performance of the semiconductor device and a manufacturing method thereof. Further in addition, it is an object of the present invention to provide a manufacturing method in which a manufacturing process is simplified. The semiconductor device of the present invention has an island-shaped semiconductor film formed over a substrate having an insulating surface and a gate electrode formed over the island-shaped semiconductor film, in which the gate electrode is oxidized its surface by high-density plasma to be slimmed and the substantial length of a channel is shortened.

Abstract: A method (10) of forming fully-depleted silicon-on-insulator (FD-SOI) transistors (150) and bulk transistors (152) on a semiconductor substrate (104) as part of an integrated circuit fabrication process is disclosed.

Abstract: A method (10) of forming fully-depleted silicon-on-insulator (FD-SOI) transistors (150) and partially-depleted silicon-on-insulator (FD-SOI) transistors (152) on a semiconductor substrate (104) as part of an integrated circuit fabrication process is disclosed.

Abstract: A method for fabricating a thin film transistor for an LCD device is presented that uses six mask processes. Portions of a semiconductor layer formed on a substrate are doped with first and second impurities in different regions. A conductive layer is deposited and the conductive and semiconductor layers patterned together by diffraction exposure using a diffraction pattern mask to define source and drain regions and an activate region. Ashing is performed and portions of the conductive layer removed to form the source, drain and channel. A gate insulating layer is formed on the substrate and gates are formed on the gate insulating layer. A passivation film is formed on the substrate and a pixel contact hole exposing one of the drains is etched. A pixel electrode is then deposited such that the pixel electrode is connected to the drain through the pixel contact hole.

Abstract: An SRAM cell that may reduce or eliminate floating body effect when using a SOI and a method for fabricating the same are provided. A floating body of an access transistor of the SRAM is connected to a source region of a driver transistor, for example, through a body extension region extending from an active region. A silicide layer may be formed or a ground line contact may be over-etched to form a conductive contact plug that may provide a current path between the body exterior regions and the source region of the driver transistor.

Abstract: A method of fabrication and a field effect device structure are presented that reduce source/drain capacitance and allow for device body contact. A Si based material pedestal is produced, the top surface and the sidewalls of which are oriented in a way to be substantially parallel with selected crystallographic planes of the pedestal and of a supporting member. The pedestal is wet etched with an anisotropic solution containing ammonium hydroxide. The sidewalls of the pedestal become faceted forming a segment in the pedestal with a reduced cross section. The dopant concentration in the reduced cross section segment is chosen to be sufficiently high for it to provide for electrical continuity through the pedestal.

Abstract: A memory circuit having dual-gate memory cells and a method for fabricating such a memory circuit are disclosed. The dual-gate memory cells each include a memory device and an access device sharing a semiconductor layer, with their respective channel regions provided on different surfaces of the semiconductor layer. The semiconductor layer has a thickness, such that when a pass voltage is applied to the gate electrode of the access device, the access device and the memory device remains isolated, such that the charge stored in the memory device is unaffected by the pass voltage. The pass voltage is determined from a range of voltages, when applied to the access device, has no effect on the threshold voltage of the memory device. The dual-gate memory cells can be used as building blocks for a non-volatile memory array, such as a memory array formed by NAND-strings.

Abstract: The first source and drain regions are formed in an upper surface of a SiGe substrate. The first source and drain regions containing an N type impurity. Vacancy concentration in the first source and drain regions are reduced in order to reduce diffusion of the N type impurity contained in the first source and drain regions. The vacancy concentration is reduced by an interstitial element or a vacancy-trapping element in the first source and drain regions. The interstitial element or the vacancy-trapping element is provided by ion-implantation.

Abstract: There is provided a semiconductor device including a semiconductor circuit formed by semiconductor elements having an LDD structure which has high reproducibility, improves the stability of TFTs and provides high productivity and a method for manufacturing the same. In order to achieve the object, the design of a second mask is appropriately determined in accordance with requirements associated with the circuit configuration to make it possible to form a desired LDD region on both sides or one side of the channel formation region of a TFT.

Abstract: There are provided a crystallization method which can design laser beam having a light intensity and a distribution optimized on an incident surface of a substrate, form a desired crystallized structure while suppressing generation of any other undesirable structure area and satisfy a demand for low-temperature processing, a crystallization apparatus, a thin film transistor and a display apparatus. When crystallizing a non-single-crystal semiconductor thin film by irradiating laser beam thereto, irradiation light beam to the non-single-crystal semiconductor thin film have a light intensity with a light intensity distribution which cyclically repeats a monotonous increase and a monotonous decrease and a light intensity which melts the non-single-crystal semiconductor. Further, at least a silicon oxide film is provided on a laser beam incident surface of the non-single-crystal semiconductor film.

Abstract: A silicon film is crystallized in a predetermined direction by selectively adding a metal element having a catalytic action for crystallizing an amorphous silicon and annealing. In manufacturing TFT using the crystallized silicon film, TFT provided such that the crystallization direction is roughly parallel to a current-flow between a source and a drain, and TFT provided such that the crystallization direction is roughly vertical to a current-flow between a source and a drain are manufactured. Therefore, TFT capable of conducting a high speed operation and TFT having a low leak current are formed on the same substrate.