Abstract: Disclosed herein is a sterilizer used at dental clinics to sterilize handpieces by the irradiation of ultraviolet rays. When inserting a contaminated handpiece into a sterilizer, an ultraviolet barrier is opened confirming the approach of the handpiece by a sensor. After the insertion of the handpiece, the ultraviolet barrier is closed, then ultraviolet lamps are turned on for a pre-determined time and then turned off, and the ultraviolet barrier is opened again. After the withdrawal of the handpiece, the ultraviolet barrier is closed. The handpiece is not contacted with the outside of the sterilizer, preventing the handpiece from being contaminated again by the sterilizer, and the leakage of the ultraviolet rays is prevented.

Abstract: A projection objective of a microlithographic projection exposure apparatus has a last optical element on the image side which is plane on the image side and which, together with an image plane of the projection objective, delimits an immersion space in the direction of an optical axis of the projection objective. This immersion space can be filled with an immersion liquid. At least one liquid or solid volume having plane-parallel interfaces can be introduced into the beam path of the projection objective, the optical thickness of the at least one volume being at least substantially equal to the optical thickness of the immersion space. By introducing and removing the volume, it is possible to convert the projection objective from dry operation to immersed operation in a straightforward way, without extensive adjustments to the projection objective or alignment work.

Abstract: An irradiating apparatus includes a support member and a reflector supported by the support member to define a concave light energy reflector surface. A light source of radiating energy is disposed generally at the source focal point of the reflector. The support member has a passage for cooling air to flow therethrough and openings for distributing the cooling air to the apparatus. The support member, thereby, performs a dual function of supporting the reflector as well as providing a manifold for the cooling air.

Abstract: An apparatus and method for EUV light production is disclosed which may comprise a laser produced plasma (“LPP”) extreme ultraviolet (“EUV”) light source control system comprising a target delivery system adapted to deliver moving plasma initiation targets and an EUV light collection optic having a ibeus defining a desired plasma initiation site, comprising; a target tracking and feedback system comprising: at least one imaging device providing as an output an image of a target stream track, wherein the target stream track results from the imaging speed of the camera being too slow to image individual plasma formation targets forming the target stream imaged as the target stream track; a stream track error detector detecting an error in the position of the target stream track in at least one axis genemily perpendicular to the target stream track from a desired stream truck intersecting the desired plasma initiation site.

Abstract: Certain exemplary embodiments of the present invention comprise a device comprising a cast collimator derived from a metallic foil stack lamination mold, said collimator defining a feature adapted to contain a plurality of radiation detection elements. In certain embodiments, the collimator can define a feature adapted to contain a plurality of radiation detection elements, such as scintillators. Certain exemplary embodiments of the present invention comprise a device comprising a cast component derived from a metallic foil stack lamination mold. In various exemplary embodiments, the cast components can be a mechanical, electrical, electronic, optical, fluidic, biomedical, and/or biotechnological component. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.

Abstract: A system and method of estimating the thickness of the individual sheets in a stack of sheets in a print media sheet input stacking tray before printing with an electronic sensing system for electronically detecting individual sheet edges in the stack thereof and a movement system providing a known traversal distance of the sheet edge sensing system relative to one side of the stack to produce multiple signals corresponding to multiple detected individual sheet edges, and dividing that multiplicity of signals into the known traversal movement to estimate the thickness of the individual print media sheets in the stack and provide a corresponding electrical output can be used for automatic control of sheet feeder, printer or finisher functions. A relatively simple contacting or non-contacting sensor may be used.

Abstract: A method and system for determining the lateral position of an edge of a web are disclosed. The system includes an array of light transmitting elements and a corresponding array of lenses and an array of light receiving elements and a corresponding array of lenses. The light transmitting elements are each paired with a light receiving element and the light transmitting elements each transmit a beam of light energy towards the corresponding receiving element. The beams of light can be occluded by a web passing between the transmitting elements and the receiving elements, thereby reducing the light received by the receiving elements. The receiving elements can generate a signal that is proportional to the amount of they receive, and a controller can be used to determine the lateral position of an edge of the web in response to the signals generated by the receivers. A compensation light beam can be employed to enable the controller to compensate for several factors that can affect measurement accuracy.

Abstract: An apparatus for inspecting particles and/or pattern defects of an object under inspection. Data processing means obtains information on size of the particles and/or the pattern defects from an intensity of the scattered light detected by the light detecting means by referring to a relationship between an intensity of scattered light from a standard particle and a size of the standard particle, and using a calibration coefficient for compensating for a change in intensity of the light of the illuminating means from a predetermined intensity.

Abstract: A phase-change memory device has an oxidation barrier layer to protect against memory cell contamination or oxidation and a method of manufacturing the same. In one embodiment, a semiconductor memory device comprises a molding layer overlying a semiconductor substrate. The molding layer has a protrusion portion vertically extending from a top surface thereof. The device further includes a phase-changeable material pattern adjacent the protrusion portion and a lower electrode electrically connected to the phase-changeable material pattern.

Abstract: A method for manufacturing a field-effect transistor includes the steps of forming a source electrode and a drain electrode each containing hydrogen or deuterium; forming an oxide semiconductor layer in which the electrical resistance is decreased if hydrogen or deuterium is added; and, causing hydrogen or deuterium to diffuse from the source electrode and the drain electrode to the oxide semiconductor layer.

Abstract: A semiconductor probe with a resistive tip and a method of fabricating the semiconductor probe. The resistive tip doped with a first impurity includes a resistive region formed at a peak thereof and lightly doped with a second impurity opposite in polarity to the first impurity, and first and second semiconductor regions formed on sloped sides thereof and heavily doped with the second impurity. The semiconductor probe includes the resistive tip, a cantilever having an end on which the resistive tip is disposed, a dielectric layer disposed on the cantilever and covering the resistive region, and a metal shield disposed on the dielectric layer and having an opening formed at a position corresponding to the resistive region.

Abstract: To improve the reliability of contact with an anisotropic conductive film in a semiconductor device such as a liquid crystal display panel, a terminal portion (182) of a connecting wiring (183) on an active matrix substrate is electrically connected to an FPC (191) by an anisotropic conductive film (195). The connecting wiring (183) is manufactured in the same process with a source/drain wiring of a TFT on the active matrix substrate, and is made of a lamination film of a metallic film and a transparent conductive film. In the connecting portion with the anisotropic conductive film (195), a side surface of the connecting wiring (183) is covered with a protecting film (173) made of an insulating material.

Abstract: The invention discloses a switching element of a pixel electrode for a display device and methods for fabricating the same. A gate is formed on a substrate. A first copper silicide layer is formed on the gate. An insulating layer is formed on the first copper silicide layer. A semiconductor layer is formed on the insulating layer. A source and a drain are formed on the semiconductor layer. Moreover, a second copper silicide layer is sandwiched between the semiconductor layer and the source/drain.

Abstract: A pixel structure, suitable being driven by a scan line and a data line on a substrate, is provided. The pixel structure includes a thin film transistor (TFT) and a pixel electrode. Wherein, the TFT includes a gate, a first and a second dielectric layer, a semiconductor layer, a source, and a drain. Especially, the semiconductor layer has a body part and at least one extending part connected to thereof. The extending part is protruded from the edge of the body part disposed between the source and the drain. In addition, at least one contact hole is disposed in the second dielectric layer for exposing the extending part, and the first dielectric layer, the semiconductor layer, and the second dielectric layer at the extending part are removed through the contact hole. So, leakage current can be effectively reduced, thereby raising the Ion/Ioff ratio of the pixel structure.

Abstract: Structure and methods of fabrication are disclosed for an enhanced FET devices in which dopant impurities are prevented from diffusing through the gate insulator. The structure comprises a Si:C, or SiGe:C, layer which is sandwiched between the gate insulator and a layer which is doped with impurities in order to provide a preselected workfunction. It is further disclosed how this, and further improvements for FET devices, such as raised source/drain and multifaceted gate on insulator, MODFET on insulator are integrated with strained Si based layer on insulator technology.

Abstract: To achieve promotion of stability of operational function of display device and enlargement of design margin in circuit design, in a display device including a pixel portion having a semiconductor element and a plurality of pixels provided with pixel electrodes connected to the semiconductor element on a substrate, the semiconductor element includes a photosensitive organic resin film as an interlayer insulating film, an inner wall face of a first opening portion provided at the photosensitive organic resin film is covered by a second insulating nitride film, a second opening portion provided at an inorganic insulating film is provided on an inner side of the first opening portion, the semiconductor and a wiring are connected through the first opening portion and the second opening portion and the pixel electrode is provided at a layer on a lower side of an activation layer.

Abstract: A thin film array panel is provided, which includes: a plurality of signal lines including contact parts for contact with an external device; a plurality of thin film transistors connected to the signal lines; an insulating layer formed on the signal lines and the thin film transistors; and a plurality of pixel electrodes formed on the insulating layer and connected to the thin film transistors, wherein the insulating layer includes a contact portion disposed on the contact parts of the signal lines and having a thickness smaller than other portions and the contact portion of the insulating layer includes an inclined portion having an inclination angle smaller than about 45 degrees.

Abstract: A thin film transistor array substrate has a gate electrode of the thin film transistor, a gate line connected to the gate electrode, and a gate pad connected to the gate line; a source/drain pattern including a source electrode and a drain electrode of the thin film transistor, a data line connected to the source electrode, a data pad connected to the data line, a storage electrode formed and superimposed with the gate line; a semiconductor pattern formed in low part of the substrate; a transparent electrode pattern including a pixel electrode connected to the drain electrode and the storage electrode, a gate pad protection electrode covering the gate pad, and a data pad protection electrode covering the data pad; and a protection pattern and a gate insulation pattern stacked in a region other than the region where the transparent electrode pattern is formed.

Abstract: A Schottky barrier silicon carbide device has a Re Schottky metal contact. The Re contact 27 is thicker than 250 Angstroms and may be between 2000 and 4000 Angstroms. A termination structure is provided by ion milling an annular region around the Schottky contact.

Abstract: A semiconductor device can comprise a contact material in substantially continuous contact with a contact region. In an embodiment the contact region may comprise an alloy comprising a wide band-gap material and a low melting point contact material. A wide band-gap material may comprise silicon carbide and a low melting point contact material may comprise aluminum. In another embodiment a substantially uniform ohmic contact may be formed between a contact material and a semiconductor material by annealing the contact at a temperature less than the melting point of the contact material. In an embodiment, the contact may be annealed for more than five hours.

Abstract: A semiconductor light emitting device can have stable electric characteristics and can emit light with high intensity from a substrate surface. The device can include a transparent substrate and a semiconductor layer on the substrate. The semiconductor layer can include a first conductive type semiconductor layer, a luminescent layer, a second conductive type semiconductor layer, and first and second electrodes disposed to make contact with the first and second conductive type semiconductor layers, respectively. The first conductive type semiconductor layer, the luminescent layer, and the second conductive type semiconductor layer can be laminated in order from the side adjacent the substrate. An end face of the semiconductor layer can include a first terrace provided in an end face of the first conductive type semiconductor layer in parallel with the substrate surface, and an inclined end face region provided nearer to the substrate than the first terrace.

Abstract: A light emitting device having a monolithic protection element and a method of fabricating the light emitting device are provided. The light emitting device includes: a light emitter having a cathode and an anode; and the resistive protection element connected to the light emitter in parallel through the cathode and the anode. Here, a resistance Rs of the resistive protection element has a value between a forward resistance Rf and a reverse resistance Rr of a current of the light emitter.

Abstract: A package for light emitting element including a package main body 1 having a bottom face 7a on which a light emitting element 2 is arranged, and a concave portion 7 which is formed in an inverted truncated cone shape by an inner wall face 7b intersecting with the bottom face 7a with a predetermined angle, and a translucent member 6 filled in the concave portion 7 of the package main body 1, the angle between the inner wall face 7b composing the concave portion 7 and the bottom face 7a is selected within ±15° of the incident critical angle in which a direct light radiated from the light emitting element 2 undergoes total reflection at the interface between the translucent member 6 and air.

Abstract: A compound electrode comprises a first layer that comprises at least one halide compound of at least one metal selected from the group consisting of alkali metals and alkaline-earth metals; and a second layer comprising an electrically conducting material. The second layer is disposed between the first layer and an electronically active material of an electronic device. The compound electrode can serve as a cathode for an organic light-emitting device or an organic photovoltaic device. The compound electrode can be produced to be substantially transparent.

Abstract: A light emitting diode module, a backlight assembly having the light emitting diode module, and a display device having the backlight assembly. The light emitting diode module includes a light emitting device including a light emitting diode chip, a body that surrounds the light emitting diode chip, and a heat releasing member that is in contact with the light emitting diode chip and protrudes from the body. The light emitting diode module also includes a printed circuit board having a hole corresponding to a protruding end portion of the heat releasing member.

Abstract: A light source apparatus and a fabrication method thereof can prevent light interference between light emitting devices adjacent to each other by forming a groove in a sub-mount and bonding a light emitting device to the groove, enhance heat radiating effect as well as luminous efficiency by collecting light emitted from the side of the light emitting device toward the front of the light source apparatus, reduce the process time and costs and increase reliability by directly connecting the sub-mount to the stem by the first electrode and the second electrode which pass through holes of the sub-mount, and extend a life span of the light emitting device because of the enhanced heat radiating effect.

Abstract: An InP high electron mobility transistor (HEMT) structure in which a gate metal stack includes an additional thin layer of a refractory metal, such as molybdenum (Mo) or platinum (Pt) at a junction between the gate metal stack and a Schottky barrier layer in the HEMT structure. The refractory metal layer reduces or eliminates long-term degradation of the Schottky junction between the gate metal and the barrier layer, thereby dramatically improving long-term reliability of InP HEMTs, but without sacrifice in HEMT performance, whether used as a discrete device or in an integrated circuit.

Abstract: The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.

Abstract: An integrated circuit chip includes a substrate, a device layer, an interconnection layer, a sealing base layer and a sealing ring stack layer. The substrate has a sealing region and a chip region. The sealing region is disposed around the chip region. The device layer is disposed within the chip region. The interconnection layer is disposed over and connected with the device layer. The sealing base layer is disposed within the sealing region. The sealing ring stack layer is disposed over and connected with the sealing base layer. A manufacturing process of the integrated circuit chip is also disclosed.

Abstract: A semiconductor device includes a transfer channel for transferring charge generated by photoelectric conversion, an insulating film formed on the transfer channel, and a transfer electrode for applying a transfer voltage to the transfer channel via the insulating film. The insulating film has a first thickness and a second thickness that is thinner than the first thickness. The insulating film has the first thickness below both ends of the transfer electrode in a width direction of the transfer channel that is orthogonal to a charge transfer direction through the transfer channel, and the insulating film has the second thickness on a part including a center of the transfer channel in the width direction.

Abstract: It is an object to provide solid-state imaging device, which can easily be manufactured and has a high reliability, and a method of manufacturing the solid-state imaging device. In the present invention, a manufacturing method comprises the steps of forming a plurality of IT-CCDs on a surface of a semiconductor substrate, bonding a translucent member to the surface of the semiconductor substrate in order to have a gap opposite to each light receiving region of the IT-CCD, and isolating a bonded member obtained at the bonding step for each of the IT-CCDs.

Abstract: The present invention provides a JFET which receives an additional implant during fabrication, which extends its drain region towards its source region, and/or its source region towards its drain region. The implant reduces the magnitude of the e-field that would otherwise arise at the drain/channel (and/or source/channel) junction for a given drain and/or source voltage, thereby reducing the severity of the gate current and breakdown problems associated with the e-field. The JFET's gate layer is preferably sized to have a width which provides respective gaps between the gate layer's lateral boundaries and the drain and/or source regions for each implant, with each implant implanted in a respective gap.

Abstract: A semiconductor photodetecting device is provided for enabling a solid-state image sensor to meet the requirements of higher quality imaging and more reduction in cost. The photodetecting device of the present invention includes: a semiconductor substrate; and an epitaxial layer formed on the semiconductor substrate by epitaxial growth. The epitaxial layer has a multilayer structure including: a first pn junction layer; a first insulating layer; a second pn junction layer; a second insulating layer; and a third pn junction layer. The first insulating layer and the second insulating layer have openings, and the first pn junction layer and the second pn junction layer are adjacent to each other through the openings of the first insulating layer which is placed in between these pn junction layers, and the second pn junction layer and the third pn junction layer are adjacent to each other through the openings of the second insulating layer which is placed in between these pn junction layers.

Abstract: An active pixel sensor for producing images from electron-hole producing radiation includes a crystalline semiconductor substrate having an array of electrically conductive diffusion regions, an interlayer dielectric (ILD) layer formed over the crystalline semiconductor substrate and comprising an array of contact electrodes, and an interconnect structure formed over the ILD layer, wherein the interconnect structure includes at least one layer comprising an array of conductive vias. An array of patterned metal pads is formed over the interconnect structure and are electrically connected to an array of charge collecting pixel electrodes. A radiation absorbing structure includes a photoconductive N-I-B-P photodiode layer formed over the interconnect structure, and a surface electrode layer establishes an electrical field across the radiation absorbing structure and between the surface electrode layer and each of the array of charge collecting pixel electrodes.

Abstract: A CMOS image sensor and a manufacturing method are disclosed. The gates of the transistors are formed in the active region of the unit pixel, and a diffusion region for the photo diode is defined by an ion implantation of impurities to the semiconductor substrate. The patterns of the photoresist that are the masking layer against ion implantation are formed on the semiconductor substrate in such a manner that they have the boundary portion of the isolation layer so as not to make the boundary of the defined photo diode contact with the boundary of the isolation layer. Damages by an ion implantation of impurities at the boundary portion between the diffusion region for the photo diode and the isolation layer are prevented, which reduces dark current of the COMS image sensor.

Abstract: A spin transistor includes a first conductive layer that is made of a ferromagnetic material magnetized in a first direction, and functions as one of a source and a drain; a second conductive layer that is made of a ferromagnetic material magnetized in one of the first direction and a second direction that is antiparallel with respect to the first direction, and functions as the other one of the source and the drain. The spin transistor also includes a channel region that is located between the first conductive layer and the second conductive layer, and introduces electron spin between the first conductive layer and the second conductive layer; a gate electrode that is located above the channel region; and a tunnel barrier film that is located between the channel region and at least one of the first conductive layer and the second conductive layer.

Abstract: A semiconductor storage device has a first transistor of first conductive type which control data writing, a second transistor of second conductive type which controls data read-out, a third transistor which amplifies a current corresponding to data to be read out, a first semiconductor layer which is disposed in a predetermined direction, in which a gate of the first transistor is formed, a second semiconductor layer which is disposed separately from the first semiconductor layer in the predetermined direction, in which source and drain of the second transistor and source and drain of the third transistor are formed, a write transistor forming region which is disposed in a direction intersecting the first and second semiconductor layers, in which source and drain of the first transistor, a gate of the third transistor and an electric charge storing region storing electric charge in accordance with data to be written are formed, and a read-out transistor gate region which is disposed in a direction intersecti

Abstract: Dielectric layers containing a lanthanum hafnium oxide layer, where the lanthanum hafnium oxide layer is arranged as a structure of one or more monolayers, provide an insulating layer in a variety of structures for use in a wide range of electronic devices.

Abstract: In order to improve the soft error resistance of a memory cell of an SRAM without increasing its chip size in deep through-holes formed by perforating a silicon oxide film, there is a silicon nitride film and a silicon oxide film, a capacitor element having a TIN film serving as a lower electrode. This capacitor element is connected between a storage node and a supply voltage line, between a storage node and a reference voltage line, or between storage nodes of the memory cell of the SRAM.

Abstract: A NAND includes a device isolation pattern disposed in a region of a substrate defining a plurality of active regions. Memory transistors having memory gate patterns, constituting a cell string, cross the plurality of active regions. Select transistors are disposed over the memory transistors, and lower plugs are disposed on each side of the cell string to electrically connect the plurality of active regions on both sides of the cell string and the select transistors.

Abstract: Integrated circuit devices are fabricated by fabricating a conductive line on an insulating layer on an integrated circuit substrate. The conductive line includes a bottom adjacent the insulating layer, a top remote from the insulating layer and first and second sidewalls therebetween. An insulating spacer is formed to extend along the first and second sidewalls and to also extend along at least a portion of the bottom between the conductive line and the insulating layer. By providing an insulating spacer beneath at least a portion of the conductive line, insulation reliability may be improved even as the spacer may become narrower and/or the contact area may be enlarged.

Abstract: A vertical type nanotube semiconductor device including a nanotube bit line, disposed on a substrate and in parallel with the substrate and composed of a nanotube with a conductive property, and a nanotube pole connected to the bit line vertically to the substrate and provides a channel through which carriers migrate. By manufacturing the semiconductor device using the bit line composed of the nanotube, cutoff of an electrical connection of the bit line is prevented and an integration density of the semiconductor device can be improved.

Abstract: The object of the present invention is to provide a new nonvolatile semiconductor memory device and its manufacturing method for the purpose of miniaturizing a virtual grounding type memory cell based on a three-layer polysilicon gate, enhancing the performance, and boosting the yield. In a memory cell according to the present invention, a floating gate's two end faces perpendicular to a word line and channel are partly placed over the top of a third gate via a dielectric film. The present invention can reduce the memory cell area of a nonvolatile semiconductor memory device, increase the operating speed, and enhances the yield.

Abstract: A nonvolatile semiconductor device and a method of fabricating the same are provided. The nonvolatile semiconductor device includes a semiconductor body formed on a substrate to be elongated in one direction and having a cross section perpendicular to a main surface of the substrate and elongated direction, the cross section having a predetermined curvature, a channel region partially formed along the circumference of the semiconductor body, a tunneling insulating layer disposed on the channel region, a floating gate disposed on the tunneling insulating layer and electrically insulated from the channel region, an intergate insulating layer disposed on the floating gate, a control gate disposed on the intergate insulating layer and electrically insulated from the floating gate, and source and drain regions which are aligned with both sides of the control gate and formed within the semiconductor body.

Abstract: Nonvolatile memory cells having a conductor-filter system, a conductor-insulator system, and a charge-injection system are provided. The conductor-filter system provides band-pass filtering function, charge-filtering function, and mass-filtering function to charge-carriers flows. The conductor-insulator system provides Image-Force barrier lowering effect to collect charge-carriers. The charge-injection system includes the conductor-filter system and the conductor-insulator system, wherein the filter of the conductor-filter system contacts the conductor of the conductor-insulator system. Apparatus on cell architecture are provided for the nonvolatile memory cells. Additionally, apparatus on array architectures are provided for constructing the nonvolatile memory cells in memory array. Method on manufacturing such memory cells and array architectures are provided.

Abstract: A semiconductor device includes a spacer adjacent a gate structure. A protection layer covers oxide portions of the spacer surface such that subsequent manufacturing operations such as wet oxide etches and strips, do not produce voids in the spacers. A method for forming the semiconductor device provides forming a gate structure with adjacent spacers including an oxide liner beneath a nitride section, then forming the protection layer over the structure, and removing portions of the protection layer but leaving other portions of the protection layer intact to cover and protect underlying oxide portions of the spacer during subsequent processing such as the formation and removal of a resist protect oxide (RPO) layer. The protection layer is advantageously formed of a nitride film and an oxide film and produces a double spacer effect when partially removed such that only vertical sections remain.

Abstract: A method of forming an array of floating gate memory cells, and an array formed thereby, that includes source and drain regions formed in a substrate, and a conductive block of material disposed over the source region. The floating gate is formed as a thin, L-shaped layer of conductive material having a first portion disposed over the channel region and a second portion extending vertically along the conductive block. The control gate includes a first portion disposed adjacent to and insulated from a distal end of the floating gate first portion, and a second portion disposed adjacent to the channel region. A portion of the control gate could extend into a trench formed into the substrate, wherein the drain region is formed underneath the trench, and the channel region has a first portion extending along the trench sidewall and a second portion extending along the substrate surface.

Abstract: The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.

Abstract: A vertical unipolar component formed in a semiconductor substrate, comprising vertical fingers made of a conductive material surrounded with silicon oxide, portions of the substrate being present between the fingers and the assembly being coated with a conductive layer. The component periphery includes a succession of fingers arranged in concentric trenches, separated from one another by silicon oxide only, the upper surface of the fingers of at least the innermost rank being in contact with said conductive layer.

Abstract: A lateral high-voltage device in which conductive trench plates are inserted across the voltage-withstand region, so that, in the on state, the current density vectors have less convergence. This can help reduce on-resistance.