Abstract: A silicon-on-insulator metal oxide semiconductor device comprising ultrathin silicon-on-sapphire substrate; at least one P-channel MOS transistor formed in the ultrathin silicon layer; and N-type impurity implanted within the ultrathin silicon layer and the sapphire substrate such that peak N-type impurity concentration in the sapphire layer is greater than peak impurity concentration in the ultrathin silicon layer.

Abstract: In an NLDMOS, DMOS or NMOS active device the ability to withstand snapback under stress conditions is provided by moving the hot spot away from the drain contact region. This is achieved by moving the drain contact region further away from the gate and including an additional n-region next to the drain or an additional floating p-region next to the drain.

Abstract: Disclosed is a tri-gate field effect transistor with a back gate and the associated methods of forming the transistor. Specifically, a back gate is incorporated into a lower portion of a fin. A tri-gate structure is formed on the fin and is electrically isolated from the back gate. The back gate can be used to control the threshold voltage of the FET. In one embodiment the back gate extends to an n-well in a p-type silicon substrate. A contact to the n-well allows electrical voltage to be applied to the back gate. A diode created between the n-well and p-substrate isolates the current flowing through the n-well from other devices on the substrate so that the back gate can be independently biased. In another embodiment the back gate extends to n-type polysilicon layer on an insulator layer on a p-type silicon substrate. A contact to the n-type polysilicon layer allows electrical voltage to be applied to the back gate.

Abstract: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.

Abstract: The invention includes methods of forming conductive metal silicides by reaction of metal with silicon. In one implementation, such a method includes providing a semiconductor substrate comprising an exposed elemental silicon containing surface. At least one of a crystalline form TiN, WN, elemental form W, or SiC comprising layer is deposited onto the exposed elemental silicon containing surface to a thickness no greater than 50 Angstroms. Such layer is exposed to plasma and a conductive reaction layer including at least one of an elemental metal or metal rich silicide is deposited onto the plasma exposed layer.

Abstract: A semiconductor device has a diffusion barrier formed between a doped glass layer and surface structures formed on a substrate. The diffusion barrier includes alumina and optionally a nitride, and has a layer thickness satisfying the high aspect ratio of the gaps between the surface structures, while adequately preventing dopants in doped glass layer from diffusing out of the doped glass layer to the surface structures and the substrate. Further, heavy water can be used during the formation of the alumina so that deuterium may be accomplished near the interface of surface structures and the substrate to enhance the performance of the device.

Abstract: A semiconductor integrated circuit device is provided, which involves inhibiting a pattern change in the node interconnect and an increase of number of manufacturing process, when the capacitor is additionally installed in the SRAM, while providing higher reliability in the node interconnect. There is provided a semiconductor integrated circuit device, comprising: a node interconnect (lower capacitance electrode), being embedded in a trench formed in an interlayer insulating film provided on a semiconductor substrate, a surface of said lower capacitance electrode being formed to be substantially coplanar to a surface of the interlayer insulating film; and a capacitor, including: a capacitance insulating film, being flatly formed on a surface of the interlayer insulating film; and an upper capacitance electrode, being flatly formed thereon.

Abstract: An interlayer insulation film is etched to form contact holes in an integrated circuit part. At this time, a trench is not formed in a guard ring part. Subsequently, ion implantation is carried out in source/drain regions in a peripheral circuit part for contact compensation, and high-temperature annealing is carried out in order to activate implanted impurities. Subsequently, an interlayer insulation film, a storage capacitor, and another interlayer insulation film are formed in sequence. Then, contact holes reaching a part of wiring layers are formed in the peripheral circuit part while, in the guard ring part, a trench reaching a diffusion layer is formed. Next, a barrier metal film is formed in each of the contact holes and the trench, and further, a contact plug comprising, for example, a W film is buried therein.

Abstract: A structure relating to removal of an oxide of titanium generated as a byproduct of a process that forms cobalt disilicide within an insulated-gate field effect transistor (FET). The structure may comprise a layer of cobalt disilicide that is substantially free of cobalt monosilicide, with substantially no stringer of an oxide of titanium on the layer of cobalt disilicide. The structure may alternatively comprise a layer of cobalt disilicide, a patch of an oxide of titanium, and a reagent in contact with the patch at a temperature and for a period of time. The layer is substantially free of cobalt monosilicide. The patch is on the layer of cobalt disilicide. The reagent is adapted to remove the patch within the period of time. The reagent does not chemically react with the layer of cobalt disilicide, and the reagent comprises water, ammonium hydroxide, and hydrogen peroxide.

Abstract: An object of the present invention is to realize a semiconductor device having a high TFT characteristic. In manufacturing an active matrix display device, electric resistivity of the electrode material is kept low by preventing penetration of oxygen ion into the electrode in doping of an impurity ion. A display device having a low electric resistivity can be obtained.

Abstract: A method for improving productivity when manufacturing a semiconductor device. A lower electrode, insulating films, an upper electrode and insulating films are formed on a semiconductor substrate in a sensor region. A cavity is formed between the insulator films above the lower electrode. The lower electrode, insulating film, the cavity and insulating film, and an upper electrode form a variable capacity sensor. The cavity is formed by etching a sacrificial pattern between the insulation films by way of a hole formed in a pair of insulation films. Other than in the above sensor region, a dummy lower electrode and four insulating films are formed on the TEG region on the semiconductor substrate; and a dummy cavity is formed between a pair of insulation films above the lower electrode however no conductive layer on the same layer as the upper electrode is formed on the dummy cavity.

Abstract: A method for fabricating a MEMS device having a fixing part fixed to a substrate, a connecting part, a driving part, a driving electrode, and contact parts, includes patterning the driving electrode on the substrate; forming an insulation layer on the substrate; patterning the insulation layer and etching a fixing region and a contact region of the insulation layer; forming a metal layer over the substrate; planarizing the metal layer until the insulation layer is exposed; forming a sacrificial layer on the substrate; patterning the sacrificial layer to form an opening exposing a portion of the insulation layer and the metal layer in the fixing region; forming a MEMS structure layer on the sacrificial layer to partially fill the opening, thereby forming sidewalls therein; and selectively removing a portion of the sacrificial layer by etching so that a portion of the sacrificial layer remains in the fixing region.

Abstract: The present invention seeks to reduce the amount of current required for a write operation by using a process for forming the read conductor within a recessed write conductor, the write conductor itself formed within a trench of an insulating layer. The present invention protects the MTJ from the voltages created by the write conductor by isolating the write conductor and enabling the reduction of current necessary to write a bit of information.

Abstract: A magnetic memory device includes a magnetoresistive element and a first wiring layer. The magnetoresistive element includes a fixed layer, a recording layer, and a non-magnetic layer interposed therebetween. The first wiring layer extends in a first direction and generates a magnetic field for recording data in the magnetoresistive element. The recording layer includes a base portion extending in a second direction rotated from the first direction by an angle falling within a range of more than 0° to not more than 20°, and first and second projections projecting from the first and second sides of the base portion in a third direction perpendicular to the second direction. The third and fourth sides of the base portion are inclined with respect to the third direction in the same rotational direction as a rotational direction in which the second direction is rotated.

Abstract: The present invention provides a thin-film structure that includes an etch-stop layer having a first side and a second side, a patterned compensation layer for dissipating thermal energy, and an etch-vulnerable layer, where the etch-stop layer substantially impedes etching. The patterned compensation layer is adjacent the first side of the etch-stop layer, and the etch-vulnerable layer is adjacent the second side of the etch-stop layer.

Abstract: A phototransistor includes a first-conduction-type lower region, a second-conduction-type upper region disposed on the first region, a second-conduction-type electrode contact region of a high concentration disposed at a surface inside of the upper region and is connected to an electrode so as to transmit a signal, a first-conduction-type first shield region of a high concentration disposed at the surface of the upper region and spaced at an interval from the electrode contact region and connected to a ground potential, and a first-conduction-type second shield region of a low concentration disposed between the electrode contact region and the first shield region at the surface of the upper region so as to surround the electrode contact region, and further, is connected to the ground potential.

Abstract: In one embodiment, a semiconductor device is formed having charge compensation trenches in proximity to channel regions of the device. The charge compensation trenches comprise at least two opposite conductivity type semiconductor layers. A channel connecting region electrically couples the channel region to one of the at least two opposite conductivity type semiconductor layers.

Abstract: The invention provides a semiconductor integrated circuit device with improved designing efficiency while achieving higher functions. An inner circuit is surrounded by a plurality of cells in which a first switch element for connecting a power supply voltage line or a ground voltage supply line to a power supply line of an internal circuit is disposed below power supply lines extending in a first and second directions, and the power lines are connected together.

Abstract: Crossing trenches of different depths may be formed in the same semiconductor structure by etching the deeper trench first. The deeper trench and the substrate may then be covered with a material that prevents further etching. The covering is etched through for the shallower trench, leaving a protective covering in the deeper trench.

Abstract: An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as, tensile stress-inducing and compressive stress-inducing, dielectric materials, and further includes altering the depth of the isolation structure and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i.e., to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device.

Abstract: An electronic assembly (98) includes a substrate (20), a capacitor having first and second conductors (38,54) formed over the substrate, a first set of conductive members (76) formed over the substrate and being electrically connected to the first conductor of the capacitor, and a second set of conductive members (78) formed over the substrate and being electrically connected to the second conductor of the capacitor.

Abstract: A complementary metal-oxide-semiconductor field effect transistor (CMOSFET) is provided. The CMOSFET includes a substrate of a first conductivity type, a first epitaxial layer, a well, a second epitaxial layer of a second conductivity type, a first sinker, a second sinker, a first buried layer and a second buried layer. The first and the second epitaxial layer are sequentially disposed on the substrate. The first sinker and the first buried layer separate a first region from the second epitaxial layer. The second sinker and the second buried layer separate a second region from the second epitaxial layer. The well is disposed in the first region. A first transistor is disposed in the well. A second transistor is disposed in the second region. A deep trench isolation is disposed between the first and the second region and extends from the substrate to the upper surface of the second epitaxial layer.

Abstract: A power semiconductor device has an active region that includes a drift region. At least a portion of the drift region is provided in a membrane which has opposed top and bottom surfaces. In one embodiment, the top surface of the membrane has electrical terminals connected directly or indirectly thereto to allow a voltage to be applied laterally across the drift region. In another embodiment, at least one electrical terminal is connected directly or indirectly to the top surface and at least one electrical terminal is connected directly or indirectly to the bottom surface to allow a voltage to be applied vertically across the drift region. In each of these embodiments, the bottom surface of the membrane does not have a semiconductor substrate positioned adjacent thereto.

Abstract: In an independent GaN film manufactured by creating a GaN layer on a base heterosubstrate using vapor-phase deposition and then removing the base substrate, owing to layer-base discrepancy in thermal expansion coefficient and lattice constant, bow will be a large ±40 ?m to ±100 ?m. Since with that bow device fabrication by photolithography is challenging, reducing the bow to +30 ?m to ?20 ?m is the goal. The surface deflected concavely is ground to impart to it a damaged layer that has a stretching effect, making the surface become convex. The damaged layer on the surface having become convex is removed by etching, which curtails the bow. Alternatively, the convex surface on the side opposite the surface having become convex is ground to generate a damaged layer. With the concave surface having become convex due to the damaged layer, suitably etching off the damaged layer curtails the bow.

Abstract: The present invention has been made in order to manufacture a silicon semiconductor substrate used for a semiconductor integrated circuit device, higher in carrier mobility, especially in electron mobility, which is a carrier of an n-type FET, on a {100} plane as a main surface, and provides a silicon semiconductor substrate and a method for manufacturing the same, wherein the conventional RCA cleaning is employed without the use of special cleaning and the surface of the substrate is planarized at an atomic level to thereby decrease the surface roughness thereof without the use of the radical oxidation. The present invention provides a silicon semiconductor substrate comprising: a {110} plane or a plane inclined from a {110} plane as a main surface of the substrate; and steps arranged at an atomic level along a <110> orientation on the main surface.

Abstract: It is an object to provide an insulating film having a very low dielectric constant and a great mechanical strength. Moreover, it is another object to provide a semiconductor device capable of reducing both a capacity between wiring layers and a capacity between wirings also in microfabrication and an increase in integration in the semiconductor device. In order to attain the objects, there is provided an inorganic insulating film comprising a porous structure having a skeletal structure in which a vacancy is arranged periodically and a large number of small holes are included.

Abstract: A photosensitive device having at least an insulator layer including a plurality of photoreceiving regions disposed on a substrate. A plurality of conductive patterns is disposed on the insulator layer without covering the photoreceiving regions. A flattened dielectric layer is disposed on the conductive patterns and the insulator layer, wherein a surface of the dielectric layer is higher than a surface of the conductive patterns in a range between 2000 ? to 4000 ?.

Abstract: A shield wiring is provided on a boundary of a target region to be shielded of macros, an inner side of the boundary, an outer side of the boundary, or an inner side and an outer side of the boundary, each being as a black box, so as to surround the target region. This shield wiring is electrically connected to a power supply terminal or a power supply wiring of the macros or the like, or to a power supply wiring on another wiring layer through a contact section, thereby fixing a potential of the shield wiring. An accurate delay value is then obtained by estimating an influence of crosstalk between a wiring in a region where the physical wiring pattern is clear and the shield wiring and also estimating a capacitance produced between the wirings.

Abstract: The present invention provides a package device for reducing the electromagnetic/radio frequency interference, which includes a first substrate with a shielding structure on the under surface of the first substrate, and an insulating layer on the shielding structure. The first substrate includes a through hole that is filled with the conductor therein. A plurality of lead-frames located on the bottom surface of the first substrate. A second substrate located above between the two lead-frames. Then, the molding compound encapsulated to cover the above structures to form a package device. Therefore, the shielding path of the package device is constructed of the plurality of lead-frames, the conductor within the first substrate, the shielding structure, and the grounded to discharge the electromagnetic/radio frequency out of the package device, thus, the electromagnetic/radio frequency interference for the package device can be reduced.

Abstract: An example of a circuit structure may include a first dielectric layer having first and second surfaces, and a channel extending at least partially between the first and second surfaces and along a length of the first dielectric layer. First and second conductive layers may be disposed on respective portions of the first and second surfaces. A first conductor, having an end, may be disposed on a surface of the first dielectric layer, including at least a first portion extending around at least a portion of the conductor end. The second conductive layer may line the channel extending around a portion of the conductor end. Some examples may include a stripline having a second conductor connected to the first conductor. Some examples may include a cover having a wall positioned on the first dielectric over the second conductor.

Abstract: The central region of a leadframe (101, 201, 301, 401, 501, 601, 701, 801, 901, 1001, 1101, 1201), is selectively etched to leave upright portions (104, 204, 304, 404, 504, 604, 704, 804, 904, 1004, 1104, 1204). Subsequently, during the packaging process, an integrated circuit (3) is located on the central region of the leadframe, and wires (107) are formed between the upright portions of the leadframe and contacts (5) of the integrated circuit (3), which are to be grounded. Subsequently, the wires and upright portions of the leadframe are encased in resin (116). Since the upright portions of the leadframe are encased in resin, the resin (116) is mechanically locked to the leadframe. Furthermore, any delamination that occurs between the resin (116) and the leadframe cannot propagate easily up the sides of the upright portions as far as the wires (107), so the wires (107) are unlikely to be torn from the upright portions (104, 204, 304, 404, 504, 604, 704, 804, 904, 1004, 1104, 1204).

Abstract: Die-down array integrated circuit (IC) device packages with enhanced thermal, electrical, and input/output properties are presented. A die-down array IC device package includes a heat spreader having a central cavity. A first substrate surface is coupled to the heat spreader. A central opening through the substrate overlaps the central cavity. Alternatively, the heat spreader is formed by coupling a ring-shaped body to a planar heat spreader. The first substrate surface is coupled to the ring-shaped body and the substrate central opening overlaps a central opening through the ring-shaped body. An array of electrically conductive terminals is coupled to a second substrate surface. An IC die is mounted to the heat spreader within the central cavity. Bond pads on the die are coupled to corresponding bond pads on the substrate with a plurality of wire bonds. Electrically conductive bumps on the die are coupled to corresponding bond pads on an interposer.

Abstract: An LSI package encompasses a transmission line header embracing a header-base, a transmission line held by the header-base, and an interface IC chip mounted on the header-base, an interposer substrate having a plurality of board-connecting joints, which facilitate connection with the printed wiring board; an LSI chip mounted on the interposer substrate; and a receptacle having a lead terminal and being mounted on the interposer substrate, configured to accommodate the transmission line header so that the interface IC chip electrically connects to the LSI chip through the lead terminal.

Abstract: An interconnect system between an integrated circuit device and a printed circuit board may include a filter between the integrated circuit device and the power subsystem of the printed circuit board. The filter may be a low-pass filter that reduces current in a higher frequency range without negatively modifying current in a lower frequency range and may reduce radiated emissions produced during operation of the integrated circuit. The filter may be implemented by arranging core-power voltage conductors and ground conductors at a first or second level interconnect into one or more voltage groupings and one or more adjacent ground groupings such that series inductance is increased. In some embodiments, the first level interconnect may include conductive bumps or pads between an integrated circuit and a substrate. In some embodiments, the second level interconnect may include solder balls, pins, pads, or other conductors of a package, socket, or interposer.

Abstract: A storage apparatus 10 is disclosed, that comprises a wiring substrate 11 having a first surface and a second surface, a flat type external connection terminal 12a disposed on the first surface of the wiring substrate 11, a semiconductor device 14 disposed on the second surface of the wiring substrate 11 and having a connection terminal 14a connected to the flat type external connection terminal 12a, a molding resin 15 for coating the semiconductor device 14 on the second surface of the wiring substrate 11, a card type supporting frame 10a having a concave portion or a hole portion fitting the wiring substrate 11, the semiconductor device 14, and the molding resin 15 in such a manner that the flat type external connection terminal 12a is exposed to the first surface of the wiring substrate 11, and adhesive resin a adhering integrally the flat type external connection terminal 12a, the wiring substrate 11, the semiconductor device 14, the molding resin 15, and the card type supporting frame 10a.

Abstract: A stacked semiconductor chip package comprising a first semiconductor chip having an upper surface, a lower surface opposed to said upper surface, and a plurality of conductive metal lines formed on said upper surface of said first semiconductor chip; a plurality of metal elements each having a first arm portion located on said upper surface of said first semiconductor chip and connected electrically to a corresponding one of said metal lines, a second arm portion located on said lower surface of said first semiconductor chip; and a second semiconductor chip having a lower surface and a plurality of conductive bumps provided on said lower surface, and mounted on said upper surface of said first semiconductor chip in such a manner that said solder bumps of said second semiconductor chip is electrically connected to said corresponding conductive metal lines on said upper surface of said first semiconductor chip.

Abstract: An inventive electronic device, such as a multi-chip module (MCM), a Single In-line Memory Module (SIMM), or a Dual In-line Memory Module (DIMM), includes a base, such as a printed circuit board, having a surface on which flip-chip pads and wire-bondable pads are provided. The flip-chip pads define an area on the surface of the base at least partially bounded by the wire-bondable pads. A first integrated circuit (IC) die is flip-chip bonded to the flip-chip pads, and a second IC die is back-side attached to the first IC die and then wire-bonded to the wire-bondable pads. As a result, the flip-chip mounted first IC die is stacked with the second IC die in a simple, novel manner.

Abstract: The present invention discloses a staggered finger configuration comprising a plurality of first and second conducting wires alternately arranged on the substrate, wherein each of the first conducting wire connecting an inner and an outer fingers and each of the second conducting wire connecting an intermediate finger between the inner and the outer fingers, thereby forming a staggered configuration.

Abstract: A frame-shaped sidewall is provided on a metallic base plate surrounding a semiconductor element arranged on the metallic base plate, a first dielectric plate is arranged on one side of the semiconductor element and a first circuit pattern is formed on its surface, a second dielectric plate is arranged on another side of the semiconductor element and a second circuit pattern is formed and the first and the second dielectric plate. Power supply portions are provided on a part of the sidewall, through which a first or a second band-shaped conductors is penetrating. Third dielectric plates are arranged on the base plate between the band-shaped conductors and the first dielectric plate or the second dielectric plate, having a line conductor pattern formed on their surfaces. The surfaces of the third dielectric plate are arranged at a position lower than the band-shaped conductor and higher than the surface of the first or the second dielectric plate with respect to a main surface of the base plate.

Abstract: A process for fabricating an integrated circuit package includes: selectively etching a leadframe strip to define a die attach pad and at least one row of contact pads; mounting a semiconductor die to one side of the leadframe strip, on the die attach pad; wire bonding the semiconductor die to ones of the contact pads; releasably clamping the leadframe strip in a mold by releasably clamping the contact pads; molding in a molding compound to cover the semiconductor die, the wire bonds and a portion of the contact pads not covered by the clamping; releasing the leadframe strip from the mold; depositing a plurality of external contacts on the one side of the leadframe strip, on the contact pads, such that the external contacts protrude from the molding compound; mounting at least one of an active and a passive component to a second side of said leadframe strip; and singulating to provide the integrated circuit package.

Abstract: An integrated circuit chip is provided, the integrated circuit chip having: a base portion, the base portion having a peripheral wall forming an elevated perimeter depending away from a surface of the base potion; a plurality of extensions extending away from the surface, a periphery of each of the plurality of extensions being spaced away from the peripheral wall, the plurality of extensions further comprising a first group of extensions and a second group of extensions, each of the first group of extensions having a greater peripheral area than a peripheral area of each of the second group of extensions and the first group of extensions being aligned with a portion of an integrated circuit disposed on another surface of the base, the portion of the integrated circuit generating a higher heat flux than other portions of the integrated circuit, and a plate secured to the elevated perimeter, the plate the plate covering the plurality of extensions and further comprising an inlet opening and an outlet opening.

Abstract: An electrical component has electrically conducting structures placed on an electrically isolating or semiconductive substrate and component structures sensitive to a voltage or an electrical arcing and galvanically separated from one another. To prevent an arcing between the galvanically separated component structures, the component structures are short-circuited with a shunt line having a smaller cross-section than the remaining electrical conductor tracks. The shunt lines can be burnt through by application of an electrical current at any given time, whereby a galvanic separation of the component structures is effected, if necessary, for the function of the component.

Abstract: A memory card comprising a substrate, a memory die on top of the memory die, a controller die on top of the memory die; and a interposer surrounding the controller die and on top of the memory die wherein the interposer allows for wire bonding to the substrate to be minimized. A system and method in accordance with the present invention achieves the following objectives: (1) increase the density of the Flash card by reducing the number of wire bond pads on the substrate and enabling insertion of the largest die possible that can fit inside a given card interior boundary; (2) more efficiently stacks Flash memory dies when stacking is necessary, to increase density of the Flash card; (3) has only a few necessary signal I/O bonding wires to the substrate to improve production yield.

Abstract: A Flash memory card is disclosed comprising a substrate, a Flash memory die on top of the substrate, a controller die on top of the Flash memory die, and an interposer coupled to with the controller die and on top of the Flash memory die wherein the interposer results in substantial reduced wire bonding to the substrate. The interposer can surround or be placed side by side with the controller die. A system and method in accordance with the present invention achieves the following objectives: (1) takes advantage of as large of a Flash memory die as possible, to increase the density of the Flash card by reducing the number of wire bond pads on the substrate and enabling insertion of the largest die possible that can fit inside a given card interior boundary; (2) more efficiently stacks Flash memory dies to increase density of the Flash card; and (3) has a substantially less number of bonding wires to the substrate as possible, to improve production yield.

Abstract: A display device includes a display panel, and the circuit substrate is separately formed and positioned different from the array substrate of the display panel and connected to the display panel. The circuit substrate includes an insulating substrate, a conductive layer, an insulating layer to cover a part of the conductive layer, a plating layer applied to a portion of the conductive layer which is exposed from the insulating layer due to misalignment between the conductive layer and the insulating layer, and a misalignment detection pattern for detecting the misalignment between the conductive layer and the insulating layer. The misalignment detection pattern has a pattern covered by the insulating layer in a manner to prevent adherence of a plating material to the conductive layer, if the misalignment between the conductive layer and the insulating layer is smaller than a predetermined misalignment tolerance.

Abstract: A circuit board has a metal pattern that is formed on a surface of the circuit board to be connected with bumps in two-dimensional arrangement for mounting an electronic device that has the bumps. A plurality of the bumps which has even electrical potentials is electrically connected by the metal pattern on the surface of the circuit pattern.

Abstract: A method, system, and apparatus, the apparatus including a metal layer on silicon, photo-resist material disposed on the metal layer, a bump pad reservoir adjacent to the metal layer, a quantity of interconnect metal disposed in the bump pad reservoir, and a resist opening in resist material disposed on a surface of the bump metal and adjacent the interconnect metal. The resist opening may be wider at an open end thereof than at an end in contact with the interconnect metal.

Abstract: Microfeature devices, microfeature workpieces, and methods for manufacturing microfeature devices and microfeature workpieces are disclosed herein. The microfeature workpieces have an integrated circuit, a surface, and a plurality of interconnect elements projecting from the surface and arranged in arrays on the surface. In one embodiment, a method includes forming a coating on the interconnect elements of the microfeature workpiece, producing a layer over the surface of the microfeature workpiece after forming the coating, and removing the coating from at least a portion of the individual interconnect elements. The coating has a surface tension less than a surface tension of the interconnect elements to reduce the extent to which the material in the layer wicks up the interconnect elements and produces a fillet at the base of the individual interconnect elements.

Abstract: A source/drain electrode is used in a thin-film transistor substrate containing a substrate, a thin-film transistor semiconductor layer, source/drain electrodes, and a transparent picture electrode. The source/drain electrode includes a nitrogen-containing layer and a thin film of pure aluminum or an aluminum alloy. Nitrogen of the nitrogen-containing layer binds to silicon of the thin-film transistor semiconductor layer, and the thin film of pure aluminum or aluminum alloy is connected to the thin-film transistor semiconductor layer through the nitrogen-containing layer.

Abstract: Disclosed are a method of manufacturing a semiconductor device and a structure of a semiconductor device. A method of forming a passivation film of a semiconductor device comprises the steps of forming metal wires on a semiconductor substrate, forming a buffer oxide film being a first passivation film on the metal wires, wherein the buffer oxide film can mitigate damage by plasma, forming a high density plasma film being a second passivation film on the buffer oxide film, and forming a third passivation film on the second passivation film. According to the present invention, it is possible to significantly reduce the leakage current between a select source line and a common source line.