Abstract: According to this invention a battery testing device is provided. Such device activates a shortening between the battery poles using a predefined electronic circuit (in order to maximize the battery's energy potential) for a time period of 10-50 ?sec. In a subsequent time period of ˜100-200 ?sec, the loading is slowly decreased until the voltage returns to an open circuit voltage UOC. During the testing process, the voltage and the battery current are measured. The measurements are stored at the device database, to be later used in an algorithm for checking battery conditions.

Abstract: Systems and methods for reducing electrostatic platform noise in electric-field sensors due to various self-charging and discharging processes are provided. A representative method includes: identifying avoidance regions of an electrostatically-floating sensor platform that have a propensity for self-induced charging and discharging; locating a first electrode and a second electrode on the electrostatically-floating sensor platform, wherein the first electrode and the second electrode are positioned and dimensioned to receive substantially equal amounts of distributed charge via self-charging; and obtaining a differential signal from these two electrodes that is proportional to an external ambient E-field of interest, while at the same time nulling out the common-mode signal that results from sensor platform self-charging and/or discharging.

Abstract: A technique for reducing a parasitic DC bias voltage on a sensor monitors the parasitic DC bias voltage on a first element of the sensor. A controlled bias voltage that is applied between the first element of the sensor and a second element of the sensor is then modified to substantially maintain the parasitic DC bias voltage at a desired potential.

Abstract: A circuit breaker detects a loose electrical connection condition of a power circuit. The circuit breaker includes first and second lugs, first and second acoustic couplers acoustically coupled to the power circuit, separable contacts electrically connected in series between the first and second lugs, and an operating mechanism adapted to open and close the contacts. An acoustic generator is coupled to the second acoustic coupler and generates a first acoustic signal to the power circuit from the second acoustic coupler. An acoustic sensor is coupled to the first acoustic coupler and has a second acoustic signal which is operatively associated with the loose electrical connection condition. The acoustic sensor outputs a sensed acoustic signal. A circuit cooperates with the acoustic generator to generate the first acoustic signal, input the sensed acoustic signal, and detect the loose electrical connection condition therefrom.

Abstract: A system, apparatus, and method (10) for detecting an electrical short condition in a dynamoelectric machine are described. The method includes determining an operating parameter of a dynamoelectric machine (14) responsive to at least one output signal of the dynamoelectric machine and providing a transfer function (16) for predicting a field current of dynamoelectric machine. The method also includes obtaining a value for a predicted field current (18) of the dynamoelectric machine from the transfer function and the operating parameter and identifying a shorted turn condition of the dynamoelectric machine responsive to a difference between the value of the predicted field current and a value of an actual field current of the dynamoelectric machine (24).

Abstract: Methods and apparatus establish and maintain reliable network cable contacts that mitigate disconnecting effects by transmitting an AC signal with a frequency that reduces the disconnecting effects. The signal frequency may be statically or dynamically selected. The approach allows the severity of a disconnecting effect to be assessed and/or monitored and may support the scheduled replacement and/or repair of network cables identified as faulty. Information related to network cable resistance may be managed within the local device and/or with assistance from a Network Management System (NMS). Physical connection reliability and resilience against disconnecting effects is further enhanced with a physical pogo-style connector that rotates to mechanically scrape and remove oxidation and debris from a conductive contact pad surface each time a physical contact is formed. Such a contact may significantly reduce the level of oxidation, oils and other debris that contribute to the disconnecting effect.

Abstract: A current measurement circuit to measure the output of a power supply transformer includes a simulation capacitor having a capacitance proportional to a parasitic capacitance of the transformer. The first electrode of the capacitor is coupled to an output winding of the transformer and the second electrode is coupled to a first node, with a second sense resistor coupled between the first node and ground so that current flowing through the simulation capacitor flows through the second sense resistor. Current flowing through a first sense resistor coupled to a second node and to ground has a component representative of the output current of the power supply and a component representative of the parasitic current. A differential amplifier coupled at an inverting input to the first node and at a non-inverting input to the second node generates an output signal that is proportional to the output current of the power supply.

Abstract: A test system includes a circuit assembly having an IC and an external circuit. The IC includes test circuitry used to observe data indicative of target resistances in the external circuit. The test system evaluates the data to determine target resistance values. A first embodiment measures two output voltages responsive to a time varying reference voltage. The two output voltages can be used to determine resistance values in the external circuit. A second embodiment enables logic contention on the IC, controllably fixes a pull-down element on the IC, and controllably sweeps a pull-up element on the IC until the voltage at a node between the pull-down and pull-up elements and coupled to an external circuit exceeds a reference voltage.

Abstract: This invention provides a solar simulator measurement method capable of high-accuracy measurements with fast-response photovoltaic devices as well as with slow-response photovoltaic devices, and a solar simulator for implementing the method. A flash having a pulse waveform with a flattened peak is generated from a xenon lamp. The flash is sensed by an irradiance detector, its irradiance measured, and the irradiance of the light source is adjusted to fall within a prescribed narrow range based on the detected irradiance value. Then, the flash with irradiance within the prescribed range irradiates photovoltaic devices under measurement, and the current and the voltage output by the photovoltaic devices are measured at multiple points while a load of the photovoltaic devices is controlled. This process is repeated with multiple flashes to obtain an I-V curve for the photovoltaic devices.

Abstract: In one embodiment, an integrated circuit includes at least one digital leakage detector that includes digital circuitry configured to detect an approximation of a magnitude of the leakage current in transistors of the integrated circuit and configured to generate a digital output representing the approximated magnitude. In another embodiment, a leak detector includes leak circuits and clocked storage devices. Each leak circuit is configured to generate an output signal indicative of a different magnitude of leakage current in a transistor. The clocked storage devices are configured to capture a state representing the output signals of the leak circuits. In another embodiment, a method includes running a test for leakage current in a digital leakage detector, wherein a digital output of the digital leakage detector represents a magnitude of a leakage current being experienced by the integrated circuit during use; and outputting the digital output from the integrated circuit.

Abstract: An LCD test device and a test process thereof are disclosed, in which a defect of an LCD panel is exactly identified through exact electrical connection between an LCD panel and a probe unit. The LCD test device includes a work table on which an LCD panel is mounted, a clamping unit on the work table, clamping a top surface of an edge of the LCD panel mounted on the work table, a probe unit electrically connected with a pad of the LCD panel fixed to the work table by the clamping unit, and a back light unit supplying light to the LCD panel fixed to the work table. Accordingly, since the defect of the LCD panel can be tested exactly, reliability of the test is improved, and it is possible to prevent yield and the cost from being reduced in advance.

Abstract: Methods and systems for hardening a clocked latch against single event effects are disclosed. A system includes a first three-input OR gate, a first NAND gate, a second three-input OR gate, and a second NAND gate. The first three-input OR gate receives as inputs a clock signal, a first signal, and a redundant first signal. An output of the first three-input OR gate is connected to an input of the first NAND gate. The second three-input OR gate receives as inputs the clock signal, a second signal, and a redundant second signal. An output of the second three-input OR gate is connected to an input of the second NAND gate. A first output signal of the first NAND gate is connected to another input of the second NAND gate and a second output signal of the second NAND gate is connected to another input of the first NAND gate.

Abstract: A semiconductor integrated circuit including: N modules set in their functions in accordance with input function setting data, a circuit block having R number of I/O parts, and a module selection part for selecting R number of modules from among the N number of modules connecting the selected R number of modules and R number of I/O parts of the circuit block and connecting one module selected from among at least two modules to each of the R number of I/O parts. Each of the R number of I/O parts has a data holding part for holding a function setting data and inputting the held function setting data to the destination module, and N modules are able to replace functions of each other when the input function setting data are the same.

Abstract: The disclosed invention is intended to decrease the power consumption of a pulse latch circuit. A pulse latch circuit that operates in sync with a pulsed clock signal, including a first operation mode in which shifting test pattern scan data is performed and a second operation mode in which shifting the test pattern scan data is not performed, comprises the following circuits: a first latch circuit that is able to latch input data in sync with the clock signal; a second latch circuit that is connected to the first latch circuit and is able to latch the test pattern scan data to be shifted in sync with the clock signal; and a control circuit that stops supply of the clock signal to the second latch circuit during the second operation mode. By thus stopping the supply of the clock signal to the second latch circuit, decrease the power consumption is achieved.

Abstract: Circuits and related methods are provided for buffering reference voltages from noise associated with output driver transistors. In one example, an output driver buffer circuit includes an output driver transistor adapted to adjust an output voltage of an output pad. The circuit also includes a pre-driver circuit connected to a gate of the output driver transistor. The pre-driver circuit is adapted to receive a reference voltage to control the output driver transistor. The pre-driver circuit includes a precharged capacitor, a first switch adapted to connect the capacitor to the gate, and a second switch adapted to connect the reference voltage to the gate. The second switch is adapted to operate following a time period after the capacitor is connected to the gate. The capacitor is adapted to buffer noise associated with the output driver transistor during the time period.

Abstract: Embodiments of methods, apparatuses, systems and/or devices associated with a bus termination scheme are disclosed.

Abstract: A data bus circuit connects a south bridge driven by a first voltage and a bay driven by a second voltage. The first voltage and the second voltage are different. The data bus circuit includes a data bus that electrically connects the south bridge and the bay, and a Thevenin termination circuit that is arranged on the data bus at a point. The Thevenin termination circuit maintains a voltage at the point substantially equal to the first voltage.

Abstract: Systems and methods are disclosed herein to provide improved techniques for loading of configuration memory cells in integrated circuits, such as programmable logic devices. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a non-volatile memory adapted to store a first bit, a second bit, and a plurality of configuration data; a plurality of configuration memory cells; and control logic adapted to determine based on values of the first and second bits whether to load the configuration data from the non-volatile memory into the configuration memory cells.

Abstract: The states associated with a programmable state machine are reordered to compress the storage of transitions which define the state machine. To reorder the states, a score is computed and assigned to each of the states. Next, the states are sorted according to their computed scores. In some embodiments, to compute the score for each current state based on the received input symbol, the number of times that the input symbol causes transition to similar states is added. The sum of the scores in each row of the table is representative of the score for the associated current state associated with that row. The states are sorted according to their score and a new state transition table is generated in accordance with the reordered states.

Abstract: Systems and methods are disclosed herein to provide improved I/O techniques. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a reference circuit adapted to receive a first reference signal and provide a second plurality of reference signals based on the first reference signal, with the reference circuit providing default voltage levels for the second plurality of reference signals if a first control signal is asserted. An input/output circuit, coupled to the reference circuit and to an output driver, receives the second plurality of reference signals to control the output driver to provide an output signal, with the output driver operated with the default voltage levels if the first control signal is asserted.

Abstract: An input integrating circuit and a differential amplifier circuit are provided in a receiver circuit which samples a pair of differential input signals, detects the levels of said pair of input signals, and latches the detected levels. The above-mentioned input integrating circuit further includes: a pair of input transistors receiving the pair of input signals at respective gates thereof; a switch transistor becoming conducting in response to a sampling clock in a sampling period so as to supply a discharge current to a common source terminal of the pair of input transistors; and a precharge circuit precharging drain terminals of the pair of input transistors in a precharge period. The input integrating circuit discharges the capacitor of the drain terminals by the discharge current in the sampling period succeeding the precharge period. The differential amplifier circuit amplifies the drain terminals of the input integrating circuit.

Abstract: A first pair of single-ended drivers, each having a respective output connected to a first line of a differential channel, are defined to work against each other with respect to driving a first signal on the first line of the differential channel. A second pair of single-ended drivers, each having a respective output connected to a second line of the differential channel, are defined to work against each other with respect to driving a second signal on the second line of the differential channel. Each of the first pair of single-ended drivers and each of the second pair of single-ended drivers is connected to receive a common input signal. A difference between the first signal on the first line of the differential channel and the second signal on the second line of the differential channel defines a differential signal that is representative of the common input signal.

Abstract: A high speed serial data communication system includes provisions for the correction of equalization errors, particularly those errors introduced by equalizer non-idealities. The equalization is achieved at the data transmitter, and is based on dynamic current subtraction at the output of a differential pair. When bit time>0, the error current is removed or subtracted from the total driver current, thereby maintaining a constant total current from bit time 0 to bit time>0. The same result can also be achieved by subtracting current when bit time>0 using field effect transistors of the opposite gender. The error current can be determined empirically from simulation or through feedback using a replica of the driver. The circuits for achieving equalization error correction and the resulting electrical network analysis are shown and described.

Abstract: Logic activation circuit for switching a logic circuit having at least one supply voltage line on or off, said logic activation circuit having: (a) at least one voltage supply switching device for connecting a supply voltage to a supply voltage line of the logic circuit in a manner dependent on a changeover control signal that is applied to a control terminal of the voltage supply switching device; and having (b) a charge equalization switching device which, in a manner dependent on a control switching pulse, connects the supply voltage line of the logic circuit to the control terminal of the voltage supply switching device for the duration of the control switching pulse so that charge equalization is effected between the supply voltage line and the control terminal of the voltage supply switching device in order to generate the changeover control signal.

Abstract: Methods and apparatus are disclosed to implement programmable logic generators that provide the advantages of compatible look-up tables (LUTs) while utilizing less silicon real estate and power for the same number of functions. The disclosed methods and apparatus employ programmable switches to emulate memory units that are used in LUTs and illustrate construction of 2- and 3-input LUTs as building blocks of other multi-input LUTs.

Abstract: A method for power consumption reduction in a limited-switch dynamic logic (LSDL) circuit provides reduced power consumption by reducing clock power dissipation. By clocking LSDL gates with a clock signal having a reduced voltage swing in the evaluation phase, the LSDL gates are permitted to operate, while reducing the clock power consumption dramatically. Since clock power consumption dominates in LSDL circuits, the reduction in clock power dissipation results in a significant reduction in overall circuit power consumption. The reduced swing clock is produced at a plurality of local clock buffers by supplying the local clock buffers with an extra power supply rail that is switched onto the clock distribution lines by the local clock buffers in response to the full-swing evaluate phase clock received from the global clock distribution network by the local clock buffers.

Abstract: A phase detector is adapted to receive first and second signals and generate third and fourth signals representative of the difference between the phases of the first and second signals. The phase detector assert the third signal in response to the assertion of the first signal and unasserts the third signal in response to the assertion of the second signal. The phase detector asserts the fourth signal in response to the assertion of the third signal and unasserts the fourth signal in response to unassertion of the first signal. The phase detector may include combinatorial logic gates, thereby to generate the third and fourth signals in response to logic levels of the first and second signals. The phase detector may include sequential logic gates, thereby to generate the third and fourth signals in response to transitions of the first and second signals.

Abstract: A clock input filter uses a first programmable low-pass delay element to filter during a low period of an input clock signal and to output a SET signal. The clock input filter uses a second programmable low-pass delay element to filter during a high period of the input clock signal and to output a RESET signal. A latch is set and reset by the SET and RESET signals. The latch outputs a filtered version of the input signal that has the same approximate duty cycle as the input signal. A pair of gates generates a corresponding pair of duty cycle adjusted versions of the input signal. Output multiplexing circuitry is provided to output either the output of the latch, or an increased duty cycle version of the input signal, or a decreased duty cycle version of the input signal, or an unfiltered version of the input signal.

Abstract: A multisense-adaptive reading circuit is described, which is associated to a sense element of an interleaved DC-DC converter module. The reading circuit comprises at least a first and second current source connected to a first and second terminal of the module, connected in turn to a first and second resistive element, as well as a tracker of a current information coming from the first and second current source. Advantageously according to the invention, the reading circuit also comprises a reading mode detector effective to detect a common mode voltage value and, based on this value, to determine a reading mode being used among possible reading modes to self-adapt the reading circuit to the reading mode being used by providing convenient enabling signals to the first and second current sources and to the tracker. A multisense-self-adaptive reading method being implemented by means of that circuit is also described.

Abstract: A system for clock-switching applied in the field of integrated circuits is described. A phase interpolator converts an input clock signal into a clock_A and a clock_B having a phase difference therebetween and transmitting the clock_A and the clock_B. A switch command unit connected to the phase interpolator receives either the clock_A or the clock_B serving as a triggering signal for triggering the switch command unit to transform an input switching signal into an output switching signal when the output switching signal is located in either a rising or a falling edge. A selecting device connected to the phase interpolator and the switch command unit, selects either clock_A or clock_B according to the output switching signal from the switch command unit to output a clock-switching signal composed of clock_A and clock_B.

Abstract: An analog output buffer circuit for a flat panel display is provided for improving an output signal distortion. The circuit includes a transistor, a current source, an input capacitor, an upper switch, a lower switch, a first switch, a second switch and a third switch. In which, the transistor and the current source are electrically connected in series between a first power supply and a second power supply. The current source provides a compensatory current for the transistor when a leakage current occurs. The upper switch and the first switch are turned on during the first period, and the lower switch and the second switch are turn on during the second period, in which the second period is after the first period. Those switches eliminate the drawback of different voltage levels between the input signal and the output signal obtained from the output buffer circuit inputted by the input signal.

Abstract: Box switches are stacked sharing a common current from power sources. The power sources may be current, voltage or a combination of such sources. In preferred embodiments, the transistor switches in the box switches may be paralleled by different polarity transistors that will act to better balance and make symmetrical the output signals. Capacitors may be used to smooth out residual noise voltage signals.

Abstract: An integrated circuit of an embodiment may comprise synchronous logic, combinational logic, and clock circuitry to clock the synchronous logic through various states dependent on the combinational logic. The synchronous logic may comprise a plurality of master-slave registers. The combinational logic is configured to drive data inputs of the synchronous logic dependent on states established by the master-slave registers. The clock circuitry is configured to clock the master portion of the master-slave registers with a lag rendering of a clock signal and to clock the slave portion of the registers with a lead rendering of the clock signal. In a particular example, the circuitry may define a frequency divider of a complementary CMOS realization.

Abstract: A reset ramp control structure and method is described. A fast ramp down condition of a monitored voltage is detected and used to force the state of system reset. Delay between fast ramp detection and the forcing of system reset is adjustable. Operation is adaptable to include all DC power systems. The reset ramp control structure provides operational protection during fast ramp down conditions when standard reset circuitry may not be operational.

Abstract: A digitally programmable delay circuit comprising a plurality of transistors connected in parallel with each other and to a line carrying a signal having an edge to be delayed. One or more of the transistors are selected by a delay control signal to impose a delay amount to the edge, wherein the delay control signal is based on a desired delay amount and a measure of instantaneous process, voltage and temperature conditions of an integrated circuit in which the plurality of transistors are implemented. A selector circuit is responsive to the delay control signal and converts the delay control signal into one or more transistor selection signals to activate one or more of the plurality of transistors. The plurality of transistors may comprise a first sub-circuit having a plurality of transistors of a first type (e.g., P-type) connected in parallel with each other in a ladder configuration, and a second sub-circuit comprising a plurality of transistors of a second type (e.g.

Abstract: A duty detection circuit includes an integration circuit for receiving an RCLK signal and an FCLK signal that are internal clock signals generated by a DLL circuit, and generating voltage levels in accordance with the duty ratio of these internal clock signals; an amplifier for amplifying the output of the integration circuit; a latch circuit for latching the output of the amplifier; a control circuit for controlling the operation timings of each component; a bias circuit for feeding a BIAS signal to the integration circuit; and a frequency monitor circuit unit for monitoring the frequency of the clock signal. The frequency monitor circuit unit is a circuit component used when the power source is turned on, during resetting, and when other initial settings are performed, and detects the actual frequency of the clock signal and adjusts the amount of charging or discharging of the capacitors C1 through C4 in the integration circuit according to this actual frequency.

Abstract: Apparatus and methods for regulating gate delays of synchronous and asynchronous digital circuits. Thermally-sensitive circuits include, generally, temperature sensitive voltage sources outputting a voltage signal indicative of the temperature of the digital circuit, where the voltage signal reflects non-linear temperature sensitivity above a predetermined threshold temperature, and delay mechanisms receiving said temperature sensitive voltage signal(s) as input and being configured to automatically continuously modulate the speed of signal propagation through the circuit in response to said voltage signal, thereby causing circuit elements within the circuits to switch less frequently and consequently causing the circuit elements to generate less heat with increasing circuit temperature.

Abstract: Generally, the embodiments presented are directed to circuits and methods for triggering an event at a fraction of a clock cycle. A triggering circuit can comprise two or more input circuits that output an event signal. The event signal is received by one of two or more delay circuits that trigger the event signal at a predetermined phase of the clock cycle by moving the event signal from a first clock domain to another clock domain. By triggering the event at a phase division, the triggering circuit outputs signals at a rate faster than the clock cycle.

Abstract: An integrated circuit includes at least three separate power supply terminals, at least one for those portions of the circuit that must accommodate the widest signal-related voltage excursion, at least one for those that experience substantially smaller signal-related voltage excursions, and a common terminal.

Abstract: A circuit for coupling a logic signal from a circuit input to a circuit output includes a parallel connection of a first circuit branch and a second circuit branch, wherein an inverter in the first branch powered as last inverter in this branch via first supply terminals, via which a first supply potential and a second supply potential are supplied, and an inverter in the second branch powered as first inverter in this branch via second supply voltage terminals, via which a second supply potential and a second reference potential are supplied, are adapted to receive the same logic value of the logic signal, wherein outputs of the two circuit branches are connected to each other and coupled to the circuit output. In such a circuit, propagation time differences of rising and falling edges, which may develop by fluctuation of various supply potentials, may be minimized.

Abstract: An embodiment of this invention provides a circuit and method for reducing the number of electronic components needed to calibrate circuits on an IC. A multiplexer is located on the IC where the outputs of a plurality of circuits located on the IC are each connected to a separate data input of the multiplexer. The control input of the multiplexer selects which data input of the multiplexer is connected to an external component. Each data input is individually connected to the component periodically.

Abstract: A biasing circuit comprising a first switching device having a control terminal, and first and second switching terminals. The first switching terminal being connected to a supply voltage, the second switching terminal being connected through a first resistive element to ground, and the control terminal being supplied by a reference voltage which is determined depending on the mode of operation of the circuit. The circuit further comprising a first branch connected between the control terminal and ground comprising a second resistive element in series with a second switching device. The second switching device forming part of a first current mirror having a second branch for effecting a generated bias value. During a normal mode of operation the reference voltage is dependant on the generated bias value, whereas during a standby mode of operation the reference voltage is connected to a low potential.

Abstract: In CMOS processing, there may be a case in which a resistance element, such as a poly-silicon resistance, or the like, may be formed which has negative temperature characteristics. In a constant current circuit using this resistance element, a constant current output less affected by the influence of varying temperature is obtained. To a load-side path of a current mirror circuit, a serial connection circuit and a temperature compensation circuit are arranged in parallel each other. The serial connection circuit includes a transistor Q1, a resistance element R1 and a bipolar transistor Q6 and flows a current I1 having positive temperature characteristics. The temperature compensation circuit includes a transistor Q8 and a resistance element R2 and flows a current I2 having negative temperature characteristics. A constant current output based on the sum current I of the currents I1 and I2 is obtained.

Abstract: A circuit producing a reversed bandgap reference voltage circuit VRBG includes first and second resistors coupled as a voltage divider between ground and a first conductor, a base of a first transistor being coupled to the voltage divider to produce a first voltage VBE1(1+1/M) between the first conductor and ground, M being a ratio of the resistances of the first and second resistors. A third resistor is coupled between a base of the second transistor and ground to produce a second voltage VBE2+VRBGP between the second conductor and ground. First circuitry forces the collector current of the first transistor to be equal to the collector current of the second transistor, and second circuitry forces the first voltage VBE1(1+1/M) to be equal the second voltage VBE2+VRBGP. One of the first circuitry and second circuitry includes an operational amplifier coupled to effectuate the forcing.

Abstract: A technique of improving antialiasing and adjacent channel interference filtering uses cascaded passive IIR filter stages combined with direct sampling and mixing. The methodology and related architecture allows for increased passive IIR filtering without necessitating use of amplifier stages.

Abstract: A phonon laser pumped by a thermal gradient, the phonon laser having a coherent phonon pumping media, a heat source and a heat sink. The pumping media includes an array of micro resonators and a thermal phonon emitting media.

Abstract: A DC offset cancellation block is provided for canceling a DC offset in a signal path. The signal path may include an input and an output. The DC offset cancellation block may include an active integrator coupled between the input and the output to provide a negative feedback to the signal path. The active integrator may include an operational-amplifier (op-amp), a capacitive component with a capacitance C, and a resistive component with a resistance R, and the capacitive component may be coupled to the op-amp via a closed feedback loop. The DC offset cancellation block may also include a first amplifier with a gain of GA coupled with the capacitive component in the closed feedback loop such that a RC time constant of the active integrator is changed from RC to RCGA.

Abstract: A dynamic pulse width modulation (PWM) amplifier comprising an input terminal, a dynamic PWM controller, a power stage, a low pass filter, and an output terminal. The input terminal receives an input signal. The dynamic PWM controller transforms the N-bit input signal sampled by a sampling frequency to a 1-bit PWM signal. The power stage receives and outputs the 1-bit PWM signal. The low pass filter receives and outputs the 1-bit PWM signal. The 1-bit PWM signal is used to drive the power stage and the low pass filter. The output terminal outputs the 1-bit PWM signal. The dynamic PWM amplifier is characterized in the dynamic PWM amplifier uses a register array to store the input signal processed immediately in each frame, regroups the input signal, and outputs the regroup signal, so that the 1-bit PWM signal is changed according to the input signal.

Abstract: A PWM circuit converts output data of a calculator to a pulse width modulation signal, and outputs it to a load (speaker) through a buffer amplifier and a low-pass filter. A digital low-pass filter has the same filter characteristic as a low-pass filter. An error calculator calculates the error ?(z) between the input data and the output of the filter, and outputs it to the calculator. The output of the filter becomes a digital signal having substantially the same digitalized waveform as an analog signal applied to the load, and also no distortion contains in the digital signal. Accordingly, the output data ?(z) of the error calculator becomes data corresponding to the distortion of the output signal. In the calculator, the data ?(z) is subtracted from the input data, and the subtraction result is applied to the PWM circuit to reduce the distortion.

Abstract: A PAMELA-type of composite power amplifier is configured in such a way that a single power amplifier is operated at low output voltage amplitudes by prohibiting a pair of outphasing power amplifiers to produce any current. Preferably, at output voltage amplitudes above the maximum voltage of the single power amplifier is to be reached, the pair of outphasing power amplifiers is taken into operation providing currents phase shifted by substantially 180 degrees. When also the outphasing power amplifiers reach their maximum voltages, an outphasing operation is performed.