Composite capacitor and method for forming the same
An electronic assembly (98) includes a substrate (20), a capacitor having first and second conductors (38,54) formed over the substrate, a first set of conductive members (76) formed over the substrate and being electrically connected to the first conductor of the capacitor, and a second set of conductive members (78) formed over the substrate and being electrically connected to the second conductor of the capacitor.
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The present invention generally relates to a microelectronic assembly and a method for forming a microelectronic assembly, and more particularly relates to a composite capacitor and a method for forming the same.
BACKGROUND OF THE INVENTIONIn recent years, semiconductor integrated circuits have become more complicated both in terms of packing density and the variety of device components that are included in a single circuit. As the productivity and performance demands increase, the size of integrated circuits, and the microelectronic dies (or “dice”), or semiconductor chips, on which they are formed continues to be reduced. As the devices become smaller and smaller, it is increasingly difficult to find room on each die for all of the desired components. Passive device components, particularly capacitors, can be greatly affected as the performance of such devices is often dependent on the surface area of die used.
Depending on the intended use of the semiconductor chip, one of the types of passive devices formed on the semiconductor substrate (e.g., wafer) may be a capacitor. “On-chip” capacitors are often used on integrated circuit devices such as converters, radio frequency (RF) circuits, and filters. In such applications, it is desirable for the capacitors to achieve a high capacitance density, as well as have a high “Q-factor,” low voltage and temperature coefficients, excellent matching properties, and long-term reliability.
One common type of on-chip capacitor used in the semiconductor industry is known as a “double poly capacitor” (DPC). A DPC typically includes two conductive plates stacked over a field oxide on the substrate with an insulating material, or dielectric, formed between. DPCs are relatively inexpensive to manufacture and can achieve reasonably high capacitance densities. However, DPCs have high voltage coefficients, and because of non-uniformity which often occurs in the thickness of the dielectric across the substrate, the capacitance density the individual capacitors formed on the same substrate varies, which leads to poor matching.
Another type of capacitor is known as a “metal-insulator-metal” (MIM) capacitor. MIM capacitors are known to have better electrical characteristics than DPCs, including smaller voltage and temperature coefficients. However, MIM capacitors add significantly to the manufacturing costs of the integrated circuit because several extra processing steps are required which are not typically used in the formation of the integrated circuits (i.e., are not part of standard complimentary metal oxide semiconductor (CMOS) processing).
Accordingly, it is desirable to provide a capacitor with improved electrical characteristics while maintaining low manufacturing costs. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.
The present invention will hereinafter be described in conjunction with the following drawings, wherein like numerals denote like elements, and
The following detailed description is merely exemplary in nature and is not intended to limit the invention or application and uses of the invention. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, brief summary, or the following detailed description. It should also be noted that
Referring to
Referring to
As shown in
Referring to
Referring again to
The dielectric layer 44 and the upper conductive layer 46 are then patterned to form a dielectric body 52 and an upper conductive plate 54 from the dielectric layer 44 and the upper conductive layer 46, respectively, on the lower conductive plate 38, as shown in
As shown in
Referring to
Still referring to
As shown, the majority of both the first and second lower conductive traces 76 and 78 extend across the lower vias 70 and 72 in substantially the same direction. However, one of the first lower traces 76 transverses the other first lower traces 76 such that all of the first lower traces 76 are electrically connected. Likewise, one of the second lower traces 78 transverses the other second lower traces 78 such that all of the second lower traces 78 are electrically connected. Referring specifically to
The first and second lower conductive traces 76 and 78 have, for example, widths similar to the widths of the vias 70 and 72 (e.g., 0.18 or 0.13 microns) and may be made of the same materials as the vias 70 and 72. The first and second lower traces 76 and 78 have a thickness 80 of, for example, between 0.2 and 0.6 microns, which also defines the thickness of the lower trace layer 68. The lower dielectric layer 66 has a thickness 82 of, for example, between 0.5 and 1.0 microns such that the first lower traces 76 lie at a height 84 of, for example, between 0.2 and 0.5 microns above the upper conductive plate 54.
As illustrated in
The formation of the upper traces 94 and 96 may substantially complete the formation of an electronic, or microelectronic, assembly, according to one embodiment of the present invention. As shown in
In an alternative view, the composite capacitor includes the DPC and a fringe capacitor formed over the DPC. The DPC includes the lower and upper conductive plates 38 and 54, and the fringe capacitor includes the different sets of conductive vias and traces within the various layers of the build up layer. The DPC and the fringe capacitor are connected in parallel.
After final processing steps, the substrate 20 may be sawed into the individual microelectronic dice 30 (shown in
One advantage of the electronic assembly described above is that the capacitance density of the capacitor is increased without having to increase the size of the device. Therefore, the size of the device may be reduced without a reduction in overall capacitance. Another advantage is that because the vias and traces are formed using conventional CMOS processing steps, the cost of manufacturing the composite capacitor is minimized. A further advantage is that the electrical performance of the capacitor is improved in several ways, such as voltage linearity coefficient, mismatch performance, across-wafer variations, Cparasitic/Cintrinsic, the Q-factor, series resistance, power loss, frequency response, and temperature dependence (i.e., coefficient).
Additionally, still referring to
Other embodiments may include build up layers with an increased number of vias and traces formed therein and/or additional build up layers with different numbers (including zero) of vias and/or traces stacked over the assembly shown in
In an embodiment having three trace layers utilizing 0.18 micron traces, the capacitance density may be increased by as much as 31%, the temperature coefficient may be decreased by as much as 24%, and the voltage coefficient may be reduced by as much as 22% compared to a conventional DPC. In an embodiment having three trace layers utilizing 0.13 micron traces, the capacitance density may be as much as 41% greater than a DPC. In an embodiment utilizing a 4000 Å thick insulation region with three trace layers, the Cparasitic/Cintrinsic ratio may be reduced by as much as 30% compared to a DPC.
The invention provides an electronic assembly including a substrate, a capacitor having first and second conductors formed over the substrate, a first set of conductive members formed over the substrate and being electrically connected to the first conductor of the capacitor, and a second set of conductive members formed over the substrate and being electrically connected to the second conductor of the capacitor.
The first conductor and the first set of conductive members may jointly form a first capacitor electrode and the second conductor and the second set of conductive members may jointly form a second capacitor electrode such that when a voltage is applied across the first and second capacitor electrodes a charge is stored between the first and second capacitor electrodes.
The first capacitor electrode and the second capacitor electrode may be separated by a distance. The electronic assembly may also include a plurality of insulating bodies respectively positioned between the first and second capacitor electrodes such that the first and second capacitor electrodes are electrically disconnected.
The first conductor may be a first conductive plate, and the second conductor may be a second conductive plate. The first conductive plate may have a first width and a first thickness. The first width may be greater than the first thickness and extend in a direction that is substantially parallel to an upper surface of the substrate. The second conductive plate may be formed over the first conductive plate and have a second width and a second thickness. The second width may be greater than the second thickness and extend in a direction that is substantially parallel to the first width.
The first conductive plate may have first and second portions, and the first width may be greater than the second width such that the second conductive plate covers only the second portion of the first conductive plate. The first set of conductive members may be a first set of conductive traces formed over the first and second conductive plates, and the second set of conductive members may be a second set of conductive traces formed over the first and second conductive plates. The electronic assembly may also include first and second conductive vias. The first conductive via may interconnect the first set of conductive traces and the first conductive plate, and the second conductive via may interconnect the second set of conductive traces and the second conductive plate.
At least one of the conductive traces of the first set of conductive traces may be positioned between conductive traces of the second set of conductive traces, and at least one of the conductive traces of the second set of conductive traces may be positioned between conductive traces of the first set of conductive traces.
The invention also provides a microelectronic assembly including a semiconductor substrate having a semiconductor device formed therein, a first conductive plate formed on the semiconductor substrate, a second conductive plate formed over the first conductive plate, the first and second conductive plates jointly forming a capacitor, and a build up layer formed over the capacitor. The build up layer may have a first set of conductive traces formed therein and electrically connected to the first conductive plate and a second set of conductive traces formed therein and electrically connected to the second conductive plate. The first conductive plate and the first set of conductive traces may jointly form a first capacitor electrode, and the second conductive plate and the second set of conductive traces may jointly form a second capacitor electrode such that when a voltage is applied across the first and second capacitor electrodes a charge is stored between the first and second capacitor electrodes.
The microelectronic assembly may also include a plurality of insulating bodies respectively positioned between the first and second capacitor electrodes such that the first and second capacitor electrodes are electrically disconnected. The first conductive plate may have first and second portions, a first width, and a first thickness. The first width may be greater than the first thickness and extend in a direction that is substantially parallel to an upper surface of the substrate. The second conductive plate may be formed over the first conductive plate and have a second width and a second thickness. The second width may be less than the first width, greater than the second thickness, and extend in a direction that is substantially parallel to the first width. The second conductive plate may cover only the second portion of the first conductive plate.
The first and second sets of conductive traces may include lower and upper conductive traces. The lower conductive traces of the first and second sets of conductive traces may be formed in a first layer of the build up layer, and the upper conductive traces of the first and second sets of conductive traces may be formed in a second layer of the build up layer. The second layer of the build up layer may be formed over the first layer of the build up layer.
At least one of the lower conductive traces of the first set of conductive traces may be positioned between lower conductive traces of the second set of conductive traces. At least one of the lower conductive traces of the second set of conductive traces may be positioned between lower conductive traces of the first set of conductive traces. At least one of the upper conductive traces of the first set of conductive traces may be positioned between upper conductive traces of the second set of conductive traces. At least one of the upper conductive traces of the second set of conductive traces may be positioned between upper conductive traces of the first set of conductive traces. The build up layer may also include first and second conductive vias. The first conductive vias may interconnect the upper and lower conductive traces of the first set of conductive traces and the first conductive plate, and the second conductive vias may interconnect the upper and lower conductive traces of the second set of conductive traces and the second conductive plate.
The invention further provides a method for constructing an electronic assembly. A capacitor having first and second conductive plates is formed over a substrate. A first set of conductive traces being electrically connected to the first conductive plate is formed over the capacitor, and a second set of conductive traces being electrically connected to the second conductive plate is formed over the capacitor. The first conductive plate and the first set of conductive members jointly form a first capacitor electrode and the second conductive plate and the second set of conductive members jointly form a second capacitor electrode such that when a voltage is applied across the first and second capacitor electrodes a charge is stored between the first and second capacitor electrodes.
The method may also include forming a plurality of insulating bodies respectively between the first and second capacitor electrodes such that the first and second capacitor electrodes are electrically disconnected. The method may also include forming first and second conductive vias interconnecting the first set of conductive traces and the first conductive plate and the second set of conductive traces and the second conductive plate, respectively.
At least one of the conductive traces of the first set of conductive traces may be formed between conductive traces of the second set of conductive traces. At least one of the conductive traces of the second set of conductive traces may be formed between conductive traces of the first set of conductive traces. The method may also include forming a semiconductor device within the substrate.
While at least one exemplary embodiment has been presented in the foregoing detailed description of the invention, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or exemplary embodiments are only examples, and are not intended to limit the scope, applicability, or configuration of the invention in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing an exemplary embodiment of the invention, it being understood that various changes may be made in the function and arrangement of elements described in an exemplary embodiment without departing from the scope of the invention as set forth in the appended claims and their legal equivalents.
Claims
1. An electronic assembly comprising:
- a substrate;
- a capacitor formed over the substrate, the capacitor comprising a first conductive plate having a first width and a first thickness and a second conductive plate formed over the first conductive plate and having a second width and a second thickness, the first and second widths being greater than the respective first and second thicknesses and extending in a direction that is substantially parallel to an upper surface of the substrate, wherein the first conductive plate has first and second portions and the first width is greater than the second width such that the second conductive plate covers only the second portion of the first conductive plate;
- a first set of conductive traces formed over the first and second conductive plates and being electrically connected to the first conductive plate of the capacitor;
- a second set of conductive traces formed over the first and second conductive plates and being electrically connected to the second conductor of the capacitor, wherein the first conductive plate and the first set of conductive traces jointly form a first capacitor electrode and the second conductive plate and the second set of conductive traces jointly form a second capacitor electrode such that when a voltage is applied across the first and second capacitor electrodes a charge is stored between the first and second capacitor electrodes, the first and second capacitor electrodes being separated by a distance;
- first and second conductive vias, the first conductive via interconnecting the first set of conductive traces and the first conductive plate and the second conductive via interconnecting the second set of conductive traces and the second conductive plate; and
- a plurality of insulating bodies positioned between the first and second capacitor electrodes such that the first and second capacitor electrodes are electrically disconnected.
2. The electronic assembly of claim 1, wherein at least one of the conductive traces of the first set of conductive traces is positioned between conductive traces of the second set of conductive traces and at least one of the conductive traces of the second set of conductive traces is positioned between conductive traces of the first set of conductive traces.
3. A microelectronic assembly comprising:
- a semiconductor substrate having a semiconductor device formed therein;
- a first conductive plate formed on the semiconductor substrate;
- a second conductive plate formed over the first conductive plate, the first and second conductive plates jointly forming a capacitor, wherein the first conductive plate has first and second portions, a first width, and a first thickness, the first width being greater than the first thickness and extending in a direction that is substantially parallel to an upper surface of the substrate, the second conductive plate is formed over the first conductive plate and has a second width and a second thickness, the second width being less than the first width, greater than the second thickness, and extending in a direction that is substantially parallel to the first width, the second conductive plate covering only the second portion of the first conductive plate;
- a build up layer formed over the capacitor, the build up layer having a first set of conductive traces formed therein and being electrically connected to the first conductive plate and a second set of conductive traces formed therein and being electrically connected to the second conductive plate, wherein the first conductive plate and the first set of conductive traces jointly form a first capacitor electrode and the second conductive plate and the second set of conductive traces jointly form a second capacitor electrode such that when a voltage is applied across the first and second capacitor electrodes a charge is stored between the first and second capacitor electrodes; and
- a plurality of insulating bodies respectively positioned between the first and second capacitor electrodes such that the first and second capacitor electrodes are electrically disconnected.
4. The microelectronic assembly of claim 3, wherein the first and second sets of conductive traces include lower and upper conductive traces, the lower conductive traces of the first and second sets of conductive traces being formed in a first layer of the build up layer and the upper conductive traces of the first and second sets of conductive traces being formed in a second layer of the build up layer, the second layer of the build up layer being formed over the first layer of the build up layer.
5. The microelectronic assembly of claim 4, wherein at least one of the lower conductive traces of the first set of conductive traces is positioned between lower conductive traces of the second set of conductive traces, at least one of the lower conductive traces of the second set of conductive traces is positioned between lower conductive traces of the first set of conductive traces, at least one of the upper conductive traces of the first set of conductive traces is positioned between upper conductive traces of the second set of conductive traces, and at least one of the upper conductive traces of the second set of conductive traces is positioned between upper conductive traces of the first set of conductive traces and the build up layer further comprises first and second conductive vias, the first conductive vias interconnecting the upper and lower conductive traces of the first set of conductive traces and the first conductive plate and the second conductive vias interconnecting the upper and lower conductive traces of the second set of conductive traces and the second conductive plate.
6. A method for constructing an electronic assembly comprising:
- forming a capacitor over a substrate, the capacitor having first and second conductive plates, wherein the first conductive plate has first and second portions, a first width, and a first thickness, the first width being greater than the first thickness and extending in a direction that is substantially parallel to an upper surface of the substrate and the second conductive plate is formed over the first conductive plate and has a second width and a second thickness, the second width being less than the first width, greater than the second thickness, and extending in a direction that is substantially parallel to the first width, the second conductive plate covering only the second portion of the first conductive plate;
- forming a first set of conductive traces over the capacitor, the first set of conductive traces being electrically connected to the first conductive plate; and
- forming a second set of conductive traces over the capacitor, the second set of conductive traces being electrically connected to the second conductive plate, wherein the first conductive plate and the first set of conductive traces jointly form a first capacitor electrode and the second conductive plate and the second set of conductive traces jointly form a second capacitor electrode such that when a voltage is applied across the first and second capacitor electrodes a charge is stored between the first and second capacitor electrodes.
7. The method of claim 6, further comprising forming a plurality of insulating bodies respectively between the first and second capacitor electrodes such that the first and second capacitor electrodes are electrically disconnected.
8. The method of claim 7, further comprising forming first and second conductive vias interconnecting the first set of conductive traces and the first conductive plate and the second set of conductive traces and the second conductive plate, respectively.
9. The method of claim 8, wherein at least one of the conductive traces of the first set of conductive traces is formed between conductive traces of the second set of conductive traces and at least one of the conductive traces of the second set of conductive traces is formed between conductive traces of the first set of conductive traces.
10. The method of claim 9, further comprising forming a semiconductor device within the substrate.
5583359 | December 10, 1996 | Ng et al. |
6385033 | May 7, 2002 | Javanifard |
6620700 | September 16, 2003 | Prinslow |
6646860 | November 11, 2003 | Takaramoto |
6690570 | February 10, 2004 | Hajimiri |
6765778 | July 20, 2004 | Du |
20030081371 | May 1, 2003 | Takaramoto et al. |
20040205679 | October 14, 2004 | Drennan |
Type: Grant
Filed: Apr 3, 2006
Date of Patent: Aug 12, 2008
Patent Publication Number: 20070228506
Assignee: Freescale Semiconductor, Inc. (Austin, TX)
Inventors: Won Gi Min (Chandler, AZ), Geno L. Fallico (Cedar Park, TX), Amanda M. Kroll (Plfugerville, TX), Hongning Yang (Chandler, AZ), Jiang-Kai Zuo (Chandler, AZ)
Primary Examiner: A. Sefer
Assistant Examiner: Kevin Quinto
Attorney: Ingrassia, Fisher & Lorenz, P.C.
Application Number: 11/397,493
International Classification: H01L 27/04 (20060101);