Abstract: The present invention provides an apparatus and method of phase correction whereby changes in phase characteristics are measured during data acquisition and, accordingly, phase correction parameters that are applied during image reconstruction are updated in real-time. This adaptive and dynamic phase correction reduces variability in image fidelity during the course of long MR scans, such as EPI scans, and provides consistent artifact reduction during the course of an MR scan.

Abstract: An RF coil includes two coil portions that are spaced apart to define a slab therebetween. Each coil portion is a microstrip transmission line formed as a loop wherein the microstrip includes a conductive strip disposed on one side of a dielectric material and a ground plane disposed on the other side of the dielectric material. When energized, a uniform RF field is produced in the slab. An array of such RF coils arranged back to back can be formed to allow for the selective excitation of a desired slab.

Abstract: There is described a magnetic resonance device incorporating at least one first component part, which when the magnetic resonance device is operating oscillates, attached by at least one local load-bearing joint to at least one second oscillation-sensitive component part of the magnetic resonance device, where the joint has at least one actuatable facility for generating counter-oscillations which damp an oscillation of the first component part, where the second component part is a cladding element, in particular a vacuum cladding, which is affixed to the magnet via the joint, whereby a gap between the cladding element and the magnet is evacuatable, and the gap is provided with a pressure-isolating acoustically soft seal, in particular in the form of bellows.

Abstract: A sensor for performing micro-conductivity measurements during well logging measurements in a borehole includes a magnetic core having a conductive insert wherein windings are driven with alternating current. Some embodiments include a sensor further having a conductive case. Various aspects of the sensor, such as dimensions and conductive properties of fabrication materials are selected to maximize performance of the sensor. Methods for using the sensor call for, among other things, placing the sensor in a well logging tool, and placing the tool in a well bore. A substantial focusing of the magnetic field on the wall of the borehole is achieved and provides for high quality data.

Abstract: This invention provides an electronic device that has a battery with a power storage unit and a display module, a power detector and a display control module. The power storage unit is for storing electrical power and the display module is placed on the surface of the battery. The power detector is selectively coupled to the battery, and generates a remaining power signal after detecting the remaining power in the battery. The remaining power signal is used to control the display control module. When the power detector is selectively coupled to the battery, the display module shows the current remaining power in response to the action of the display control module. When the power detector is separated from the battery, the display module is essentially capable of maintaining the showing of remaining power.

Abstract: An interface for a bus test instrument is readily adaptable for testing a wide range of bus types. The interface includes a pair of transmit lines and a pair of receive lines. A transmitting circuit is adaptable for transmitting either single-ended or differential signals over the transmit lines, and at least one receiving circuit is adaptable for receiving either single-ended or differential signals from either the receive lines or the transmit lines. The flexible interface allows the testing of single-ended and differential busses, as well as busses that support both unidirectional and bidirectional communication.

Abstract: A method of sensing absolute position of a structure includes: generating a signal pattern to repetitively provide a changing voltage to each of two or more tracks of a sensor, capacitively coupling an electrode of the sensor to the tracks to determine a first electrode position along the tracks by detecting a first group of signals emitted in response to the signal pattern, moving at least one of the electrode and the tracks relative to another of the electrode and the tracks to result in a second electrode position along the tracks different from the first electrode position, and detecting a second group of signals emitted in response to the signal pattern with the electrode capacitively coupled to the tracks to determine the second electrode position.

Abstract: A simple and robust variable coaxial capacitive sensor and detection method for monitoring the position of a rapidly reciprocating member such as a piston or displacer in a free piston Stirling engine. The coaxial capacitor of the present invention in a preferred embodiment thereof is configured to modulate capacitive electrode area rather than inter-electrode spacing and as a result a highly linear transfer function can be achieved. Also disclosed are detection methods which derive and process signals in connection with applications which have small sensor capacitance variations while suppressing stray capacitance error.

Abstract: A reduced number of voltage regulator modules provides a reduced number of supply voltages to the package. The package includes a voltage plane for each of the voltage regulator modules. Each core or other component on the die is tied to a switch on the package, and each switch is electrically connected to all of the voltage planes. A wafer-level test determines a voltage that optimizes performance of each core or other component. Given these voltage values, an engineer may determine voltage settings for the voltage regulator modules and which cores are to be connected to which voltage regulator modules. A database stores voltage setting data, such as the optimal voltage for each component, switch values, or voltage settings for each voltage regulator module. An engineering wire may permanently set each switch to customize the voltage supply to each core or other component.

Abstract: A defective position of a sample to be tested is detected by irradiating the test sample and another test sample with electron beam while scanning the test samples, storing values of current generated in the test samples correspondingly to electron beam irradiation positions as current waveforms and comparing the current waveforms.

Abstract: A probe card, and a probe sheet used for the method of testing (producing) a semiconductor device using the probe card, include first contact terminals in electrical contact with the electrodes of a test object formed at a narrow pitch, wires connected with and led from the first contact terminals, and second contact terminals in electrical contact with the wires. The first and second contact terminals are formed using the etching holes of a crystalline member and lined with a metal sheet.

Abstract: A test configuration for double sided probing of a device under test includes a holder to secure the device under test in a first orientation, a calibration substrate secured in a second orientation and a probe capable of calibration using the calibration substrate and probing the device under test.

Abstract: An apparatus includes a test board for testing electrical characteristics of the semiconductor chip; socket pins vertically disposed on the test board to electrically connect the test board, and external terminals of the semiconductor chip; socket springs interposed between the socket pins and the test board and making the socket pins vertically elastic; a plurality of laser beam transmitters vertically penetrating the socket pins, the socket springs, and the test board; and a laser beam source supplying laser beams to the laser beam transmitters.

Abstract: An insulative block has a first face adapted to oppose a board on which an inspection circuit is arranged and a second face adapted to oppose a device to be inspected. The insulative block is formed with through holes each of which communicates the first face and the second face. A conductive plating layer is formed on the first face, the second face, and an inner face of at least one of the through holes. Each of contact probes includes a conductive tubular body held in an associated one of the through holes and a plunger which is retractably projected from one end of the tubular body and is adapted to come in contact with a terminal of the device. The contact probes includes a first group of contact probes adapted to come in contact with terminals of a first circuit in the device, and a second group of contact probes adapted to come in contact with terminals of a second circuit in the device.

Abstract: Testing of a system-on-a-chip having a programmable section and a plurality of high-speed interfaces begins by configuring the programmable section to support a 1st level testing of the plurality of high-speed interfaces. The testing continues by testing one of the plurality of high-speed interfaces at the 1st level of testing via the programmable section. The testing continues by evaluating the tested performance characteristics in accordance with the prescribed performance characteristics of the standard to determine whether the one of the plurality of high-speed interfaces conforms with the standard requirements. When the one of the plurality of high-speed interfaces conforms with the standard requirements, the plurality of high-speed interfaces are configured for a 2nd level testing, where the 1st level testing is more stringent than the 2nd level testing. The testing continues by testing, at the 2nd level, remaining ones of the plurality of high-speed interfaces.

Abstract: A pipeline tester is disclosed that is capable of testing systems-on-a-chip (SOCs) or Devices Under Test (DUTs) in pipeline fashion. The tester provides faster, more economical testing of such SOCs and DUTs, which are loaded sequentially into the tester. A plurality of underlying test stations are disposed in the tester. Above the test stations are disposed corresponding test fixtures which are configured to receive moveable test beds therein. The test beds are mechanically and electrically connected to the underlying test stations. Loaded within each test bed is an SOC or DUT on which one or more electrical or electronic tests are performed. Once the test has been completed, the test bed is moved to another test station, where another electrical or electronic test is performed.

Abstract: On-chip termination (OCT) calibration techniques are provided that support input/output (IO) banks on an integrated circuit (IC) using OCT controllers. The OCT controllers calibrate the on-chip termination impedance in the IO banks using a shared parallel bus or separate parallel buses. Multiplexers or select logic in each IO bank select control signals from the OCT controllers in response to select signals. According to some embodiments, each of the IO banks on an IC can receive OCT control signals from any of the OCT controllers on the IC.

Abstract: Provided is a semiconductor device capable of controlling an on-die-termination (ODT) circuit and an off-chip-driver (OCD) circuit and a control method used by the semiconductor device. The semiconductor device includes a control code generation unit generating a control code in response to a control signal, an addition unit adding an adjustment code to the control code to produce an adjusted control code, and an ODT circuit, wherein an impedance of the ODT circuit is adjusted in response to the adjusted control code. The semiconductor device can adjust the control code more precisely by adding or subtracting the adjustment code to or from the control code. Accordingly, the impedance of an OCD circuit or ODT circuit can be adjusted more precisely.

Abstract: A power gated semiconductor integrated circuit comprises: (1) logic circuit to be power gated, said logic circuit having a virtual ground rail; (2) footer device disposed between said virtual ground rail and a ground rail for reducing power consumption of said logic circuit; and (3) virtual rail voltage clamp disposed electrically in parallel with said footer device for limiting the voltage at the virtual ground rail, the virtual rail voltage clamp comprising at least one NFET. A total of Nf NFETs are connected to the virtual ground rail of the integrated circuit for use as both virtual rail voltage clamps and footer devices. A quantity of Nmax-VC NFETs are scanned and perform the function of voltage clamps and the remaining (Nf-Nmax-VC) NFETs perform power gating. Manufacturing variability immunity and tuning of the variability immunity is achieved by adjusting the quantity Nmax-VC based upon testing of the manufactured integrated circuit.

Abstract: Some embodiments of the invention provide a reconfigurable IC that has several reconfigurable circuits. Each reconfigurable circuit for configurably performing a set of operations and for reconfiguring at a first frequency. The reconfigurable IC also has at least one reconfiguration signal generator for receiving a clock signal at a second frequency and producing a set of reconfiguration signals with a third frequency. The reconfiguration signals are supplied to the reconfigurable circuits to direct the reconfiguration of the reconfigurable circuits at the first frequency.

Abstract: A field programmable gate array includes a plurality of programmable logic blocks to implement one or more logic functions. The field programmable gate array includes a plurality of independent registers not associated with any specific one of the plurality of programmable logic blocks. The plurality of independent registers may be programmed to support any one of the plurality of programmable logic blocks.

Abstract: A circuit arrangement including a data input for applying a data signal, a set input for applying a set signal and an output for providing an output state. The output is coupled to the data input and to the set input in such a manner that the output state provided is set only when an input state of the data signal and the output state differ from one another and the set signal changes to a prescribed state.

Abstract: Interconnecting logic provides connectivity of an embedded fixed logic circuit, or circuits, with programmable logic fabric of a programmable gate array such that the fixed logic circuit functions as an extension of the programmable logic fabric. The interconnecting logic includes interconnecting tiles and may further include interfacing logic. The interconnecting tiles provide selective connectivity between inputs and/or outputs of the fixed logic circuit and interconnect of the programmable logic fabric. The interfacing logic, when included, provides logic circuitry that conditions data transfers between the fixed logic circuit and the programmable logic fabric. In one operation, the programmable logic fabric is configured prior to the startup/boot sequence of the fixed logic circuit. In another operation, the fixed logic circuit is started up and is employed to configure the programmable logic fabric.

Abstract: A level shifter includes a first inverter coupled between the second voltage and the first voltage, and a second inverter coupled between the second voltage and the first voltage, the second inverter being cross-coupled with the first inverter for latching a value therein. A first switch module is coupled between a first data storage node of the first and second inverters and an input signal swinging between the first voltage and a ground voltage. A second switch module is coupled between a second data storage node of the first and second inverters and an inverted input signal swinging between the ground voltage and the first voltage. The first and second inverters and the first and second switch modules include one or more MOS transistors with gate oxide layers of the same thickness.

Abstract: An input buffer circuit with hysteresis includes a first stage and a second stage. The first stage includes a resistive device to provide a resistance between two nodes of the first stage. The two nodes are responsive to a signal input. The second stage includes four series-coupled transistors. A first node is coupled to the control electrodes of two of the four transistors and the second node is coupled to the control electrodes of the other two transistors. The second stage includes a signal output. In some examples, a resistance provided by the resistive device is variable and provides the buffer circuit with hysteresis.

Abstract: An output buffer circuit, which minimizes or prevents output delay of output signal and degradation of slew rate while suppressing overshoot and undershoot, is provided. In a first time period when an input signal to a gate of an N-channel output transistor changes from ‘L’ level to ‘H’ level, the gate is connected to an output terminal through a capacitor element so that the overshoot is suppressed. In addition, the output buffer circuit stores negligible electrical charge in the capacitor element prior to the first time period, which results in minimal delay in outputting a buffered signal and degradation of slew rate while suppressing undershoot when the input signal changes from ‘H’ level to ‘L’ level in the first time period.

Abstract: A universal logic gate apparatus is disclosed, which include a plurality of self-assembling chains of nanoparticles having a plurality of resistive connections, wherein the plurality of self-assembling chains of nanoparticles comprise resistive connects utilized to create a universal, reconfigurable logic gate A plasticity mechanism is also provided, which is based on a plasticity rule for creating stable connections from the plurality of self-assembling chains of nanoparticles for use with the universal, reconfigurable logic gate. The plasticity mechanism can be based, for example, on a 2-dimensional binary input data stream, depending upon design considerations. A circuit is also associated with the plurality of self-assembling chains of nanoparticles, wherein the circuit provides a logic bypass that implements a flip-cycle for second-level logic.

Abstract: An inhibit circuit which produces an inhibit signal when a variation in a power supply potential is detected includes a comparator having a negative input connected to a generator producing a reference potential and a positive input connected to an output of a first image circuit producing a first potential that is an image of the power supply potential. The first image circuit includes a diode and a circuit for the production of a reference current parallel-connected between a common point to which the power supply potential is applied and an output of the first image circuit connected to the positive input of the comparator. The circuit has particular utility in portable integrated circuits with very low consumption when idle such as in mobile telephony.

Abstract: A pulse extension circuit for extending a pulse signal includes an input unit for receiving the pulse signal, an edge detection unit coupled to the input unit for generating a initiation signal, a pulse initiation unit coupled to the edge detection unit for outputting a control signal and adjusting a voltage level of the control signal, a pulse width control unit coupled to the pulse initiation unit for outputting a termination signal, a reset unit coupled to the edge detection unit, the pulse initiation unit and the pulse width control unit for outputting the first reset signal and the second reset signal to reset the pulse initiation unit and the pulse width control unit, and an output unit coupled to the input unit and the pulse initiation unit for extending a signal period of the pulse signal according to the pulse signal and the control signal.

Abstract: A duty cycle corrector includes a first controllable delay configured to delay a first signal to provide a second signal, a second controllable delay configured to delay the second signal to provide a third signal, a circuit configured to adjust the first controllable delay and the second controllable delay to phase lock the third signal to the first signal, and a phase mixer configured to phase mix the first signal and the third signal to provide a fourth signal.

Abstract: The disclosed methodology and apparatus measures the duty cycle of a reference clock signal that a clock circuit supplies to a duty cycle measurement (DCM) circuit located “on-chip”, namely on an integrated circuit (IC) in which the DCM circuit is incorporated. In one embodiment, the DCM circuit includes a capacitor driven by a charge pump. The reference clock signal drives the charge pump. The clock circuit varies the duty cycle of the reference clock signal among a number of known duty cycle values. The DCM circuit stores resultant capacitor voltage values corresponding to each of the known duty cycle values in a data store. The DCM circuit applies a test clock signal having an unknown duty cycle to the capacitor via the charge pump, thus charging the capacitor to a new voltage value that corresponds to the duty cycle of the test clock signal. Control software accesses the data store to determine the duty cycle to which the test clock signal corresponds.

Abstract: An integrated circuit is configured with a pin for specifying a reset configuration vector of a circuitry within the integrated circuit. The resistance value of a low cost external resistor coupled to the pin is detected and utilized to identify the configuration. Logic on the integrated circuit detects and utilizes the resistor value to index to a configuration vector in a look-up table. The integrated circuit is then configured in accordance with the indexed configuration vector.

Abstract: A latch section includes a latch circuit. The latch circuit includes inverters and latches an input signal from a gating section. Between one of the inverters of the latch circuit and the output terminal OUT is disposed an analog switch whose ON/OFF characteristics are switched according to High/Low of a reset signal. Between the output terminal and an input for receiving a low potential as a power supply of a flip-flop is disposed a switching element whose ON/OFF characteristics are switched according to High/Low of the reset signal.

Abstract: A high-reliability, multi-threshold complementary metal oxide semiconductor (CMOS) latch circuit is presented that uses both low and high threshold inverters. The multi-threshold latch circuit includes: a low threshold forward clock inverter inverting an input-terminal logic state and applying the inverted logic state to an output-terminal logic state when a clock is in a first logic state; and a high threshold backward clock inverter forming a circular latch structure together with the forward clock inverter, and inverting an input-terminal logic state and applying the inverted logic state to an output logic state when the clock is in a second logic state.

Abstract: A phase adjustor circuit and a phase adjusting method are capable of preventing a phase shift amount from fluctuating even if a frequency of a transmission carrier wave of a sensor signal fluctuates. A chopping wave converter circuit converts a pulse string signal into a chopping wave. A chopping wave amplitude control circuit compares the amplitude value of the chopping wave with an amplitude reference value and outputs an adjustment signal corresponding to a difference between those values to the chopping wave converter circuit. The chopping wave converter circuit changes a slope of the chopping wave according to the adjustment signal to adjust the amplitude value of the chopping wave. As a result, a feedback group is structured, and the amplitude value of the chopping wave is maintained to a constant value according to the amplitude reference value.

Abstract: The present invention is an electronic isolator that provides low input to output insertion loss, high output to input insertion loss, and substantial asymmetric isolation between a source circuit and a load circuit. The invention actively reduces noise and reflected power appearing on the isolator output. In numerous embodiments, the invention operates in circuit applications from dc through millimeter wave. Multistage electronic isolator embodiments provide increased isolation and greater noise reduction. In other embodiments, the electronic isolator also removes noise appearing on its input. In another embodiment, the invention is configured for high power applications. This embodiment includes circuitry for redirecting power away from the load into resistors or other dissipative elements. In another embodiment, the electronic isolator is configured to remove signal distortion produced by one or more power amplifiers in the system.

Abstract: A method is provided for setting an initial value on a charge-storage element. A circuit includes at least one charge-storage element with at least one signal node coupled to at least one reset circuit that is associated with the charge-storage element. A diode can be included between the charge-storage element and the reset circuit. Initially, an initial potential is applied to the at least one signal node during a setting phase by connecting the at least one signal node to the initial potential. A rest potential can then be applied to the signal node during a subsequent holding phase.

Abstract: A device controls internal voltage. Increased reliability of a semiconductor memory device is obtained by increasing or decreasing a level of internal reference voltage according to change of the device. Fuse ROMs generate fuse signals having different levels according to a cutting condition of each fuse. A bit counter performs up/down counting operation in response to a count control signal after setting the fuse signals to initial values in response to a set signal and generates counter output signals which are higher or lower than the initial values by a counting number. A decoder decodes the counter output signals and activates one of switching signals. A reference voltage selector provides a trimming level of internal reference voltage in response to the switching signals and generating reference voltage.

Abstract: A current control circuit with limiter includes a voltage follower as the output unit of the current control circuit, the voltage follower including a transistor, the circuit further including two operational amplifiers and two diodes. In a first operational amplifier, the non-inverting input receives an input voltage to the current control circuit and the inverting input receives the output of the voltage follower. In a second operational amplifier, the non-inverting input receives a predetermined voltage and the inverting input receives the output of the voltage follower. A first diode is connected between the output of the first operational amplifier and the input of the voltage follower. A second diode is connected between the output of the second operational amplifier and the input of the voltage follower.

Abstract: The invention relates to a demodulator to demodulate frequency-modulated signals FM including a phase locked loop PLL including at least a phase detector, a loop filter and a voltage controlled oscillator function VCO?, characterized in that said voltage controlled oscillator function VCO? has modifiable gain. The invention allows to eliminate drawbacks presented by the conventional use of a complex gain modifiable amplifier at the input of demodulated signal processing means. Application: demodulation of modulated signals: wireless phone, home network.

Abstract: A variable gain amplifier circuit according to an embodiment of the invention includes: an output offset correcting unit for executing correction to attenuate a fixed offset component independent of a gain change of a variable gain amplifier circuit out of a DC offset involved in an output voltage of an amplifying unit; and an input offset correcting unit for executing correction to attenuate an input offset component that varies depending on a gain of an amplifying unit. The correction of the fixed offset component with the output offset correcting unit and the correction of the input offset component with the input offset correcting unit are independently executed.

Abstract: A voltage control circuit is proposed, having an input for supplying a voltage control signal and having an output for production of a supply voltage. The voltage control circuit contains a control loop with a DC/DC converter arranged between a first node and a second node. The first node is designed to emit the difference between signals which are applied on the input side. The second feed node is designed to emit the sum of the applied signals. The first and the second feed nodes provide two point modulation with the DC/DC converter within the control loop of the voltage control circuit. In this case, a signal which is applied on the input side is split into a radio frequency component and a low frequency component. The processing of the low frequency component in the DC/DC converter reduces the requirements for the switching frequencies for the DC/DC converter, increases the efficiency of the voltage control circuit, and reduces the power losses.

Abstract: A multiple power mode amplifier provides a low and a high power mode without using switches. This amplifier may be used in radio frequency (RF) applications such as mobile telephones, pagers, portable digital assistants, and wireless e-mail devices. In the low power mode, the power consumption of the amplifier is reduced, which will increase operation time, especially important for battery-operated devices. In one implementation, the amplifier includes a number of impedance matching network units (130, 140, 150, and 160), impedance transformer (170), and a power stage (120). An implementation provides further power consumption savings by modulating a bias of an amplifier stage.

Abstract: An amplifier circuit of a BTL system is disclosed, which comprises a first operational amplifier which outputs an output signal having a same phase as an input signal input to a signal input terminal, a second operational amplifier which outputs an output signal having an opposite phase to the input signal, a voltage divider which generates a midpoint voltage of the input signal, a first resistor connected between an output terminal and a negative phase input terminal of the first operational amplifier, second and third resistors connected in series between the negative phase input terminals of the first and second operational amplifiers, a fourth resistor connected between an output terminal and the negative phase input terminal of the second operational amplifier, and an impedance converter connected between a midpoint voltage node of the voltage divider and a series-connection node of the second and third resistors.

Abstract: An amplifier has an input stage amplifying circuit, an output stage amplifying circuit, and a negative feedback circuit. The input stage amplifying circuit differential-amplifies a first input voltage inputted to a positive phase input node and a second input voltage inputted to an opposite phase input node, and outputs from a positive phase output node. The output stage amplifying circuit amplifies output voltage from a node and outputs it from an output terminal, and generates the second input voltage corresponding to output voltage and feedback-inputs it to the opposite phase input node. The negative feedback circuit has a first PMOS for a current source whose output current fluctuates due to output voltage of the positive phase output node, and a differential amplifying section to which the output current of the first PMOS is supplied and which is formed from a second and third PMOS which differential-amplify the first input voltage and the second input voltage.

Abstract: A power amplification controlling apparatus and method in a mobile communication system are provided. An amplifying part amplifies an input Radio Frequency (RF) signal with a power supply voltage. A bias adaptation part detects a change in at least one an operation and an environment of the amplifying part, attenuates the RF signal according to the detected change, detecting the envelope of the attenuated signal, and generates a supply voltage control signal according to the envelope. A power supply part changes the power supply voltage in response to the supply voltage control signal.

Abstract: The present invention relates to an analog predistorter (100) having a tunable amplitude (60) and/or phase (80) expansion. The predistorter (100) includes a coupler (110) having an input port (112), an output port (114), a first (116) and a second (118) coupled port separated by 90 degrees. A first compensation circuit (120A) is connected to the first coupled port (116) and comprises a first combination (130A) of linear (132A) and nonlinear (131A) circuit elements and a first impedance adjusting unit (140A) for adjusting the impedance seen by the nonlinear circuit element (131A). A second compensation circuit (120B) is connected to the second coupled port (118) and comprises a second combination (130B) of linear (132B) and nonlinear (131B) circuit elements a second impedance adjusting unit (140B) for adjusting the impedance seen by said nonlinear circuit element (131B).

Abstract: A two-port dual-gate field-effect transistor for amplifier applications, wherein a self-bias circuit includes a number of passive elements, such as resistors, diodes and capacitors, is utilized to coupled the output of the amplifier with a second gate of the dual-gate device as a bias source, which transforms the conventional three-port cascade topology into a two-port dual-gate device so as to facilitate device testing, modeling, and packaging for discrete device application. The technology improves the RF performance in conventional two-port single-gate HEMT devices, with slight noise figure degradation.

Abstract: A circuit for improving amplification and noise characteristics of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), and a frequency mixer, an amplifier and an oscillator using the circuit are provided. A gate terminal of the MOSFET is connected to a body terminal of the MOSFET through a capacitor and the gate and body terminals of the MOSFET are connected to a current source to simultaneously provide a signal to both the gate terminal and the body terminal, in order to improve amplification and noise characteristics of the MOSFET. As a result, a higher level of amplification and a lower level of noise than the conventional art can be obtained.

Abstract: A variable gain voltage/current converter circuit of the present invention has an input section active element having an input terminal, an output terminal, and a ground terminal for performing a voltage/current conversion, a potential control circuit for controlling a conversion gain of the input section active element based on a potential at the output terminal of the input section active element, an output section voltage/current converter circuit for generating a current corresponding to a voltage signal generated from the potential control circuit, and a current compensation circuit connected to the output terminal of the input section active element for generating a DC current in accordance with the amount of DC current which flows from the output terminal of the input section active element to the input section active element. The current compensation circuit compensates for a change in a DC current of the input section active element, which occurs when the conversion gain is adjusted.