Abstract: A white light emitting diode component capable of emitting white light includes an LED chip capable of emitting luminescent light, a first phosphor for absorbing first luminescent light of the luminescent light and emitting first emission, and a second phosphor for absorbing second luminescent light of the luminescent light and emitting second emission. A blend of the luminescent light (except for the first and the second luminescent light) and the first and the second emissions forms the white light. The first phosphor has a chemical formula of (Ca1?x?yEuxMy)Se, where x is not equal to zero, y is between zero and one, and M is composed of at least one element selected from a group consisting of Be, Mg, Sr, Ba, and Zn.

Abstract: A semiconductor light-emitting device having a semiconductor light-emitting chip; a high refractive index lens covering around the semiconductor light-emitting chip; and a resin having fine particles mixed therein that fills a space between the semiconductor light-emitting chip and the lens is provided. In the semiconductor light emitting device, the resin having fine particles mixed therein is composed of an optically transparent resin into which a large number of high refractive fine particles having a mean diameter of 100 nm or less and composed of a dielectric material are mixed uniformly to have a distance 200 nm or less between respective particles.

Abstract: A semiconductor light-emitting device includes: a semiconductor multilayer film, a substrate supporting the semiconductor multilayer film; and a phosphor layer formed on the substrate so as to cover the semiconductor multilayer film. The phosphor layer has an outer edge of a cross section taken in a direction parallel to the principal surface of the substrate having a substantially circular shape or a substantially regular polygonal shape having five or more sides. An outer edge of the principal surface of the substrate is formed in a substantially circular shape or a substantially regular polygonal shape having five or more sides. With this configuration, light obtained therefrom has less non-uniformity in color and a high luminous flux can be realized.

Abstract: Light emitting diodes include a substrate having first and second opposing faces and that is transparent to optical radiation in a predetermined wavelength range and that is patterned to define, in cross-section, a plurality of pedestals that extend into the substrate from the first face towards the second face. A diode region on the second face is configured to emit light in the predetermined wavelength range, into the substrate upon application of voltage across the diode region. A mounting support on the diode region, opposite the substrate is configured to support the diode region, such that the light that is emitted from the diode region into the substrate, is emitted from the first face upon application of voltage across the diode region.

Abstract: A semiconductor device for adequately removing heat generated by a semiconductor element is provided. A semiconductor device 100 is equipped with a substrate 2, having a bottom surface 2b and an element mounting surface 2a which is positioned on the opposite side of bottom surface 2b, and a semiconductor element 1, having a main surface 1a which is mounted onto element mounting surface 2a. With L being the length in the long direction of main surface 1 and H being the distance between bottom surface 2b and element mounting surface 2a, the ratio H/L is 0.3 or greater. When the semiconductor element is a light emitting element, element mounting surface 2a is a cavity 2u, and element 1 is provided in cavity 2u. A metal layer 13 is provided on the surface of cavity 2u. In addition, when an electrode 32 which connects to an external part is provided on main surface 1a, on the cavity side of the part which connects with electrode 32, main surface 1a is provided with a groove.

Abstract: A rectifier for rectifying alternating current into direct current is described, in which a three-phase generator includes a three-phase stator winding. The phases of the stator winding are triggered via switching elements of a power circuit. The power circuit is controlled via a control part, which includes a controller component. The rectifier includes a control part (control module) having control terminals and a power circuit (power module) controlled by the control module and optionally provided with a cooling device, in which all the power-conducting components are designed as power MOS components and integrated in a stacked construction.

Abstract: A direct detector for terahertz radiation comprises a grating-gated field-effect transistor with one or more quantum wells that provide a two-dimensional electron gas in the channel region. The grating gate can be a split-grating gate having at least one finger that can be individually biased. Biasing an individual finger of the split-grating gate to near pinch-off greatly increases the detector's resonant response magnitude over prior QW FET detectors while maintaining frequency selectivity. The split-grating-gated QW FET shows a tunable resonant plasmon response to FIR radiation that makes possible an electrically sweepable spectrometer-on-a-chip with no moving mechanical optical parts. Further, the narrow spectral response and signal-to-noise are adequate for use of the split-grating-gated QW FET in a passive, multispectral terahertz imaging system. The detector can be operated in a photoconductive or a photovoltaic mode.

Abstract: High-speed silicon CMOS circuits and high-power AlGaN/GaN amplifiers are integrated on the same wafer. A thin layer of high resistivity silicon is bonded on a substrate. Following the bonding, an AlGaN/GaN structure is grown over the bonded silicon layer. A silicon nitride or a silicon oxide layer is then deposited over the AlGaN/GaN structure. Following this, a thin layer of silicon is bonded to the silicon nitride/silicon oxide layer. An area for the fabrication of AlGaN/GaN devices is defined, and the silicon is etched away from those areas. Following this, CMOS devices are fabricated on the silicon layer and AlGaN/GaN devices fabricated on the AlGaN/GaN surface.

Abstract: The present invention is a compound semiconductor device characterized in that it is Cu-metalized to improved the reliability of the device and to greatly reduce the cost of production.

Abstract: A bipolar transistor comprising a collector region of a first conduction type, and a subcollector region of the first conduction type at a first side of the collector region. The transistor further includes a base region of the second conduction type provided at a second side of the collector region, and an emitter region of the first conduction type which is provided above the base region on the side remote from the collection region. A carbon-doped semiconductor region is provided on the first side alongside the collector region. The bipolar transistor is characterized in that the carbon-doped semiconductor region has a carbon concentration of 1019-1021 cm?3 and the base region has a smaller cross section than the collector region and the collector region has, in the overlap region with the base region, a region having an increased doping compared with the remaining region.

Abstract: A test vehicle for evaluating a manufacturing process for integrated circuits that uses a more space efficient layout of library driving cells arranged to produce circuits that exercise many interconnections that may be designed at the minimum design parameters of a manufacturing process. The cells can be configured to operate as ring oscillators increasing the effective circuit frequency of the test module allowing higher frequency circuit testing, and shortening the time it takes to perform life cycle testing. Visibly marking cells, combined with electrically isolating error prone circuit segments makes, identifying defects much more efficient. The accessibility of many testing methods allows quick location of root cause failures, which allows improvements to be made to the manufacturing process.

Abstract: A MOSFET-type semiconductor device includes a monocrystalline semiconductor layer formed in a shape of a thin wall on a insulating film, a gate electrode straddling over the semiconductor layer around the middle portion of the wall-shaped semiconductor layer via a gate insulating film, source and drain regions formed at the both ends of the semiconductor layer, a first metal-semiconductor compound layer formed on one of the side walls of each of source and drain regions of the semiconductor layer, and a second metal-semiconductor compound layer having a different composition and Shottky barrier height from that of the first metal-semiconductor compound layer on the other side wall of each of source and drain regions of the semiconductor layer.

Abstract: A proper incident state can be obtained in each pixel in accordance with a distance between an optical system and a sensor photoreceptive portion, and improved photoreceptive efficiency and even sensitivity of pixels can be attempted. Since a main light beam a launches on pixels in a screen peripheral part at an angle of incidence ?, a microlens (260), color filter (250), wires (220, 230 and 240), photodiode (110) and so on are disposed along the direction of incidence in accordance with the angle of incidence ? in a positional relationship. The angle of incidence ? here is determined in consideration of a distance from the microlens (260) to the surface of the silicon substrate (100) and a position in depth of the photoelectric converting portion of the photodiode (110) from the surface of the silicon substrate (100). The photoelectric converting portion (n-type region) of the photodiode (110) tilts in a pixel in the screen peripheral part in accordance with the angle of incidence ?.

Abstract: A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.

Abstract: An image sensing circuit and method is disclosed, wherein a photodiode is formed in a substrate through a series of angled implants. The photodiode is formed by a first, second and third implant, wherein at least one of the implants are angled so as to allow the resulting photodiode to extend out beneath an adjoining gate. Under an alternate embodiment, a fourth implant is added, under an increased implant angle, in the region of the second implant. The resulting photodiode structure substantially reduces or eliminates transfer gate subthreshold leakage.

Abstract: A solid-state imaging device includes a plurality of pixels two-dimensionally arrayed in a well region disposed on a semiconductor substrate, each pixel including a photoelectric conversion section having a charge accumulation region which accumulates signal charge; an element isolation layer which is disposed on the surface of the well region along the peripheries of the individual charge accumulation regions and which electrically isolates the individual pixels from each other; and a diffusion layer which is disposed beneath the element isolation layer and which electrically isolates the individual pixels from each other, the diffusion layer having a smaller width than that of the element isolation layer. Each charge accumulation region is disposed so as to extend below the element isolation layer and be in contact with or in close proximity to the diffusion layer.

Abstract: In the solid-state imaging device of the present invention having a photoelectric conversion section and a charge transfer section equipped with a charge transfer electrode for transferring an electric charge generated in the photoelectric conversion section, the charge transfer electrode has an alternate arrangement of a first layer electrode including a first layer electrically conducting film and a second layer electrode including a second layer electrically conducting film, which are formed on a gate oxide film including a laminate film consisting of a silicon oxide film and a metal oxide thin film, and the first layer electrode and the second layer electrode are separated by insulation with an interelectrode insulating film including a sidewall insulating film formed by a CVD process to cover the lateral wall of the first layer electrode.

Abstract: A photoelectric conversion device is provided which is capable of improving the light condensation efficiency without substantially decreasing the sensitivity. The photoelectric conversion device has a first pattern provided above an element isolation region formed between adjacent two photoelectric conversion elements, a second pattern provided above the element isolation region and above the first pattern, and microlenses provided above the photoelectric conversion elements with the first and the second patterns provided therebetween. The photoelectric conversion device further has convex-shaped interlayer lenses in optical paths between the photoelectric conversion elements and the microlenses, the peak of each convex shape projecting in the direction from the electro-optical element to the microlens.

Abstract: A capacitor element is provided which is composed of a lower electrode, an upper electrode formed in opposing relation to the lower electrode, and a capacitor dielectric film made of a ferroelectric material or a high dielectric material and formed between the lower and upper electrodes. The lower electrode, the capacitor dielectric film, and the upper electrode are formed in a region extending at least from within a hole provided in an interlayer insulating film having a first hydrogen barrier film disposed on the upper surface thereof toward a position above the hole. A second hydrogen barrier film in contact with the first hydrogen barrier film is disposed to cover the upper surface of the upper electrode and the side surface of the portion of the upper electrode which has been formed above the hole.

Abstract: The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conductive containers. A retaining structure lattice is formed in physical contact with at least some of the containers, and subsequently the insulative material is removed to expose outer surfaces of the containers. The retaining structure can alleviate toppling or other loss of structural integrity of the container structures. The electrically conductive containers correspond to first capacitor electrodes. After the outer sidewalls of the containers are exposed, dielectric material is formed within the containers and along the exposed outer sidewalls. Subsequently, a second capacitor electrode is formed over the dielectric material. The first and second capacitor electrodes, together with the dielectric material, form a plurality of capacitor devices.

Abstract: Embodiments in accordance with the present invention provide alternative materials, and methods of forming such materials, that are effective as dielectric layers. Such embodiments include forming metal-containing dielectric layers over a silicon-containing substrate where a metal-containing layer is first formed and that treated to form a dielectric layer. Dielectric layers formed by methods of the present invention have a dielectric constant greater than that of silicon dioxide, and can have an equivalent oxide thickness of less than 2 nanometers. Such dielectric layers are useful in the forming of a variety of semiconductor devices such as transistors, capacitors and the like where such devices and integrated circuits formed from such devices are encompassed by embodiments in accordance with the present invention.

Abstract: An exposed top end of a vertical oxide spacer is removed, and a nitride layer is deposited in an amount sufficient to replace the removed portion prior to exposing a memory device to a self align contact etch process. The nitride layer may be used to prevent a short circuit through the oxide spacer. The present invention also provides memory devices that have a gate stack, a vertical spacer adjacent to the gate stack, in which the vertical spacer has a lower portion comprising an oxide and an upper portion comprising a nitride, and a continuous nitride layer overlaying the vertical spacer and the gate stack. The present invention further provides methods of fabricating the above devices, and processor systems which include the devices.

Abstract: A semiconductor memory device includes a memory cell which includes a first gate insulation film provided on the semiconductor substrate; a floating gate electrode provided on the first gate insulation film; a second gate insulation film provided on the floating gate electrode; a control gate electrode provided on the second gate insulation film; a source layer and a drain layer that are provided in the semiconductor substrate, the source layer and the drain layer respectively being provided either side of a channel region which is below the floating gate electrode; a source electrode that is electrically connected to the source layer; a buffer film provided on the drain layer; and a memory cell including a drain electrode electrically connected to the drain layer through the buffer film, wherein when viewing the surface of the semiconductor substrate from above, an overlapped area between the floating gate electrode and the drain layer is smaller than an overlapped area between the floating gate electrode an

Abstract: An arrangement of nonvolatile memory devices, having at least one memory device level stacked level by level above a semiconductor substrate, each memory level comprising an oxide layer substantially disposed above a semiconductor substrate, a plurality of word lines substantially disposed above the oxide layer; a plurality of bit lines substantially disposed above the oxide layer; a plurality of via plugs substantially in electrical contact with the word lines and, an anti-fuse dielectric material substantially disposed on side walls beside the bit lines and substantially in contact with the plurality of bit lines side wall anti-fuse dielectrics.

Abstract: In a non-volatile memory device with a buried control gate, the effective channel length of the control gate is increased to restrain punchthrough, and a region for storing charge is increased for attaining favorably large capacity. A method of fabricating the memory device includes forming the control gate within a trench formed in a semiconductor substrate, and forming charge storing regions in the semiconductor substrate on both sides of the control gate in a self-aligning manner, thereby allowing for multi-level cell operation.

Abstract: A semiconductor device may include a fin structure having source/drain regions and channel fins connected between source/drain patterns. A gate insulation layer may be provided on the channel fins. A gate electrode may include lower gate patterns and an upper gate pattern. The lower gate patterns may extend in a vertical direction and contact the gate insulation layer. The upper gate pattern may extend in a second horizontal direction substantially perpendicular to the first horizontal direction. The upper gate pattern may be connected to upper portions of the lower gate patterns.

Abstract: A first semiconductor pillar layer of a first conductivity type is formed on a main surface of a semiconductor substrate of the first conductivity type. A second semiconductor pillar layer of a second conductivity type is formed adjacent to the first semiconductor pillar layer. A third semiconductor pillar layer of the first conductivity type is formed adjacent to the second semiconductor pillar layer. A semiconductor base layer of the second conductivity type is formed on the main surface of the second semiconductor pillar layer. An insulated-gate type semiconductor element is formed in the semiconductor base layer. The carrier concentration on the side of a main surface of each of said first through third semiconductor pillar layers is higher than a carrier concentration on the opposite side of said main surface in each of said first through third semiconductor pillar layers.

Abstract: A vertical type semiconductor device includes: a silicon substrate having a first surface and a second surface; a first electrode disposed on the first surface of the silicon substrate; and a second electrode disposed on the second surface of the silicon substrate. Current is capable of flowing between the first electrode and the second electrode in a vertical direction of the silicon substrate. The second surface of the silicon substrate includes a re-crystallized silicon layer. The second electrode includes an aluminum film so that the aluminum film contacts the re-crystallized silicon layer with ohmic contact.

Abstract: A LDMOS transistor comprises a trench formed through the epitaxial layer at least to the top surface of the substrate, the trench having a bottom surface and a sidewall contacting the source region and the portion of the channel region extending under the source region. A first insulating layer is formed over the upper surface and sidewall surfaces of the conductive gate. A continuous layer of conductive material forming a source contact and a gate shield electrode is formed along the bottom surface and the sidewall of the trench and over the first insulating layer to cover the top and sidewall surfaces of the conductive gate. A second insulating layer is formed over an active area of the transistor, including over the continuous layer of conductive material and filling the trench. A drain electrode can extend over the second insulating layer to substantially cover the active area.

Abstract: Disclosed are a programmable, random logic device array, and a method of forming such a device. The device comprises a substrate, and a semiconductor layer above the substrate. That semiconductor layer, in turn, includes a first region of a first semiconductor type, an array of spaced apart second regions of a second semiconductor type, and a plurality of space-charge regions. Each of the space charge regions extends around a respective one of the second regions and separates that one of the second regions from the first region of the semiconductor layer. The programmable, random, logic device array further comprises first and second sets of contacts. The first set of contacts are in electrical contact with areas of said first region of the semiconductor layer, and the second set of contacts are in electrical contact with the second regions.

Abstract: A semiconductor device including a first semiconductor layer formed on a semiconductor substrate, a second semiconductor layer surrounding the first semiconductor layer, the second semiconductor layer being formed on the semiconductor substrate with one of an insulating film and a cavity, and a third semiconductor layer surrounding the second semiconductor layer, the third semiconductor layer being formed on the semiconductor substrate.

Abstract: Provided are an electrostatic discharge (ESD) protection device and a method for making such a device. In one example, the ESD protection device includes a Zener diode region formed in a substrate and an N-type metal oxide semiconductor (NMOS) device formed adjacent to the Zener diode region. The Zener diode region has two doped regions, a gate with a grounded potential positioned between the two doped regions, and two light doped drain (LDD) features formed in the substrate. One of the LDD features is positioned between each of the two doped regions and the gate. The NMOS device includes a source and a drain formed in the substrate and a second gate positioned between the source and the drain.

Abstract: An exemplary ESD protection circuit includes first and second sets of transistors and an ESD discharge transistor. Each of the transistors includes a source electrode, a drain electrode, and a gate electrode. The drain electrodes and gate electrodes of each of the transistors are connected to each other, and the source electrodes of the transistors are respectively connected to the drain electrodes of the next adjacent transistors in both sets of the transistors. The gate electrode of the ESD transistor, the source electrodes of last transistors of the first and second sets of the transistors are connected to each other, the source electrode of the ESD transistor is connected to the drain electrode of a first transistor of the first set of the transistors, and the drain electrode of the ESD transistor is connected to the drain electrode of a first transistor of the second set of the transistors.

Abstract: A semiconductor device includes a first doped region disposed on a first well in a semiconductor substrate; a second doped region disposed on a second well adjacent to the first well in the semiconductor substrate, the second doped region having a dopant density higher than that of the second well; and a gate structure overlying parts of the first and second wells for controlling a current flowing between the first and second doped regions. A first spacing distance from an interface between the second doped region and the second well to its closest edge of the gate structure is greater than 200 percent of a second spacing distance from a center point of second doped region to the edge of the gate structure, thereby increasing impedance against an electrostatic discharge (ESD) current flowing between the first and second doped regions during an ESD event.

Abstract: A transistor structure comprises a semiconductor element extending between a source zone and a drain zone, as well as three portions of gates disposed on different sides of the semiconductor element. Such a structure is especially compact and may be used as two or three transistors having independent respective functions. In particular, the structure may be used as a combination of a transistor with a logic or analog function, with one or two random access memory cells.

Abstract: A method for making a semiconductor device is described. That method comprises forming a dielectric layer on a substrate, and forming an impurity containing metal layer on the dielectric layer. A metal gate electrode is then formed from the impurity containing metal layer. Also described is a semiconductor device that comprises a metal gate electrode that is formed on a dielectric layer, which is formed on a substrate. The metal gate electrode includes a sufficient amount of an impurity to shift the workfunction of the metal gate electrode by at least about 0.1 eV.

Abstract: A semiconductor device provided with stable ESD protection capabilities, incorporating a transistor and a protective diode to form a power control IC. The semiconductor device includes a semiconductor substrate of a first conductivity type; a well region of a second conductivity type, formed in the semiconductor substrate; the transistor formed in the well region; a guard ring region of the second conductivity type having an impurity concentration higher than the well region, formed on the surface of the semiconductor substrate inside the periphery of, and spatially separated from the boundary of, the well region; a substrate pickup region of the first conductivity type having an impurity concentration higher than the semiconductor substrate, formed on the periphery of the well region in contact with the well region and the semiconductor substrate; and a thick oxide film formed on the surface of the semiconductor substrate between the guard ring region and the substrate pickup region.

Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate having a source region and a drain region, and a gate stack formed on the semiconductor substrate between and in contact with the source and drain regions. The gate stack includes, in sequential order from the substrate: a tunneling film; a first trapping material film doped with a first predetermined impurity, the first trapping material film having a higher dielectric constant than the nitride film (Si3N4); a first insulating film having a higher dielectric constant than a nitride film; and a gate electrode. Such a nonvolatile semiconductor memory device can effectively control the trap density according to the doping concentration, thereby increasing the write/erase speed of data at a low operating voltage.

Abstract: The present invention provides a back illuminated photodetector having a sufficiently small package as well as being capable of suppressing the scattering of to-be-detected light. A back illuminated photodiode 1 comprises an N-type semiconductor substrate 10, a P+-type doped semiconductor region 11, a recessed portion 12, and a coating layer 13. In the surface layer on the upper surface S1 side of the N-type semiconductor substrate 10 is formed the P+-type doped semiconductor region 11. In the rear surface S2 of the N-type semiconductor substrate 10 and in an area opposite the P+-type doped semiconductor region 11 is formed the recessed portion 12 that functions as an incident part for to-be-detected light. Also, on the rear surface S2 is provided the coating layer 13 for transmitting to-be-detected light that is made incident into the recessed portion 12.

Abstract: In one embodiment, a pair of sidewall passivated trench contacts is formed in a substrate to provide electrical contact to a sub-surface feature. A doped region is diffused between the pair of sidewall passivated trenches to provide low resistance contacts.

Abstract: A first insulation film, a first conductor film, and a cap are sequentially formed on a semiconductor substrate. The first insulation film, the first conductor film, and the cap, and the substrate are etched in the same pattern. A second insulation film is placed in that etched pattern. The cap is removed. A second conductor film is formed on the side face of the second insulation film.

Abstract: A power semiconductor device has a first region in which a transistor is formed, a third region in which a control element is formed, and a second region for separating the first region and the third region.

Abstract: The invention relates to a substrate for epitaxy, especially for preparation of nitride semiconductor layers. Invention covers a bulk nitride mono-crystal characterized in that it is a mono-crystal of gallium nitride and its cross-section in a plane perpendicular to c-axis of hexagonal lattice of gallium nitride has a surface area greater than 100 mm2, it is more than 1,0 ?m thick and its C-plane surface dislocation density is less than 106/cm2, while its volume is sufficient to produce at least one further-processable non-polar A-plane or M-plane plate having a surface area at least 100 mm2. More generally, the present invention covers a bulk nitride mono-crystal which is characterized in that it is a mono-crystal of gallium-containing nitride and its cross-section in a plane perpendicular to c-axis of hexagonal lattice of gallium-containing nitride has a surface area greater than 100 mm2, it is more 1,0-?m thick and its surface dislocation density is less than 106/cm2.

Abstract: The invention relates to an electronic component and a semiconductor wafer, and a method for producing them. The semiconductor wafer has strip-type separating regions. The separating regions are provided with through contacts in the direction of the rear side of the semiconductor wafer. The semiconductor chip separated from such a semiconductor wafer constitutes an electronic component with external contacts in the form of edge contacts. Such an electronic component of semiconductor chip size can be used in diverse ways.

Abstract: An array of grooves (23) is formed in a first side (12) of a wafer (10) during a wafer processing method. A back grinding tape (16) is adhered to the first side. An amount of material is removed from the second side (20) of the wafer. An adhesive layer (30) is applied to the second side. Dicing tape (24) is applied to the adhesive layer to create a first wafer assembly (32). The first wafer assembly is supported on a support surface (34) with the dicing tape facing the support surface and the back grinding tape exposed. The back grinding tape is removed and the adhesive layer is severed through the array of grooves to create individually removable die (28).

Abstract: An optical device having a high reflector tunable stress coating includes a micro-electromechanical system (MEMS) platform, a mirror disposed on the MEMS platform, and a multiple layer coating disposed on the mirror. The multiple layer coating includes a layer of silver (Ag), a layer of silicon dioxide (SiO2) deposited on the layer of Ag, a layer of intrinsic silicon (Si) deposited on the layer of SiO2, and a layer of silicon oxynitride (SiOxNy) deposited on the layer of Si. The concentration of nitrogen is increased and/or decreased to tune the stress (e.g., tensile, none, compressive).

Abstract: An integrated circuit package system including an integrated circuit die, a leadframe and an integrated circuit support. The integrated circuit support between the integrated circuit die and the leadframe with the electrical interconnects connected to the leadframe.

Abstract: Provided is a circuit device having conductive patterns which are equally spaced apart and a manufacturing method thereof. A method for manufacturing a circuit device of the present invention includes the steps of: preparing a conductive foil; forming conductive patterns, which are included in a unit having at least regions for mounting circuit elements, by forming isolation trenches having a uniform width in the conductive foil; electrically connecting the conductive patterns to the circuit elements; sealing with a sealing resin so as to cover the circuit elements and to be filled in the isolation trenches; and removing the conductive foil in its thickness portions where no isolation trenches are provided.

Abstract: An assembly device of an image sensor chip is disclosed. A flexible circuit has a die-attached portion, a plurality of bendable portions, and a plurality of bonding portions where the bendable portions extend from the die-attached portion and are connected to the corresponding bonding portions. A plurality of inner leads are formed on the bonding portions. An image sensor chip with bumps is attached to the die-attached portion. The bendable portions are so bent that the bonding portions are located above the image sensor chip. By thermocompression bonding, the inner leads of the flexible circuit are bonded to the bumps on the image sensor chip. In one embodiment, a transparent cover is adhered to the bonding portions and located above a sensing area of the image sensor chip.

Abstract: A semiconductor chip package has a pillar body including at least three conductors insulated from each other by an insulating layer. The pillar body has a periphery that includes a plurality of mounting faces, with each mounting face defined by two adjacent conductors separated by a portion of the insulating layer. A plurality of semiconductor chips are attached on the mounting faces and selectively and electrically connected to the conductors. The semiconductor package of the present invention can be used in a semiconductor illuminator which has a housing having a reflecting cup, with the pillar body positioned inside the reflecting cup.