Abstract: The present invention provides systems, devices and methods for controlling a desired output of an output device. These systems, devices and methods include connecting an electrical resistance element having a selected one of a plurality of resistance values with an electrical circuit portion having a plurality of electrical components, determining an electrical characteristic associated with the connected electrical circuit portion and the variable resistance element, and generating a control signal based on the electrical characteristic to control the desired output of the output device.

Abstract: A method of reducing noise induced from reference plane currents is disclosed. The method includes routing a first path for an electrical trace on a circuit board such that the first path references a voltage plane. The method further includes routing a second path for the electrical trace on the circuit board such that the second path references a ground plane whereby the second path is substantially similar to the first path. The method further includes electrically coupling the first path to the second path at each of the ends of the first and second paths such that noise induced into the electrical trace is reduced.

Abstract: A latch mechanism for an electronic device is secured to a base of the electronic device. The latch mechanism includes a latch lever including a pressing portion for being applied an external force along a first direction and at least one latch portion for clasping a cover of the electronic device, at least one fulcrum plate for being secured to the base, at least one lifting plate deflectably secured to the fulcrum plate, at least one first elastic member positioned between the latch lever and the fulcrum plate to provide a first restoration force along the first direction to the latch lever, and at least one second elastic member positioned between the fulcrum plate and the lifting plate to provide a second restoration force to a side of the lifting plate so as to make the other side of the lifting plate resist against the cover.

Abstract: An apparatus for mounting a card in an information handling system provides a first riser card including a plurality of first connections. A second riser card is coupled to the first riser card by a plurality of connectors, the second riser card including a plurality of second connections. A first card slot extends from the first riser card and is electrically coupled to the plurality of first connections, and a second card slot extends from the first riser card and is electrically coupled to the plurality of second connections. The apparatus may be coupled to an information handling system in a chassis to provide for the mounting of cards in the chassis.

Abstract: The present invention is associated with a power adapter capable of simultaneously providing a low-level DC voltage and a high-level DC voltage. The power adapter includes a transformer having a primary winding for storing energy when a main switch coupled therewith is turned on and transferring the stored energy to the secondary side of the transformer when the main switch is turned off. The transformer includes a first secondary winding and a second secondary winding connected in series with each other. A first rectifier/filter circuit is connected across the first secondary winding for generating a low-level DC voltage by rectifying and filtering the energy received by the first secondary winding, and a second rectifier/filter circuit is connected across the first secondary winding and the second secondary winding for generating a high-level DC voltage by rectifying and filtering the energy received by the first secondary winding and the second secondary winding.

Abstract: A switching mode power supply (SMPS) with an active load detection function which supplies AC power input to a primary coil of a transforming element, then to a secondary coil of the transforming element, and then rectifies and outputs the AC power is provided. The SMPS comprises a controlling unit for controlling switching frequency by changing the time constant of a switching unit depending on the current and reducing the amount of power supplied to the primary coil of the transforming element. The current at a terminal of a resistor can be controlled under a cross condition, and the current flowing to the resistor can be controlled when in a normal state, thereby preventing energy loss which always occur in the resistor. The switching frequency during a standby state can be reduced to reduce switching loss.

Abstract: This invention relates to a control circuit for the closed-loop control of an output voltage of a primary-controlled switched-mode power supply as well as an associated method. The switched-mode power supply comprises a primary-side switch and a transformer with at least one auxiliary winding in which an auxiliary voltage is induced after opening the primary-side switch. The voltage induced in the at least one auxiliary winding provides the basis for the measurement voltage passed to the control circuit and for the supply voltage of the control circuit. The invention also refers to an associated switched-mode power supply.

Abstract: A device corrects the power factor in forced switching power supplies and includes a converter and a control device to obtain a regulated voltage on an output terminal. The control device comprises an error amplifier having an inverting terminal (Vout) and a non-inverting terminal receiving a reference voltage. The device includes first and second resistances coupled in series with a conduction element positioned between the first resistance and the inverting terminal of the error amplifier and a fault detector suitable for detecting the electrical connection of the conduction element with the output terminal and suitable for detecting an output signal of the second resistance. The fault detector is suitable for supplying a malfunction signal upon detecting an electric disconnection of the conduction element from the output terminal or when the output signal of the second resistance tends to zero.

Abstract: A synchronous rectification circuit for power converters operable under fixed and/or variable frequencies where no current sense circuit or phase-lock circuit are needed is provided. It has a power switch coupled to a transformer for the rectification. A signal-generation circuit is used for generating a control signal in response to a magnetized voltage of the transformer, a demagnetized voltage of the transformer, and a magnetization period of the transformer. The control signal is coupled to turn on the power switch. The enable period of the control signal is correlated to a demagnetization period of the transformer.

Abstract: A circuit for controlling a switch to be controlled in unidirectional fashion while the voltage present thereacross is an A.C. Voltage, including circuitry for delaying the switch turning-on with respect to a zero crossing of the voltage thereacross, and circuitry for triggering the switch turning-off after its turning on, at the end of a predetermined time interval plus or minus an error time controlled by the duty cycle of the A.C. Voltage across the switch, in one or several previous periods. The control circuit applies to the forming of a rectifying circuit by the switch.

Abstract: A transformerless power conversion circuit is interconnected with an electric grid and converts an input DC power provided by a power generator into an AC power and feeding the AC power into the grid. The power conversion circuit includes a buck-boost converter converting the input DC power into two sets of DC power levels; and at least one half-bridge inverter converting the two sets of DC power levels into the AC power for feeding into the grid. The isolating transformer can be eliminated and the common ground problem for DC side and AC side is also solved. The power conversion circuit has significant improvement for device size, manufacture cost and conversion efficiency.

Abstract: A power module is adapted to be connected to a voltage source and to supply power to a load. The power module includes a switching bridge that includes a first power transistor and a second power transistor, a first gate controller for driving the first power transistor and a second gate controller for driving the second power transistor. The first gage controller includes a first gate transformer, and a leakage inductance of the first gate transformer forms a resonant circuit with an input capacitance of the first power transistor. The second gate controller includes a second gate transformer, and a leakage inductance of the second gate transformer forms a resonant circuit with an input capacitance of the second power transistor.

Abstract: An information storage device includes a ferroelectric layer having a first surface and a second surface opposite the first surface. A common electrode layer is formed on the first surface of the ferroelectric layer. At least two conductive track layers separated from each other are positioned on the second surface of the ferroelectric layer. A conductive roller that has two opposite ends supported by the conductive track layers is provided. The conductive roller is movable along a conductive track. A ferromagnetic layer creates a magnetic field on the conductive roller.

Abstract: A semiconductor memory device includes resistance memory elements that are coupled to selection transistors addressed by word lines and bit lines. The memory elements are read by read/write lines arranged parallel to the word lines. Two successive memory elements along a read/write line are coupled to selection transistors that are coupled to different word lines.

Abstract: A method and apparatus for multiple string searching using a ternary content addressable memory. The method includes receiving a text string having a plurality of characters and performing an unanchored search of a database of a stored patterns matching one or more characters of the text string using a state machine, wherein the state machine comprises a ternary content addressable memory (CAM) and wherein the performing comprises comparing a state and one of the plurality of characters with contents of a state field and a character field, respectively, stored in the ternary CAM. In various embodiments, one or more of the following search features may be supported: exact string matching, inexact string matching, single character wildcard matching, multiple character wildcard matching, case insensitive matching, parallel matching and rollback.

Abstract: A semiconductor storage device comprising a plurality of memory cells disposed in an array in the row and column directions and a bit line extending in the column direction of the memory cell or a word line extending in its row direction, which is disconnected in the middle of the array.

Abstract: A method for programming a one-time programmable memory of an integrated circuit includes the following steps: writing an instruction set into the one-time programmable memory via a first programmable interface, running a programmable self-instruction of the instruction set, and writing a proofreading value of the integrated circuit into the one-time programmable memory via a second programmable interface. The present method takes full advantage of the one-time programmable memory. Manufacturers for manufacturing integrated circuits don't write various proofreading values corresponding to different applications. A producing efficiency can be increased, and a producing cost can be decreased. The present integrated circuit needs not to be communicated with an addition storing device, so the present integrated circuit has a simple construction, and the cost can be decreased. Since the present integrated circuit can write perform a proofreading self-instruction, the producing cost can be decreased.

Abstract: This memory comprises a bit line, a first word line and a second word line arranged to intersect with the bit line while holding the bit line therebetween and a first ferroelectric film and a second ferroelectric film, having capacitances different from each other, arranged between the bit line and the first word line and between the bit line and the second word line respectively at least on a region where the bit line and the first and second word lines intersect with each other. The bit line, the first word line and the first ferroelectric film constitute a first ferroelectric capacitor while the bit line, the second word line and the second ferroelectric film constitute a second ferroelectric capacitor, and the first ferroelectric capacitor and the second ferroelectric capacitor constitute a memory cell.

Abstract: A phase-change random access memory device may include a phase-change pattern, a first electrode structure connected to the phase-change pattern, and a second electrode structure spaced apart from the first electrode structure and connected to the phase-change pattern, wherein at least one of the first electrode structure and the second electrode structure includes a plurality of resistor patterns connected to the phase-change pattern in parallel.

Abstract: A memory includes a sense amplifier segment and a plurality of word lines including a spare word line, a first transfer word line, and a second transfer word line complementary to the first transfer word line. The memory includes a plurality of bit lines coupled to the sense amplifier segment and a memory cell located at each cross point of each word line and each bit line. The first transfer word line and the second transfer word line are adapted for simultaneously inverting data bit values stored in memory cells along a failed word line to correct a parity error during self refresh.

Abstract: One aspect of this disclosure relates to a method for operating a memory cell. According to various embodiments, the method includes charging a storage node of the memory cell, including forward biasing a thyristor to switch the thyristor into a high conductance low impedance state, and storing a first charge type in the storage node and storing the first charge type in a trapping insulator separating a floating body of an access transistor from the thyristor. The method further includes discharging the storage node of the memory cell, including reverse biasing the thyristor into a low conductance high impedance state, and discharging the first charge type from the storage node and discharging the first charge type from the trapping insulator. Other aspects and embodiments are provided herein.

Abstract: A non-volatile memory cell includes a floating gate transistor having a floating gate coupled to a metal layer capacitor defined in one or more metal layers. Within each metal layer, the metal layer capacitor includes a first plate coupled to the floating gate and a second plate separated from the first plate by a fringe capacitance junction.

Abstract: A memory write timing system includes a modified memory bitcell including a storage device and a write/read circuit for writing/reading data to/from the storage device; and an output circuit for detecting the current state of the storage device.

Abstract: A two-port SRAM memory cell includes a pair of cross-coupled inverters coupled to storage nodes. An access transistor is coupled between each storage node and a write bit line and controlled by a write word line. The write word line is also coupled to a power supply terminal of the pair of cross-coupled inverters. During a write operation, the write word line is asserted. A voltage at the power supply terminal of the cross-coupled inverters follows the write word line voltage, thus making it easier for the stored logic state at the storage nodes to change, if necessary. At the end of the write operation, the write word line is de-asserted, allowing the cross-coupled inverters to function normally and hold the logic state of the storage node. Coupling the power supply node of the cross-coupled inverters allows faster write operations without harming cell stability.

Abstract: A MRAM includes: first wirings, second wirings, memory cells, a second sense amplifier and a first sense amplifier. The first wirings and second wirings are extended in a first and a second direction. The memory cells are placed correspondingly to positions where the first wirings are crossed with the second wirings. The second sense amplifier detects a state of a reference cell on the basis of an output from the reference cell provided by corresponding to a reference wiring. The first sense amplifier (2) detects a state of the memory cell on the basis of an output from the reference cell and an output from the memory cell. The memory cell includes a magnetic tunneling junction element having a laminated free layer. The magnetic tunneling junction element has a magnetization easy axis direction which is different from the first and second directions.

Abstract: A method, system and computer program product for resetting a phase change memory cell having a memory cell threshold voltage is disclosed. The method includes reading a resistance of the memory cell. If the resistance is larger than a chosen resistance, the resetting of the memory cell ends. Otherwise, the method proceeds by applying a voltage, larger than the memory cell threshold voltage, to the bit line, and applying a voltage VWL, larger than the access device threshold voltage, to the word line. The resistance of the memory cell is again read. If the resistance is larger than the chosen resistance, the resetting of the memory cell ends. Otherwise, the method proceeds by applying a voltage, larger than the memory cell threshold voltage, to the bit line, increasing voltage VWL by a voltage ?V and applying the increased voltage VWL to the word line.

Abstract: Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The memory cell's reset current can be double a set current, causing peak currents to depend on write data. When all data bits are reset to the amorphous state, a very high peak current is required. To reduce this worst-case peak current, the data is encoded before storage in the PCM cells. An 8/10 encoder adds 2 bits but ensures that no more than half of the data bits are reset. An 8/9 encoder adds an indicator bit, and inverts the 8 bits to ensure that no more than half of the bits are reset. The indicator bit indicates when the 8 bit are inverted, and when the 8 bits are un-inverted. Peak currents are thus reduced by encoding to reduce reset data bits.

Abstract: One aspect of the present subject matter relates to a memory cell, or more specifically, to a one-transistor SOI non-volatile memory cell. In various embodiments, the memory cell includes a substrate, a buried insulator layer formed on the substrate, and a transistor formed on the buried insulator layer. The transistor includes a floating body region that includes a charge trapping material. A memory state of the memory cell is determined by trapped charges or neutralized charges in the charge trapping material. The transistor further includes a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region. The transistor further includes a gate insulator layer formed over the channel region, and a gate formed over the gate insulator layer. Other aspects are provided herein.

Abstract: A system is disclosed for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the memory elements. For example, one implementation prevents or reduces boosting of the source side of the NAND string channel during a read process. Because the source side of the NAND string channel is not boosted, at least one form of read disturb is minimized or does not occur.

Abstract: A set non-volatile storage elements are subjected to a programming process in order to store a set of data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target condition to store the appropriate data. Decisions about whether to continue programming or whether the programming is successful are made based on whether overlapping groups of the non-volatile storage elements have less than a threshold number of non-volatile storage elements that are not properly programmed.

Abstract: A row decoder preventing leakage current and a semiconductor memory device including the same are provided. The row decoder includes an address decoder and a selection signal generator. The address decoder decodes a predetermined address signal and activates an enable signal. The selection signal generator electrically connects a boosted voltage node to an output node to activate a block selection signal when the enable signal is activated and electrically breaks a path between the boosted voltage node and the output node and a path between the boosted voltage node and a ground voltage node when the enable signal is deactivated. The selection signal generator includes a feedback circuit, a switch, and a direct current (DC) path breaker. The feedback circuit is electrically connected to the output node to generate an output voltage that varies with a voltage level of the block selection signal. The switch transmits the output voltage of the feedback circuit to the output node.

Abstract: A portion of a memory array has a string of two or more non-volatile memory cells, a first select gate coupled in series with one non-volatile memory cell of the string of two or more non-volatile memory cells, and a second select gate coupled in series with the first select gate. A length of the second select gate is greater than a length of the first select gate.

Abstract: Method and system for memory devices is provided. The system includes a plurality of non-volatile storage elements connected in a string between a source side element and a drain side element; a plurality of bit lines, wherein each bit line is connected to a plurality of non-volatile storage elements; and a plurality of word lines, the plurality of word lines include a dummy word line between a source side select element and a first word line that is connected to a first non-volatile storage element to be programmed, wherein a program voltage is applied to the first non-volatile storage element connected to the first word line and an intermediate voltage is applied to a second non-volatile storage element connected to the dummy word line.

Abstract: A method for operating a non-volatile storage system which reduces program disturb. Multiple boosting modes are implemented while programming non-volatile storage. For example, self-boosting, local self-boosting, erased area self-boosting and revised erased area self-boosting may be used. One or more switching criteria are used to determine when to switch to a different boosting mode. The boosting mode may be used to prevent program disturb in unselected NAND strings while storage elements are being programmed in selected NAND strings. By switching boosting modes, an optimal boosting mode can be used as conditions change. The boosting mode can be switched based on various criteria such as program pulse number, program pulse amplitude, program pass number, the position of a selected word line, whether coarse or fine programming is used, whether a storage element reaches a program condition and/or a number of program cycles of the non-volatile storage device.

Abstract: Shifts in the apparent charge stored on a floating gate (or other charge storage element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other charge storing elements). To account for this coupling, the read process for a targeted memory cell will provide compensation to an adjacent memory cell (or other memory cell) in order to reduce the coupling effect that the adjacent memory cell has on the targeted memory cell. The compensation applied is based on a condition of the adjacent memory cell. To apply the correct compensation, the read process will at least partially intermix read operations for the adjacent memory cell with read operations for the targeted memory cell.

Abstract: A memory cell stores several data using n (n: natural number more than 1) threshold voltages. A voltage supply circuit supplies a predetermined voltage to a gate of the memory cell in a verify operation of verifying whether or not the memory cell reaches a predetermined threshold voltage. A detection circuit connected to one terminal of the memory cell charges one terminal of the memory cell to a predetermined potential. The detection circuit detects the voltage of one terminal of the memory cell based on a first detection timing, and further, detects the voltage of one terminal of the memory cell based on a second detection timing.

Abstract: Non-volatile storage elements are programmed in a manner that reduces program disturb, particularly at the edges storage elements strings, by using modified pass voltages. In particular, during the programming of a selected storage element, an isolation voltage is applied to a storage element proximate to the selected storage element thereby electrically dividing the channel associated with the storage elements into two isolated areas. Additional isolated areas are formed remotely from the selected storage element by applying the isolation voltage to other remote storage elements. The isolated channel regions associated with the storage elements are then boosted with different pass voltages in order to alleviate the effects of program disturb. Thus, a standard pass voltage is applied to storage elements immediately adjacent to the selected storage element, and a lower pass voltage is applied to storage elements remote from the selected storage element.

Abstract: A non-volatile storage device in which power consumption is reduced by providing reduced read pass voltages on unselected word lines during a read operation. A programming status of one or more unselected word lines which are after a selected word line on which storage elements are being read is checked to determine whether the unselected word lines contain programmed storage elements. When an unprogrammed word line is identified, reduced read pass voltages are provided on that word line and other word lines which are after that word line in a programming order. The programming status can be determined by a flag stored in the word line, for instance, or by reading the word line at the lowest read state. The unselected word lines which are checked can be predetermined in a set of word lines, or determined adaptively based on a position of the selected word line.

Abstract: A method of reducing gate disturb in a charge-trapping layer memory cell by applying different Vpass voltages to different sides of a selected wordline. A higher Vpass voltage is used to pass higher source/drain voltage and a lower Vpass voltage is used to pass a lower source/drain voltage. By controlling the Vpass voltages on different sides of a selected wordline, it is possible to reduce a vertical field that is established in a gate region when the Vpass voltages are applied. A reduced vertical field results in suppressed gate disturb. The method also includes a novel bit-line biasing scheme that may further reduce the vertical field and thereby may further suppress gate disturb, particularly in an array of memory cells.

Abstract: This disclosure concerns a semiconductor memory including memory cells; a first dummy cell and a second dummy cell generating a reference potential and storing first data and second data of mutually opposite polarities, respectively; word lines; a first and a second dummy word lines connected to gates of the first and the second dummy cells; a pair of bit lines; and a sense amplifier provided for the pair of bit lines, the sense amplifier detecting the first data using the second data as a reference or detecting the second data using the first data as a reference in a refresh operation of the first and the second dummy cells.

Abstract: A reference cell outputs a reference current of a data reading current of a memory cell. A trimming data in accordance with the reference current is memorized in a non-volatile memory cell. A standard current generator outputs a standard current whose current quantity is adjusted in accordance with the trimming data. A current comparator compares the standard current to the reference current. The output of the reference current from the reference cell is adjusted through a reference cell adjuster based on a result of the comparison by the current comparator.

Abstract: When performing a data sensing operation, including a verify operation during programming of non-volatile storage elements (or, in some cases, during a read operation after programming), a first voltage is used for unselected word lines that have been subjected to a programming operation and a second voltage is used for unselected word lines that have not been subjected to a programming operation. In some embodiments, the second voltage is lower than the first voltage.

Abstract: A sense amplifier for multiple level flash memory cells is comprised of a voltage ramp generator that generates a ramp voltage signal. Reference sense amplifiers compare an input reference current to a ramp current generated from the ramp voltage signal. When the ramp voltage signal is greater than the reference current, an output latch signal is toggled. A sense amplifier compares an input bit line current to a threshold and outputs a logical low when the bit line current goes over the threshold. The sense amplifier output is latched into one of three digital latches at a time determined by the latch signals. An encoder encodes the data from the three digital latches into two bits of output data.

Abstract: The present invention determines or identifies programming variations for different groups within an array or memory device that properly program memory cells within the respective groups. Then, during programming operations for a given memory cell, programming voltages are applied according to the determined or identified programming variations for the group to which the given memory cell belongs. These adjusted programming variations facilitate successful programming of the particular memory cell.

Abstract: A memory cell having three transistors and a capacitor having metallic electrodes is described. Multiple memory cells may be arranged in a memory unit or array. Collective electrodes may be used in a space-saving embodiment of the capacitor.

Abstract: A memory includes a plurality of lower level bit lines, a higher level bit line, and bit line driving circuitry. The bit line driving circuitry includes a plurality of bit line inputs, each bit line input coupled to a corresponding one of the plurality of lower level bit lines. The bit line driving circuitry further includes a first select input to receive a first select value, a second select input to receive a second select value, and an output configured to drive a select one of first bit value or a second bit value at the third bit line based on the first select value and the second select value and a bit value of at least one of the plurality of lower level bit lines.

Abstract: A memory device having a number of terminals for transferring input data and output data to and from a memory array. The memory device includes an auxiliary circuit for receiving input auxiliary information associated with the input data and for generating output auxiliary information associated with the output data. The input and output auxiliary information include inverting codes, parity codes, temperature information, and time delay information. The input and output auxiliary information are transferred to and from the memory device on the same terminals that the input data and the output data are transferred.

Abstract: A memory card (1) includes an electrically rewritable non-volatile memory (4), a data processor (3) having a function of executing instructions, and managing the allocation of file data in the non-volatile memory, an interface control circuit (2) having a function of establishing an external interface, for controlling the execution of instructions by the data processor in response to external commands and for controlling access to the non-volatile memory and a buffer memory (7) for temporarily storing the file data. The interface control circuit includes command control means for decoding a first command externally supplied and for instructing the data processor to fetch an instruction from the buffer memory and to operate.

Abstract: A memory control circuit that controls m (=L/k) memories (first to mth memories), each of which has a k-bit width, the m memories storing data having a data width (D bits) of an integral multiple of k bits up to L bits, the circuit comprising: an address input circuit that determines a memory (nth memory) storing a first k bits of the data among the m memories, based on a start-position specification address which is a predetermined j bits of an A-bit address indicating a storage destination of the data, and inputs to the nth to mth memories a first specification address for specifying a storage destination of the data, the first specification address being an A-j bits of the A-bit address, which is the A-bit address without the predetermined j bits thereof, and inputs to the first to (n?1)th memories a second specification address obtained by adding one to the first specification address; a data input circuit that inputs a plurality of pieces of divided data obtained by dividing the data into k-bit data to t

Abstract: This invention relates to an MRAM array architecture which incorporates certain advantages from both cross-point and 1T-1MTJ architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of MRAM cells each column being provided in a respective stacked memory layer.