Abstract: An object is to provide a structure for forming a circuit for which high-speed operation and low-voltage operation are required and a circuit for which sufficient reliability is required at the time of high voltage application in a circuit group provided over one substrate in a semiconductor device, and a manufacturing method thereof. A semiconductor device is provided with a plurality of kinds of transistors which include single-crystal semiconductor layers with different thicknesses, which are separated from a single-crystal semiconductor substrate and bonded, over one substrate. The single-crystal semiconductor layer of a transistor for which high-speed operation is required is formed thinner than that of a transistor for which high resistance to a voltage is required, so that the thickness of the single-crystal semiconductor layer is made to be thin.

Abstract: A semiconductor device packaged in three dimensions comprises a first thin film device, a second thin film device, and a third thin film device, each of the first, second, and third thin film devices comprising a first insulating film, a first electrode formed over the first insulating film, a second insulating film formed over the first electrode, first and second thin film transistors formed over the second insulating film, wherein the first thin film transistor is connected to the first electrode through a first contact hole, a third insulating film formed over the first and second thin film transistor, a second electrode formed over the third insulating film, wherein the second electrode is connected to the second thin film transistor through a second contact hole, and a fourth insulating film formed over the third insulating film and the second electrode.

Abstract: A non-volatile semiconductor storage device includes a substrate, a first insulating layer formed on the substrate, a semiconductor layer formed of polysilicon on the first insulating layer, a pair of conductor regions formed on the first insulating layer to pass through the semiconductor layer and to sandwich a part of the semiconductor layer, and formed of a metal or a silicide, a tunnel layer formed on the part of the semiconductor layer sandwiched between the pair of conductor regions, a charge storage layer formed on the tunnel layer, a second insulating layer formed on the charge storage layer, and a control gate formed on the second insulating layer.

Abstract: The present invention relates to a thin film transistor device formed on an insulating substrate of a liquid crystal display device and others, a method of manufacturing the same, and a liquid crystal display device. In structure, there are provided the steps of forming a negative photoresist film on a first insulating film for covering a first island-like semiconductor film, forming a resist mask that has an opening portion in an inner region with respect to a periphery of the first island-like semiconductor film by exposing/developing the negative photoresist film from a back surface side of a transparent substrate, etching the first insulating film in the opening portion of the resist mask, forming a second insulating film for covering the first insulating film and a conductive film thereon, and forming a first gate electrode and a second gate electrode by patterning the conductive film.

Abstract: In forming a TFT and a storage capacitance element, whereas sharing with each other the conductive film and the insulation film, which are components of the TFT and the storage capacitance element, contributes to improving production efficiency, it is difficult to obtain a storage capacitance element that is optimized independently of the TFT. A TFT substrate provided with a TFT and a storage-capacitance element according to the present invention is characterized in that the storage-capacitance element is obtained that includes an electrically conductive film and an insulation film each being different from those used in the TFT. Furthermore, in order to form such a structure, a method of manufacturing the TFT substrate is provided that achieves both flexibility in design and efficiency in production without need for addition of any photolithography processes.

Abstract: A method for making a semiconductor apparatus including the steps of: forming a laminate structure of an insulating film made of a metal oxide and a semiconductor thin film on a substrate; forming a light absorption layer on top of the laminate structure; and irradiating an energy beam of a wavelength capable of being absorbed by the light absorption layer on the light absorption layer and simultaneously crystallizing the insulating film and the semiconductor thin film by means of heat generated in the light absorption layer.

Abstract: A method of receiving video data, a control signal, etc. via a non-contact transmission path is adopted, and a receiving circuit for receiving and amplifying a signal is formed on the same insulating substrate as a display device. Thus, there are provided a thin-film transistor which is formed in a semiconductor thin film that is formed on the insulating substrate and crystallized in a predetermined direction, and an inductor for forming an inductive-coupling circuit, which is formed by using an electrically conductive thin film provided on the insulating substrate. The direction of movement of carriers flowing in the thin-film transistor is parallel to the direction of crystallization of the semiconductor thin film, and the inductor and the thin-film transistor are integrated so as to be electrically coupled directly or indirectly.

Abstract: An opening for forming a gate electrode is provided by a first photoresist pattern formed on an insulating film. Reactive ion etching by inductively coupled plasma is applied to the insulating film through the first photoresist pattern as a mask to thereby expose the surface of a GaN semiconductor layer, evaporating thereon a gate metal such as NiAu, thereby forming the gate electrode by self-aligned process. This prevents an oxidized film from being formed on the surface of the semiconductor layer. After the gate electrode is formed, a second photoresist pattern is formed to form a field plate on the gate electrode and the insulating film through the second photoresist pattern as a mask. Thereby, Ti having a high adhesiveness with an insulating film made of SiN or the like can be used as a field plate metal.

Abstract: A silicon carbide semiconductor device having a MOS structure includes: a substrate; a channel area in the substrate; a first impurity area; a second impurity area; a gate insulating film on the channel area; and a gate on the gate insulating film. The channel area provides an electric current path. The channel area and the gate insulating film have an interface therebetween. The interface includes a dangling bond, which is terminated by a hydrogen atom or a hydroxyl. The interface has a hydrogen concentration equal to or larger than 2.6×1020 cm?3.

Abstract: Disclosed herein is a method for growing a semiconductor layer which includes the step of growing a semiconductor layer of hexagonal crystal structure having the (11-22) or (10-13) plane direction on the (1-100) plane of a substrate of hexagonal crystal structure.

Abstract: An integrated circuit package includes an angled one-piece substrate having a light source fixed to one area and a sensor die fixed to a second area, such that the light source is directed to illuminate the field of view of the sensor die when a surface of interest is imaged. The integrated circuit package is well suited for generating navigation information regarding movement relative to a surface. In one method of forming the integrated circuit package, the single-piece substrate is originally a generally flat lead frame to which the sensor die and light source are attached. After the components have been connected, the lead frame is bent to provide the desired light source-to-sensor angle. In an alternative method, the lead frame is pre-bent. For either method, optics may be connected to the integrated circuit package, thereby providing a module that includes the optics, the light source, the sensor and the packaging body.

Abstract: A plurality of rectangle semiconductor substrates are attached to a single mother glass substrate. A pixel structure is determined so that even if a gap or a an overlapping portion is generated in a boundary between a plurality of semiconductor substrates, a single-crystal semiconductor layer does not overlap with the gap or the overlapping portion. Two TFTs are located in a first unit cell including the first light emitting element, four TFTs are located in a second unit cell including the second light emitting element, and no TFT is located in a third unit cell including the third light emitting element. A boundary line is between the third unit cell and a fourth unit cell.

Abstract: A LED device formed of LED chips bonded to an exoergic member by the LED chips being bonded to an Au—Sn alloy layer formed on an upper surface of the exoergic member with columnar crystals being formed within the Au—Sn alloy layer extending in a direction perpendicular to the upper surface of the exoergic member. The method of producing the LED device forms an Sn film directly on the upper surface of the exoergic member, an Au film on a lower surface of the LED chips, mounts the LED chips with the Au film thereon onto the Sn film formed on the upper surface of the exoergic member, and the exoergic member with LED chips mounted thereon is heated in an atmosphere in which a forming gas flows, so that the LED chips are bonded to the exoergic member.

Abstract: It is an object of the present invention to provide a gallium nitride-based compound semiconductor light-emitting device which has a highly reflective positive electrode that has high reverse voltage and excellent reliability with low contact resistance to the p-type gallium nitride-based compound semiconductor layer. The inventive reflective positive electrode for a semiconductor light-emitting device comprises a contact metal layer adjoining a p-type semiconductor layer, and a reflective layer on the contact metal layer, wherein the contact metal layer is formed of a platinum group metal or an alloy containing a platinum group metal, and the reflective layer is formed of at least one metal selected from the group consisting of Ag, Al, and alloys containing at least one of Ag and Al.

Abstract: GaN substrate (30) whose growth plane (30a) is oriented off-axis with respect to either the m-plane or the a-plane. That is, in the GaN substrate (30), the growth plane (30a) is either an m-plane or an a-plane that has been misoriented. Inasmuch as the m-plane and the a-plane are nonpolar, utilizing the GaN substrate (30) to fabricate a semiconductor light-emitting device (60) averts the influence of piezoelectric fields, making it possible to realize superior emission efficiency. Imparting to the growth plane the off-axis angle in terms of either the m-plane or the a-plane realizes high-quality morphology in crystal grown on the substrate. Utilizing the GaN substrate to fabricate semiconductor light-emitting devices enables as a result the realization of further improved emission efficiency.

Abstract: A light-emitting device and a method to from the device are is described. The device described herein may realize the transversely single mode operation by the buried mesa configuration even when the active layer contains aluminum. The method provides a step to form the mesa on a semiconductor substrate with an average dislocation density of 500 to 5000 cm?2, a step to form a protection layer, which prevents the active layer from oxidizing, at least on a side of the active layer, and a step to from a blocking layer so as to cover the protection layer and to bury the mesa.

Abstract: The light-emitting diode is a light-emitting diode including a light-converting material substrate and a semiconductor layer formed on the light-converting material substrate, wherein the light-converting material substrate includes a solidified body in which at least two or more oxide phases selected from a simple oxide and a complex oxide are formed continuously and three-dimensionally entangled with each other, at least one oxide phase in the solidified body comprises a metal element capable of emitting fluorescence, and the semiconductor layer includes a plurality of compound semiconductor layers and has at least a light-emitting layer capable of emitting visible light.

Abstract: A light emitting diode device layer structure including a p-type contact layer that contains at least some indium (In), wherein the p-type contact layer is a not-intentionally doped strained nitride contact layer.

Abstract: An optoelectronic thin-film chip is specified, comprising at least one radiation-emitting region (8) in an active zone (7) of a thin-film layer (2) and a lens (10, 12) disposed downstream of the radiation-emitting region (8). The lens is formed by at least one partial region of the thin-film layer (2), the lateral extent (?) of the lens (10, 12) being greater than the lateral extent of the radiation-emitting region (?). A method for producing such an optoelectronic thin-film chip is furthermore specified.

Abstract: A method for manufacturing a light-emitting diode (LED) module is provided. Plural LED package structures are formed on a substrate first. A space is located between two adjacent LED package structures. A Lens laminated plate is subsequently bonded to the LED package structures. The lens laminated plate includes plural lenses, and each lens is located right above a LED of each LED package structure. Finally, plural LED modules are formed by cutting the substrate along the space. A LED module structure is also disclosed.

Abstract: The present invention provides a light-emitting diode-converted phosphor compound having the following chemical formula: (M1-m-nCemEun)2BO3X wherein M is at least one element selected from the group consisting of Ca, Sr and Ba, X is at least one element selected from the group consisting of Cl and Br, 0?m?0.5, and 0?n?0.5.

Abstract: A light-emitting diode includes: a light-emitting structure, a transparent electrically conductive thick film, a first electrical contact and a second electrical contact. The light-emitting structure includes a first-type cladding layer, a second-type cladding layer, and an active layer sandwiched between the first-type cladding layer and the second-type cladding layer. The transparent electrically conductive thick film is formed on the first-type cladding layer. The first electrical contact is located on the transparent electrically conductive thick film. The second electrical contact is located on the second-type cladding layer. The transparent electrically conductive thick film is made from a metal-doped metal oxide.

Abstract: A light-emitting diode (LED) apparatus includes an epitaxial multilayer, a micro/nano rugged layer and an anti-reflection layer. The epitaxial multilayer has a first semiconductor layer, an active layer and a second semiconductor layer in sequence. The micro/nano rugged layer is disposed on the first semiconductor layer of the epitaxial multilayer. The anti-reflection layer is disposed on the micro/nano rugged layer. In addition, a manufacturing method of the LED apparatus is also disclosed.

Abstract: A light emitting device includes an emission portion, an optical control portion for reflecting or refracting light emitted from the emission portion in a predetermined direction, a light guiding member including a light input surface to which the reflected or refracted light is inputted, a refection region formed on a surface thereof for reflecting the inputted light, and a light output surface for externally outputting the reflected light from the refection region, a reflection portion, on which the emission portion is mounted and which covers externally the refection region, for dissipating heat generated from the emission portion and for reflecting light passing through the refection region in a direction of the light output surface, and a space formed between the light guiding member and the reflection portion.

Abstract: A light emitting die package and a method of manufacturing the die package are disclosed. The die package includes a leadframe, at least one light emitting device (LED), a molded body, and a lens. The leadframe includes a plurality of leads and has a top side and a bottom side. A portion of the leadframe defines a mounting pad. The LED device is mounted on the mounting pad. The molded body is integrated with portions of the leadframe and defines an opening on the top side of the leadframe, the opening surrounding the mounting pad. The molded body further includes latches on the bottom side of the leadframe. The lens is coupled to the molded body. A composite lens is used as both reflector and imaging tool to collect and direct light emitted by LED(s) for desired spectral and luminous performance.

Abstract: A side-emission type semiconductor light-emitting device 10 includes a substrate 12, and the substrate 12 is provided with a case 14 formed of a resin having opacity and reflectivity. The substrate 12 is formed, on its surface, with electrodes 18a and 18b onto which an LED chip 20 is bonded. A transparent or translucent resin 16 is charged between the substrate 12 and the case 14 whereby the LED chip 20 is molded. A light-emitting surface of the side-emission type semiconductor light-emitting device 10 includes surfaces 16a, 16b and a surface opposite to the surface 16b which are formed of the transparent or translucent resin 16. Furthermore, the light-emitting surface is formed by a roughened surface. Due to this, a light outputted from the LED chip and a light reflected from the case 14 is scattered by the light-emitting surface.

Abstract: In order to emit a light from an electrode side, in semiconductor light emitting devices such as LED and the like, and liquid crystal, the electrode is formed of a transparent material so as to transmit a light through the transparent electrode and exit the light. A ZnO, which constitutes a material for the transparent electrode, is subject to erosion by acid and alkali, thus, as the case may cause loss of a reliability of the electrode under the influence of ion-containing moisture. In order to solve such a problem, this invention has as its aim a transparent electrode film provided with stability capable of preventing any degradation under the influence of any ion-containing moisture, while being kept acid-proof and alkali-proof. In order to accomplish the above-mentioned aim, this invention provides a transparent electrode made up of a ZnO as its main material, wherein its surface is covered with a Mg-doped ZnO film.

Abstract: Solid state light emitting devices include a solid state light emitting die and a light conversion structure. The light conversion structure may include a single crystal phosphor and may be on a light emitting surface of the solid state light emitting die. The light conversion structure may be attached to the light emitting surface of the solid state light emitting die via an adhesive layer. The light conversion structure may also be directly on a light emitting surface of the solid state light emitting die. Related methods are also disclosed.

Abstract: The present invention relates a III-nitride compound semiconductor light emitting device in which a first layer composed of a carbon-containing compound layer, such as an n-type or p-type silicon carbide (SiC), silicon carbon nitride (SiCN) or carbon nitride layer (CN) layer, is formed on the p-type III-nitride semiconductor layer of the existing III-nitride semiconductor light emitting device, and a second layer composed of a III-nitride semiconductor layer with a given thickness is formed on the first layer.

Abstract: In a method for producing a nitride semiconductor light-emitting device according to the present invention, first, a nitride semiconductor substrate having groove portions formed is prepared. An underlying layer comprising nitride semiconductor is formed on the nitride semiconductor substrate including the side walls of the groove portions, in such a manner that the underlying layer has a crystal surface in each of the groove portions and the crystal surface is tilted at an angle of from 53.5° to 63.4° with respect to the surface of the substrate. Over the underlying layer, a light-emitting-device structure composed of a lower cladding layer containing Al, an active layer, and an upper cladding layer containing Al is formed. According to the present invention, thickness nonuniformity and lack of surface flatness, which occur when accumulating a layer with light-emitting-device structure of nitride semiconductor over the nitride semiconductor substrate, are alleviated while inhibiting occurrence of cracking.

Abstract: A fourth semiconductor region of a first conduction type is provided in a partial region of a third semiconductor region of a second conduction type. This configuration enhances the blocking voltage at the time when the sheet carrier concentration of a fifth semiconductor region is enhanced.

Abstract: A semiconductor device includes a first layer having a first conductivity type, a second layer having a second conductivity type, a third layer having the second conductivity type, one or more first zones having the first conductivity type and located within the second layer, wherein each one of the one or more first zones is adjacent to the third layer, and one or more second zones having the second conductivity type and located within the second layer, wherein each one of the one or more second zones is adjacent to one or more of the one or more first zones.

Abstract: A method for manufacturing a semiconductor light emitting device, which is capable of providing high characteristic homogeneity and reproducibility, is disclosed. The disclosed method includes forming a buffer layer over a substrate, selectively growing a nitride crystal layer on the buffer layer, forming a nitride semiconductor layer having a multilayer structure over the nitride crystal layer, forming a first electrode on the nitride semiconductor layer, attaching an auxiliary substrate to the first electrode, separating the substrate from the nitride crystal layer, forming a second electrode on the nitride crystal layer exposed in accordance with the separation of the substrate, and removing the auxiliary substrate from the first electrode.

Abstract: A HEMT-type field-effect semiconductor device has a main semiconductor region comprising two layers of dissimilar materials such that a two-dimensional electron gas layer is generated along the heterojunction between the two layers. A source and a drain electrode are placed in spaced positions on the main semiconductor region. Between these electrodes, with spacings therefrom, an insulator is provided with is made from a material capable of developing a stress to reduce carrier concentration in neighboring part of the two-dimensional electron gas layer, creating a discontinuity in this layer. A gate electrode overlies the insulator via a piezoelectric layer which is made from a material capable of developing, in response to a voltage applied to the gate electrode, a stress for canceling out the stress developed by the insulator.

Abstract: A semiconductor integrated circuit having a substantially rectangular standard cell divided by first borderlines opposed to other standard cells longitudinally adjacent to the standard cell and second borderlines opposed to other standard cells laterally adjacent to the standard cell, the standard cell has: a p-type MOS transistor having first diffused regions and a first gate electrode; an n-type MOS transistor having second diffused regions and a second gate electrode with STI disposed for device isolation between the n-type MOS transistor and the p-type MOS transistor substantially in parallel with the first borderlines; dummy p-type MOS transistors having third gate electrodes disposed on the second borderlines so as to be adjacent to the first diffused regions of the p-type MOS transistor, the third gate electrodes being connected to power supply wiring so as to turn off the dummy p-type MOS transistors; and dummy n-type MOS transistors having fourth gate electrodes disposed on the second borderlines so

Abstract: Provided are a first wiring layer where each of the first, second internally present wirings can be selectively connected to the first and the second externally extended wirings, and a second wiring layer that has substantially the same structure as that of the first wiring layer. There is further provided an interlayer contact layer which arbitrarily connects one of the first and the second internally present wirings on the first wiring layer to one of the first, second internally present wirings on the second wiring layer, and connects the remainder of the first and the second internally present wirings on the first wiring layer to the remainder of the first and the second internally present wirings on the second wiring layer.

Abstract: A semiconductor device has a first semiconductor layer including a first circuit, a second semiconductor layer disposed on the first semiconductor layer and having a second circuit, and a via extending through portions of the first and second semiconductor layers and by which the first and second circuits are electrically connected. One of the circuits is a logic circuit and the other of the circuits is a memory circuit. The semiconductor device is manufactured by fabricating transistors of the logic and memory circuits on respective substrates, stacking the substrates, and electrically connecting the logic and memory circuits with a via.

Abstract: The present invention provides a field-effect transistor and method for the fabrication of a field-effect transistor by deposition on a substrate (480), which method comprises a wet chemical deposition of materials that react to form a semi-conducting material. The materials deposited include cadmium, zinc, lead, tin, bismuth, antimony, indium, copper or mercury. The wet chemical deposition may be by chemical bath deposition or spray pyrolysis. A vacuum deposition process is not required.

Abstract: A high-sensitivity field effect transistor using as a channel ultrafine fiber elements such as carbon nanotube, and a biosensor using it. The field effect transistor comprises a substrate, a source electrode and a drain electrode arranged on the substrate, a channel for electrically connecting the source electrode with the drain electrode, and a gate electrode causing polarization due to the movement of free electrons in the substrate. For example, the substrate has a support substrate consisting of semiconductor or metal, a first insulating film formed on a first surface of the support substrate, and a second insulating film formed on a second surface of the support substrate, the source electrode, the drain electrode, and the channel arranged on the first insulating film, the gate electrode disposed on the second insulating film.

Abstract: Noise occurring in a circuit is more accurately detected. A low-pass filter (11) is connected to a power supply line for a power supply terminal (VDD), and noise in the power supply line is removed to generate and output a referential voltage (V0). A high-pass filter (12) is connected to a power supply line, and a noise signal in the power supply line is passed with the referential voltage (V0) as a reference. A high-pass filter (13) is connected to a ground line for a ground terminal (GND), and a noise signal in the ground line is passed based on the referential voltage (V0) as a reference. A reference voltage generation circuit (14) generates and outputs a reference voltage (Vref) based on the referential voltage (V0) as a reference. Comparison circuits (CMP1 and CMP2) respectively compare output voltage of the high-pass filters (12 and 13) and the reference voltage (Vref).

Abstract: Semiconductor device comprising at least: one substrate, a transistor comprising at least one source region, one drain region, one channel and one gate, a planar layer based on at least one piezoelectric material, resting at least on the gate and capable of inducing at least mechanical strain on the transistor channel, in a direction that is substantially perpendicular to the plane of a face of the piezoelectric layer situated on the gate side, piezoelectric layer being arranged between two biasing electrodes, one of the two biasing electrodes being formed by a first layer based on at least one electrically conductive material such that the piezoelectric layer is arranged between this first conductive layer and the gate of the transistor.

Abstract: Various apparatus and methods of monitoring endcap pullback are disclosed. In one aspect, an apparatus is provided that includes a substrate that has a plurality of semiconductor regions. Each of the plurality of semiconductor regions has a border with an insulating structure. A transistor is positioned in each of the plurality of semiconductor regions. Each of the transistors includes a gate that has a first lateral dimension and an end that has a position relative to its border. A voltage source is electrically coupled to the transistors whereby levels of currents flowing through the transistors are indicative of the positions of the ends of the gates relative to their borders.

Abstract: A transistor having a gate dielectric layer of partial thickness difference and a method of fabricating the same are provided. The method includes forming a gate dielectric layer having a main portion with a relatively thin thickness formed on a semiconductor substrate, and a sidewall portion with a relatively thick thickness formed on both sides of the main portion. A first gate is formed overlapping the main portion of the gate dielectric layer, and forming a second gate layer covering the sidewall portion of the gate dielectric layer and covering the first gate. The second gate layer is etched, thereby forming second gates patterned with a spacer shape on sidewalls of the first gate. The exposed sidewall portion of the gate dielectric layer is selectively etched using the second gates as a mask, thereby forming a pattern of the gate dielectric layer to be aligned with the second gates. A source/drain is formed in a portion of the semiconductor substrate exposed by the second gates.

Abstract: An active pixel sensor in a p-type semiconductor body includes an n-type common node formed below a pinning region. A plurality of n-type blue detectors more lightly doped than the common node are disposed below pinning regions and are spaced apart from the common node forming channels below blue color-select gates. A buried green photocollector is coupled to the surface through a first deep contact spaced apart from the common node forming a channel below a green color-select gate. A red photocollector buried deeper than the green photocollector is coupled to the surface through a second deep contact spaced apart from the common node forming a channel below a red color-select gate. A reset-transistor has a source disposed over and in contact with the common node. A source-follower transistor has gate coupled to the common node, a drain coupled to a power-supply node, and a source forming a pixel-sensor output.

Abstract: An image sensor according to one embodiment of the present invention includes a semiconductor substrate having a CMOS circuit formed therein; an interlayer dielectric layer formed on the semiconductor substrate and including a trench formed therein; a metal wiring and a first conductive layer formed within the trench of the interlayer dielectric layer; an intrinsic layer formed on the semiconductor substrate including the first conductive layer and the interlayer dielectric layer; and a second conductive layer formed on the intrinsic layer.

Abstract: A semiconductor device includes: a compound semiconductor substrate; a buffer layer, a channel layer, and a Schottky junction forming layer sequentially formed on the compound semiconductor substrate, the buffer layer, the channel layer, and the Schottky junction forming layer each being a compound semiconductor; a source electrode and a drain electrode located on the Schottky junction forming layer; and a gate electrode disposed between the source and drain electrodes and forming a Schottky junction with the Schottky junction forming layer. The carrier density in the channel layer is inversely proportional to the third power of depth into the channel layer from a top surface of the channel layer, the channel layer has a uniform sheet carrier density, and the top surface of the channel layer has a dopant concentration in a range from 5.0×1017 cm?3 to 2.0×1018 cm?3.

Abstract: An image sensor and a method for manufacturing the same are provided. The image sensor can include transistor circuitry on a substrate, and a photodiode arranged above the transistor circuitry. The photodiode can include carbon nanotubes and a conductive polymer layer on the carbon nanotubes. A transparent conducting electrode can be provided on the carbon nanotubes.

Abstract: A CMOS image device comprises a pixel array region including a photo diode region, a floating diffusion region, and at least one MOS transistor having a gate and a junction region, a CMOS logic region disposed around the pixel array region, the CMOS logic region including a plurality of nMOS transistors and pMOS transistors, and contact studs formed on the floating diffusion region and the junction region in the pixel array region, the contact studs comprising impurity-doped polysilicon layers.

Abstract: A pixel of an image sensor, the pixel includes a floating diffusion node to sense photo-generated charge, a reset diode to reset the floating diffusion node in response to a reset signal, and a set diode to set the floating diffusion node.

Abstract: A pixel and a pixel array of an image sensor device of the present invention have small pixel sizes by resetting sensed charge using a diode built vertically above a substrate. The pixel and the pixel array also have low noise performance by using a JFET as a source follower transistor for sensing charge. The pixel includes a floating diffusion node configured to sense photo-generated charge, a reset diode configured to reset the floating diffusion node in response to a reset signal, and a junction field effect transistor configured to output a signal having an output voltage level corresponding to a charge level of the floating diffusion node.