Abstract: A differential amplifier circuit is provided with transfer gates for interrupting input signals to control a timing of supplying the input signals and a timing of starting the differential amplifier circuit.

Abstract: A slew rate controlled circuit driver generates a binary output signal with strong direct current (DC) characteristics based on a received binary logic signal, while minimizing crowbar current. The slew rate controlled circuit driver may include a first driver with smaller transistors that open and/or close quickly to allow a generated output signal to meet required rise and fall time requirements, and may include a second driver with larger transistors that open and/or close more slowly, that allow the generated output signal to support for strong DC signal characteristics, such as support for high DC current loads without degrading the DC voltage signal levels. Further, OPEN and CLOSE states of transistors within each of the first and second drivers may be controlled to reduce, during switching between HIGH and LOW output signal states, the establishment of paths between HIGH signal sources and LOW signal sources that contribute to crowbar current.

Abstract: A design structure for an integrated circuit that includes a gate control voltage generator that supplies a current control gate voltage to a plurality of current control devices of a corresponding plurality of dynamic logic circuits each having a keeper circuit. The gate control voltage generator provides, via current control gate voltage, global control of the amount of keeper current flowing through the keeper circuits so as to enhance the performance of the dynamic logic circuits.

Abstract: The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors.

Abstract: The present invention provides a method involving at least one first circuit having at least one first input, at least one second input, and at least one output. The method includes determining at least one first value of at least one output of a second circuit based on at least one first value of the at least one first input. The second circuit has been configured using first configuration information generated based on the first circuit and at least one first value of the at least one second input. The method also includes generating, concurrently with determining the at least one first value of said at least one output, second configuration information based on the first circuit and at least one second value of the at least one second input.

Abstract: The circuit for detecting the maximal frequency of the pulse frequency modulation includes an oscillator-controlling unit, a delay circuit and a master-slave register. The oscillator-controlling unit is connected to an oscillator, which generates the pulse frequency modulation signals, and includes a first-half pulse-generating module and a second-half pulse-generating module. The delay circuit is connected to the second-half pulse-generating module. The master-slave register includes a clock, an input end and an output end, wherein the input end is connected to the oscillator-controlling unit, and the clock is connected to the delay circuit.

Abstract: An apparatus comprising a first comparator circuit, a second comparator circuit, a third comparator circuit, and a difference circuit. The first comparator circuit may be configured to generate a first intermediate current in response to a first input voltage and a second input voltage. The second comparator circuit may be configured to generate a second intermediate current in response to the first input voltage and the second input voltage. The third comparator circuit may be configured to generate an intermediate reference current in response to a first reference voltage and a second reference voltage. The difference circuit may be configured to generate a first compare voltage and a second compare voltage in response to the first intermediate current, the second intermediate current, and the intermediate reference current. The apparatus may indicate a squelch condition when the first compare voltage is greater than the second compare voltage.

Abstract: An electronic circuit device has a current correction circuit that supplies a correction current which is capable of offsetting an increment or a decrement of a consumption current of a signal processor circuit that varies based on a signal level of an input signal. Therefore, even if the consumption current of the signal processor circuit varies based on the signal level of the received input signal, the variation of the consumption current is offset by the current correction circuit. As a result, even if the consumption current varies based on the signal level of the input signal, since a current that flows in a resistor does not vary, a voltage drop can be held constant. Accordingly, it is possible to accurately conduct a comparison determination by a comparator.

Abstract: An improved clock switch in an integrated circuit chip that multiplexes two asynchronous clock signals to generate a multi-frequency clock signal in a manner that avoids glitches on the clock output line and meta-stable states within the switch. The clock switch does not include a cross-coupled feedback loop, thus rendering the clock switch test-friendly and avoiding potential race conditions in the switch. The clock switch is useable with asynchronous clock sources having a variety of different clock frequencies and phases.

Abstract: A transistor drive circuit of a power converter is developed for operating in a wide voltage range. It includes an N-type high-side transistor, a P-type high-side transistor and an N-type low-side transistor. A voltage clamp device is connected to the gate of the N-type high-side transistor to limit the maximum output voltage. A detection circuit is coupled to detect the supply voltage of the transistor drive circuit to generate a disable signal in response to the voltage level of the supply voltage. The disable signal is coupled to disable the P-type high-side transistor once the voltage level of the supply voltage is higher than a threshold voltage.

Abstract: A shift register includes a control unit, a signal switching unit and a buffer unit. The control unit determines whether to transfer an input signal from a first input terminal to a first output terminal according to a first control signal, and determines whether to conduct a first pre-defined voltage to a second output terminal according to a second control signal. The signal switching unit uses the signal output from the first output terminal as one of the considerations for determining whether to conduct a second pre-defined voltage to a third output terminal, and uses the second control signal as one of the considerations for determining whether to conduct the second pre-defined voltage to the first output terminal. The buffer unit outputs signal according to the signals from the first/third output terminals. Further, at least once, the second control signal is enabled after the first control signal has been enabled.

Abstract: A baseband clock synthesizer having particular use in a BLUETOOTH piconet device, having the capability of generating either 12 MHz or 13 MHz clock signals generated from any reference clock signal, e.g., 12.00, 12.80, 13.00, 15.36, 16.80, 19.20, 19.44, 19.68, 19.80, and 26.00 MHz. A fractional-N frequency divider is implemented with a PLL including a variable divider allowing the use of virtually any reference frequency input to generate a locked 156 MHz clock signal used as a basis for a 12 MHz or 13 MHz baseband clock signal. A residue feedback sigma-delta modulator provides a varying integer sequence to an integer divider in a feedback path of the PLL, effectively allowing division by non-integer numbers in the PLL. Thus, the PLL can be referenced to virtually any reference clock and still provide a fixed output clock signal (e.g., 12 or 13 MHz).

Abstract: A chopper circuit has a delay circuit that delays a received control signal and a difference detection circuit that detects a difference between a control signal delayed by the delay circuit and the received control signal. A first threshold based on which the delay circuit checks a change in the received control signal and a second threshold based on which the difference detection circuit checks a change in the received control signal are realized with a common threshold.

Abstract: A sawtooth wave generating apparatus includes a base frequency generating section and a frequency generating section for generating the frequency of a reference signal, a sawtooth wave forming section which forms a sawtooth wave based on the reference signal, a voltage comparator which compares the voltage value of the sawtooth wave formed by the sawtooth wave forming section with a predetermined voltage value, a phase comparator which compares the phase of the output signal from the voltage comparator with the phase of the reference signal, and a low-pass filter (LPF) which cuts out a high frequency component of the output signal from the phase comparator, and feeds back the resulting output signal to the sawtooth wave forming section.

Abstract: A phase locked loop (PLL), including a phase-frequency detector receiving two clock signals and outputting a phase detection signal corresponding to the phase difference between the two clock signals is provided. A controller receives the phase detection signal and generates a first control signal and a second control signal according to the phase detection signal, an oscillator receiving the first control signal and outputting a first output clock signal with a folded period corresponding to the first control signal and a loop divider receiving the second control signal and the first output clock signal dividing the frequency of the first output clock signal by an integer unfolding divisor corresponding to the second control signal and outputting a second output clock signal coupled to the phase-frequency detector. The PLL eliminates unlocked frequencies for all process imperfections, has decreased circuit area and provides a broad output bandwidth.

Abstract: A charge pump in a PLL incorporates interlinked first and second charge pumps that inject or withdraw a charge from a loop filter. The charge is proportional to a phase difference between a VCO and reference clock in the PLL.

Abstract: A write strategy circuit (recording pulse generator) generates a recording pulse for controlling a laser output applied to an optical disc using data modulated by a DVD encoder or a CD encoder. A delay circuit delays delay subject signals by a predetermined amount to generate delay signals. A delay amount for the delay circuit is controlled by a delay amount control circuit. A logic circuit generates a recording pulse by logically synthesizing the delay signals. The delay amount control circuit includes a voltage controlled oscillator formed by connecting, in a ring-like manner, a plurality of delay elements having the same configuration as the delay elements included in the delay circuit. An output signal of the voltage controlled oscillator is locked at a point where a delay amount for each delay element becomes a fraction of an integer of one cycle of a reference clock signal.

Abstract: A clock signal synchronization method and an apparatus device for utilization with the synchronization of clock signals is disclosed. In one embodiment the apparatus includes a delay device with a variably controllable delay time into which a clock signal, or a signal obtained therefrom, is input, charged with the variably controllable delay time, and output as a delayed clock signal. A device is provided for determining whether a clock edge of the delayed clock signal output by the delay device, or of a signal obtained therefrom, lies within a predetermined time window before a corresponding clock edge of the clock signal, or of the signal obtained therefrom.

Abstract: Clock synchronization and skew adjustment circuits are described that utilize varying unit delay elements in their delay lines in either a graduated or a stepped unit time delay arrangement, allowing a reduced circuit implementation and improved lock characteristics. These graduated or a stepped unit time delays allow reduction in the number of the fine unit delay elements of the delay lines by placing a fine delay element granularity at the most critical timings to sense and adjust for the portion of the clock signal time period that are high speed or critical. This allows clock synchronization and skew adjustment circuits to be implemented in an optimized manner that exhibits a reduced overall circuit size and power consumption, while having improved lock characteristics over a wide range of frequencies.

Abstract: A delay locked loop circuit for delaying an input clock to lock a delay clock. The delay locked loop includes a frequency divider for dividing a frequency of the input clock by a number N to obtain a frequency-divided clock, a plurality of delay components for delaying the input clock to generate a plurality of delay clocks with different phase according to a count value, a phase detector coupled to a final delay components for detecting a phase transition between a final delay clock and the input clock, and a counter coupled to the phase detector and the frequency divider for generating the count value according to the phase transition between the final delay clock and the input clock.

Abstract: An electronic device selects one of a plurality of input signals for coupling to an output channel. Individual pulldowns provide a separate pathway for each input, and are coupled to a common node which: is pre-charged to a voltage less than a system voltage. Each pulldown is coupled to a select line for gating an associated input signal.

Abstract: A modulator control circuit including a linear control circuit, a non-linear control circuit, and a combiner. The linear control circuit has an input receiving a compensation signal indicative of an output parameter and an output providing a first control signal. The non-linear control circuit has an input receiving the compensation signal and an output providing a second control signal. The non-linear control circuit senses transients of the compensation signal not otherwise detected by the linear control circuit and asserts the second control signal indicative thereof. The combiner combines the first and second control signals to provide a pulse width modulation signal for controlling the output parameter, such as output voltage or the like.

Abstract: A mixer (114) includes a phase clock generator (404), a latch (420), and a multiplier (118). The phase clock generator (404) provides a plurality of phase clock signals. The latch (420) is coupled to the phase clock generator (404) via a first plurality of conductors (410) and provides a plurality of resynchronized phase clock signals. The multiplier (118) is coupled to the latch (420) via a second plurality of conductors (430) and mixes an input signal using the plurality of resynchronized phase clock signals to provide a mixed output signal. The second plurality of conductors (430) is characterized as having a lower end-to-end impedance than an end-to-end impedance of the first plurality of conductors (410).

Abstract: A multiplexer circuit provided herein includes a plurality of pass devices coupled in parallel between a power supply and a ground supply. According to one embodiment, each pass device may include a first pair of transistors, which is coupled in series between the power supply and the ground supply, and a second pair of transistors, which is coupled to the first pair of transistors for controlling a current passed there through. In general, the second pair of transistors may be configured for increasing the amount of current passed through the first pair of transistors. For example, the second pair of transistors may utilize a bootstrapping effect to increase a pair of control voltages supplied to the gate terminals of the first pair of transistors. The increased control voltages function to over-drive the gate terminals of the first pair of transistors, thereby increasing the amount of current passed there through.

Abstract: A temperature compensated self-refresh circuit maintains a stable current characteristic by maintaining a predetermined self-refresh cycle to cope with a process skew and a voltage change in a low power consumption memory product and by changing the self-refresh cycle only depending on temperature change. The temperature compensated self-refresh circuit is provided with a reference voltage generating unit adapted and configured to use an internal power voltage of a Widlar type so as to reduce a process skew and to have NMOS transistors with a LVT (Low Voltage Transistor) structure so as to have the same voltage as that of a temperature sense unit, thereby maintaining a predetermined cycle of an oscillating signal coping with the process skew.

Abstract: The present invention relates to a frequency-independent voltage divider in which a compensation structure (10) for compensating a distributed parasitic capacitance of a resistor arrangement (20) is arranged between the resistor arrangement (20) and a substrate (50). Thereby, the compensation structure (10) shields the resistor arrangement (20) partly from the substrate (50), and thus shields the parasitic capacitance. This allows for an improved compensation.

Abstract: The disclosed technology provides circuitry for providing a DC output voltage. In accordance with one aspect of the invention, the circuit includes a power connection and a transistor connected to the power connection. A current source coupled to the transistor causes the transistor to pass at least a minimum current. The transistor's gate-to-source voltage can vary based on the current that passes through it, so that the minimum current established by the current source corresponds to a particular gate-to-source voltage. A reference voltage circuit is coupled to the transistor and causes a substantially constant voltage to appear on the gate connection of the transistor. The transistor's source connection carries an output voltage that is based on the gate voltage and the transistor's gate-to-source voltage. In accordance with one aspect of the invention, the DC output voltage circuitry has a substantially flat PSRR across frequencies of interest.

Abstract: A voltage buffer for capacitive loads isolates the load from the feedback loop. Using a variation of a follower arrangement, a second transistor outside of the feedback loop introduced. The current to the load is supplied through the second transistor, which is connected to have the same control gate level as the transistor in the feedback loop and provide an output voltage based on the reference input voltage. The output voltage is dependent upon the input voltage, but the load is removed from the feedback loop. By removing the load from the feedback loop, the loop is stabilized with only a very small or no compensating capacitor, allowing the quiescent current of the buffer to be reduced and the settling time to be improved. One preferred use of the present invention is to drive the data storage elements of a non-volatile memory.

Abstract: A circuit device has a passive network (101) with an input (109) and an output, the output of the passive network (101) forming an output terminal (103) of the circuit device and a feedback path coupling the output terminal (103) of the circuit device to the input (109) of the passive network (101), the feedback path having an amplifier (107) configured to adjust an attenuation of the circuit device.

Abstract: Disclosed is a filter circuit with an order of three or more, comprising at least one means for amplifying an in-band signal, wherein the frequency response of the filter output has a desirable attenuation characteristic obtainable with the order of the filter circuit. The gain of the amplifying means is variably controlled.

Abstract: Various embodiments are disclosed relating filter calibration with cell re-use. According to an example embodiment, an apparatus includes a first circuit, including a variable circuit element. The first circuit is adapted to output an output frequency signal during a calibration mode and to operate as a filter during a filter mode. A control circuit is coupled to the first circuit and is adapted to receive a reference frequency signal and to calibrate the first circuit by adjusting the variable circuit element based on the reference frequency signal and the output frequency signal during the calibration mode. The calibrated first circuit is configured to then operate as a filter during the filter mode.

Abstract: A demodulator for processing a PWM (pulse width modulation) signal includes a variable capacitor, a charging unit, a discharging unit, and a tuner. The charging and discharging units charge or discharge the variable capacitor depending on the PWM signal. The tuner determines a capacitance of the variable capacitor and a discharge current of the discharging unit for proper operation of the demodulator in various RF environments.

Abstract: A low distortion class-D amplifier. The amplifier comprises a power supply terminal for receiving power, an amplification stage, and an output stage. The amplification stage receives an input signal and generates a ramp signal. Further more, the amplification stage generates a pulse width modulation signal based on the ramp signal and a hysteretic signal. The output stage coupled to the power supply terminal receives the pulse width modulation signal and generates an output. Advantageously, the ramp signal and the hysteretic signal are positioned at a voltage level that is half the voltage level of said power supply and that varies proportionally with said power supply.

Abstract: The invention relates to a procedure and a circuit device for the subtraction of electrical signals, with at least two regulating loops each comprising at least one amplifier unit. Advantageously, the circuit device comprises a device for subtracting a signal, made available by the circuit device and representing the difference between the electrical signals, from one of the electrical signals. In a preferred embodiment of the invention, the potentials on lines carrying the electrical signals are maintained at the same value with the help of a first one or of the regulating loops.

Abstract: An embodiment of the present invention provides an apparatus, comprising an integrated circuit, wherein a first portion of the integrated circuit is placed on a top tier substrate and a second portion of the integrated circuit is placed on a bottom tier substrate stacked adjacent the top tier substrate and wherein the first portion and the second portion of the integrated circuit are interconnected; and printed spiral arms stacked vertically on both the top and bottom surface of the top tier substrate thereby creating high Q inductors.

Abstract: An automatic gain controller includes a variable gain amplifier for amplifying an input signal having a specified DC level on the basis of the DC level, and outputting a first differential signal having a specified gain ?, a second differential signal having a 180° phase difference from the first differential signal, and an output signal obtained by subtracting the second differential signal from the first differential signal; a full-wave-rectifying unit for full-wave-rectifying the first differential signal and the second differential signal; a low-pass filter for extracting the DC component from the output signal of the full-wave-rectifying unit and outputting the extracted DC component; a reference voltage level adjustment unit for adjusting a DC level of a reference voltage; and a comparison unit for comparing the output signal of the low-pass filter with the output signal of the reference voltage level adjustment unit to adjust a gain of the variable gain amplifier.

Abstract: A method, algorithm, architecture, circuits, and/or systems for low noise amplification are disclosed. In one embodiment, an amplifier can include an input stage, including a first differential input configured to receive a differential signal, a first current source coupled to the first differential input, a first current load receiving a first bias voltage and coupling the input stage to a first power supply, and a first pair of common mode feedback transistors, coupled to an output of the first current load and configured to limit a current to the first current source. The input stage provides an amplified signal to an additional stage having a structure similar to the input stage, configured to further amplify the amplified signal.

Abstract: A transimpedance amplifier circuit comprises a first amplifier having an input, an output and a first transconductance. A second amplifier has an input that communicates with the output of the first amplifier, an output and a second transconductance. A first resistance has one end that communicates with the input of the first amplifier. A third amplifier has an input that communicates with the output of the second amplifier, an output and a third transconductance. A fourth amplifier has an input that communicates with the output of the third amplifier, an output and a fourth transconductance. An inverter has an input that communicates with the output of the fourth amplifier and an output that communicates with an opposite end of the first resistance.

Abstract: A class AB folded cascode circuit includes a differential current follower having first and second cascode transistors with emitters connected to first and second input conductors. An input of a first current mirror is coupled to the first input conductor, and an input of a second current mirror is coupled to the second input conductor. Outputs of the second and first current mirrors are coupled to collectors of the first and second cascode transistors, respectively, and also to first and second outputs, respectively, of the differential current follower. A third current mirror converts a differential output current in the first and second output conductors to a corresponding single-ended output voltage on the second output conductor.

Abstract: A circuit capable of quiescent current control, the circuit comprising a first operational transconductance amplifier (OTA) including a first output terminal, a first transistor including a first gate coupled to the first output terminal of the first OTA, a second OTA including a second output terminal, a second transistor including a second gate coupled to the second output terminal of the second OTA, a resistive load including a first terminal coupled to the first output terminal and the first gate, and a second terminal coupled to the second terminal and the second gate, a first current source capable of providing a first current flowing toward the first terminal of the resistive load, and a second current source capable of providing a second current flowing away from the second terminal of the resistive load.

Abstract: A tuned low-noise amplifier is disclosed. A device in accordance with the present invention comprises a first current source, a second current source, a comparator, coupled to the first current source and the second current source, for providing a control signal, and a third current source, receiving the control signal and coupled to the tuned low-noise amplifier, wherein a current in the third current source is proportional to a current in the first current source and the second current source, where values of the first current source, the second current source, and the third current source are based on a quasi-Proportional-To-Absolute-Temperature (PTAT) curve.

Abstract: An integrated power combiner is disclosed. The power combiner includes a first circular geometry primary winding having one or more inductive elements, such as an active winding with one or more driver stages. A circular geometry secondary winding is disposed adjacent to the first primary winding, such as an active winding with one or more driver stages. A second circular geometry primary winding is disposed adjacent to the secondary winding and has one or more inductive elements. One or more connections are provided between one or more of the inductive elements of the first circular geometry primary winding and one or more of the inductive elements of the second circular geometry primary winding.

Abstract: To improve operation during cutback power mode by reducing gain expansion, sections of a multi-section amplifier are selectively biased. During cutback power condition, fewer than all sections of the multi-section amplifier are biased. Selective biasing reduces power consumption and obtains desired output power. To reduce gain expansion, a bias resistor is provided between one or more sections to establish a small or leakage bias current into non-enabled or non-biased sections. This leakage bias current weakly biases the non-enabled sections allowing small signal amplification by the non-enabled sections. The combined amplification of the enabled section and the weakly biased section provide greater initial gain at lower power input signal levels thereby reducing gain expansion.

Abstract: The present invention is ripple cancellation circuitry used with a switching power supply, which provides direct current (DC) power via a DC power amplifier (PA) signal to an RF PA final stage. The DC PA signal includes a DC component and a power supply ripple component, which is generated as a result of the switching characteristics of the switching power supply and creates an output ripple in an RF output signal from the PA final stage. The ripple cancellation circuitry substantially cancels the output ripple by adding a ripple cancellation signal having a ripple component that is phase-shifted approximately 180 degrees from the output ripple to the RF output signal. The ripple cancellation circuitry uses a switching signal that is provided by the switching power supply to generate the ripple cancellation signal.

Abstract: An apparatus and method for eliminating unwanted signal power dissipation in balanced amplifier circuits and for prohibiting unwanted signal power from appearing at the balanced amplifier load is presented. Load impedances to the amplifier power output transistors are maintained very low at unwanted frequencies, and are at an operational impedance level at the fundamental frequency. An impedance network control concept is presented, which may be either manually or automatically implemented.

Abstract: A charge pump that generates a bias input to affect an output voltage of the charge pump is described herein. The charge pump may include a charge pump stage, a replica charge pump stage, and a self-biased differential amplifier. In some instances, the charge pump may be incorporated into a delay locked loop or a phase locked loop.

Abstract: An automatic switching phase-locked loop (PLL) is disclosed, including a phase detector, a charge pump generating a pump current, a band selector receiving a control voltage to produce a band selection signal and a voltage setting signal based the control voltage, a loop filter generating the control voltage corresponding to the pump current and setting the control voltage based on the voltage setting signal, and a multi-band voltage control oscillator (VCO) coupled to the control voltage and the band selection signal, selecting one of a plurality of operating bands based on the band selection signal, and providing an output signal of a frequency within the selected operating band based on the control voltage.

Abstract: A phase-locked loop (PLL) for stably adjusting a frequency band of a voltage-controlled oscillator and a phase locking method. In the PLL, a frequency band controller alters the frequency band selection digital value in response to an input clock signal and an oscillation control signal generated from an LPF of a basic PLL circuit, and thus a voltage-controlled oscillator of the basic PLL circuit alters the frequency of an output clock signal in response to the oscillation control signal and the frequency band selection digital value. The output clock signal is rapidly and stably phase-locked at a target frequency depending on the frequency band selection digital value.

Abstract: An integrated circuit including a phase-locked loop (PLL) circuit responsive to a voltage controlled oscillator (VCO) frequency band selection circuit that provides automatic frequency band selection in real time to account for run-time variations, such as power supply and temperature variations over time. The PLL includes a charge pump and an LC tank circuit that provides the automatic frequency band selection based on a VCO control voltage signal supplied by the charge pump.

Abstract: Provided are a method, system, and device to monitor degradation of a signal due to circuit aging. In one embodiment, a signal may be applied to a data path prior to aging of the circuit producing the signal to provide a reference value. The signal generating circuit may then be aged while the data path is disabled to protect the data path from the effects of circuit aging. Upon reenabling the data path, the signal may be reapplied in an after stress test to measure the effects of circuit aging on the circuitry generating the signal. For example, the effects of circuit aging may be measured for clock duty cycle degradation, clock skew degradation and signal margin degradation as well as other signal parameters. Additional embodiments are described and claimed.