Abstract: The invention relates to a device for measuring living cells or similar biocomponents comprising a field effect transistor which is provided with a source, a drain and a channel area placed on a substrate. Said channel area connects said source and drain and is provided with a gate-electrode mounted thereon. The gate electrode has at least two laterally disposed parallel electrode areas which are perpendicular to a direction in which the channel area connects the source to the drain in such a way that they are distant and electrically insulated from each other.

Abstract: There are provided a first reference layer, in which a direction of magnetization is fixed, and a storage layer including a main body, in which a length in an easy magnetization axis direction is longer than a length in a hard magnetization axis direction, and a projecting portion provided to a central portion of the main body in the hard magnetization axis direction, a direction of magnetization of the storage layer being changeable in accordance with an external magnetic field.

Abstract: A magnetic memory capable of reducing diffusion of ferromagnetic material into semiconductor element area is provided. A magnetic memory 1 includes plural memory areas 3 disposed in two-dimension of m rows and n columns (m, n are integers of 2 or more). The magnetic memory 1 includes semiconductor layer 6 including drain area 32a and source area 32c for write transistor 32, magnetic material layer 8 including TMR element 4 and write wiring 31, and wiring layer 7 including bit wirings 13a and 13b and word wiring 14 being sandwiched between semiconductor layer 6 and magnetic material layer 8. Since wiring layer 7 is sandwiched between magnetic material layer 8 and semiconductor layer 6, the ferromagnetic material diffusing (migrates) from TMR element 4 hardly reaches to semiconductor layer 6. Thus, the diffusion of the ferromagnetic material into the drain area 32a and the source area 32c can be reduced.

Abstract: In a solid-state imaging device of the present invention, light-sensitive elements 54, each of which includes a light receiving section capable of receiving light, are arranged in a matrix form at regular spacings in a photoreceiving region provided on a semiconductor substrate 51. A plurality of detecting electrodes 53 are provided on the semiconductor substrate 51 corresponding to the light-sensitive elements 54 for detecting an electrical charge generated by each light-sensitive element 54. A plurality of interconnections 57 coat the detecting electrodes 53, and apply a voltage thereto. A plurality of reflecting walls 62 are formed in a grid pattern over the interconnection 57 so as to partition the light-sensitive elements 54 individually for reflecting a portion of light entering the semiconductor substrate 51 from above onto the light receiving section of each light-sensitive element 54. The plurality of reflecting walls 62 are electrically insulated from the interconnections 57.

Abstract: The present invention is directed towards radiation detectors and methods of detecting incident radiation. In particular the present invention is directed towards photodiodes with controlled current leakage detector structures and a method of manufacturing photodiodes with controlled current leakage detector structures. The photodiodes of the present invention are advantageous in that they have special structures to substantially reduce detection of stray light. Additionally, the present invention gives special emphasis to the design, fabrication, and use of photodiodes with controlled leakage current.

Abstract: A self-aligned silicon carbide power MESFET with improved current stability and a method of making the device are described. The device, which includes raised source and drain regions separated by a gate recess, has improved current stability as a result of reduced surface trapping effects even at low gate biases. The device can be made using a self-aligned process in which a substrate comprising an n+-doped SiC layer on an n-doped SiC channel layer is etched to define raised source and drain regions (e.g., raised fingers) using a metal etch mask. The metal etch mask is then annealed to form source and drain ohmic contacts. A single- or multilayer dielectric film is then grown or deposited and anisotropically etched. A Schottky contact layer and a final metal layer are subsequently deposited using evaporation or another anisotropic deposition technique followed by an optional isotropic etch of dielectric layer or layers.

Abstract: A passive matching network is connected to an input/output line for an automatic test equipment drive channel to compensate for capacitances associated with a receiver circuit connected to the line, and also an optional current-mode driver circuit. The matching circuit preferably comprises a T-coil circuit that can include a bridging capacitor; separate T-coil circuits can be provided to separately compensate for receiver circuit and current-mode driver circuit capacitances. The driver and receiver circuits can be implemented on a common layer of an integrated circuit, with the T-coil windings implemented in a separate layer of the same integrated circuit that is spaced from the common layer by at least one dielectric layer.

Abstract: A semiconductor device and a fabrication method thereof in which the semiconductor device includes capacitors having a metal/insulator/metal (MIM) structure are disclosed. The method includes forming an interlayer insulating film on a structure of a semiconductor substrate that exposes lower wiring and a lower insulating film; selectively etching the interlayer insulating film to form a first electrode opening that exposes the lower wiring; forming a first electrode in the first electrode opening such that the first electrode opening is filled; selectively etching the interlayer insulating film at a region of the same adjacent to the first electrode to thereby form a second electrode opening; forming a dielectric layer along inner walls that define the second electrode opening; forming a second electrode on the dielectric layer in such a manner to fill the second electrode opening; and forming upper wiring on at least a portion of the second electrode.

Abstract: Oxygen can be doped into a gallium nitride crystal by preparing a C-plane gallium nitride seed crystal or a three-rotationally symmetric plane foreign material seed crystal, supplying material gases including gallium, nitrogen and oxygen to the C-plane gallium nitride seed crystal or the three-rotationally symmetric foreign seed crystal, growing a faceted C-plane gallium nitride crystal having facets of non-C-planes on the seed crystal, maintaining the facets on the C-plane gallium nitride crystal and allowing oxygen to infiltrate via the non-C-plane facets to the gallium nitride crystal.

Abstract: The present invention discloses an anodically bonded vacuum cell structure with a glass substrate including a cavity, and a substrate deposited on the glass substrate, thereby enclosing the cavity to form a bonding interface. The bonding interface having silicon such that the substrate includes a layer of silicon or a secondary substrate with silicon layer bonded onto the secondary substrate.

Abstract: A transistor may be formed of different layers of silicon germanium, a lowest layer having a graded germanium concentration and upper layers having constant germanium concentrations such that the lowest layer is of the form Si1-xGex. The highest layer may be of the form Si1-yGey on the PMOS side. A source and drain may be formed of epitaxial silicon germanium of the form Si1-zGez on the PMOS side. In some embodiments, x is greater than y and z is greater than x in the PMOS device. Thus, a PMOS device may be formed with both uniaxial compressive stress in the channel direction and in-plane biaxial compressive stress. This combination of stress may result in higher mobility and increased device performance in some cases.

Abstract: In each of a p-channel MOS transistor and an n-channel MOS transistor, a channel direction is set in the <100> direction and a first stressor film accumulating therein a tensile stress is formed in a STI device isolation structure. Further, a second stressor film accumulating therein a tensile stress is formed on a silicon substrate so as to cover the device isolation structure.

Abstract: The invention provides a substantially transparent material comprising particles of an inorganic titanate or an inorganic zirconate and at least one compound, wherein the particles are uniformly dispersed in the at least one compound, and wherein the particles are bonded to the at least one compound via at least one surface functional group of the particles. The invention also provides a light emitting device comprising a light emitting diode encapsulated with the substantially transparent material.

Abstract: It is an object of the present invention to provide, with good yields, a composition for forming an insulation film which allows obtaining an insulation film for a semiconductor device having a low dielectric constant, excellent stress resistance and excellent crack resistance; an insulation film for a semiconductor device formed from the composition for forming an insulation film; and a high quality and highly reliable semiconductor device fabricated using the insulation film for a semiconductor device. This composition for forming an insulation film comprises a polymer of which the main chain is a chain portion which substantially contains only carbon, silicon and hydrogen, and which contains nitrogen in portions other than the main chain. It is preferable that nitrogen exists as a constituent represented by Formula 1 in the polymer.

Abstract: A method for manufacturing an organic EL device comprising: coating a composition including an organic EL material on a plurality of electrodes to form an organic EL layer on each electrode; defining an effectively optical area in which the plurality of electrodes are formed; and defining a coating area which is broader than the effectively optical area, on which the composition including an organic EL material is to be coated. According to this method, a uniform display device without uneven luminance and uneven chrominance within a pixel or among a plurality of pixels in the effectively optical area can be obtained.

Abstract: The present invention is directed to a high frequency module used for wireless communication module, and comprises a first organic substrate (11) in which conductive pattern or patterns are formed on the principal surface thereof and one element body (7) or more are mounted, and a second organic substrate (12) in which a recessed portion (22) is formed in correspondence with the area where the element body or bodies (7) are mounted at the connecting surface to the first organic substrate (11). In the state where the second organic substrate (12) is connected to the first organic substrate (11), an element body accommodating portion (24) which seals the element body or bodies (7) is constituted by the recessed portion (22), wherein the element body accommodating portion (24) is adapted so that moisture resistance characteristic and oxidation resistance characteristic are maintained.

Abstract: In one embodiment of the invention, a lead-frame is designed for use in IC packages such as those conforming to the TO 220 standard or other standards for power packages. The device areas of the lead-frame are arranged in columns, and each column is molded so as to expose a portion of the leads. The device areas can then be cingulated by sawing, as in conventional QFN packages. In this manner, packages conforming to power package standards such as the TO 220 standard can be produced much quicker and cheaper than they can in conventional trim and forming methods.

Abstract: A semiconductor device with its package size close to its chip size has a stress absorbing layer, allows a patterned flexible substrate to be omitted, and allows a plurality of components to be fabricated simultaneously. There is: a step of forming electrodes (12) on a wafer (10); a step of providing a resin layer (14) as a stress relieving layer on the wafer (10), avoiding the electrodes (12); a step of forming a chromium layer (16) as wiring from electrodes (12) over the resin layer (14); a step of forming solder balls as external electrodes on the chromium layer (16) over the resin layer (14); and a step of cutting the wafer (10) into individual semiconductor chips; in the steps of forming the chromium layer (16) and solder balls, metal, thin film fabrication technology is used during the wafer process.

Abstract: An apparatus and method for manufacturing a display device substrate are provided. In one embodiment, the apparatus comprises a clamp for clamping an edge of a plastic substrate, and a tension member applying tension along a surface of the plastic substrate by interacting with the clamp to strain the plastic substrate. Advantageously, the flexible plastic substrate is substantially prevented from deflecting in a manufacturing process thereby reducing defects in the display device substrate.

Abstract: The present invention is concerned with a method for producing a semiconductor device wherein lower-layer wirings and upper-layer wirings are formed with an interlayer insulating film therebetween, and the lower-layer wirings are electrically connected to the upper-layer wirings via via-hole plugs. Over a semiconductor substrate, the interlayer insulating film is formed to cover the lower-layer wirings. In the interlayer insulating film, via-holes for exposing surfaces of the lower-layer wirings are formed, and simultaneously, in a region of the interlayer insulating film where no via-holes exist, dummy via-holes which are not deep enough to reach down to the lower-layer wirings are formed. The dummy via-holes are formed in such a manner that the density of the dummy via-holes gradually decreases from a region where the via-holes are formed. Over the semiconductor substrate, a metal layer is formed to fill the via-holes and the dummy via-holes.

Abstract: A configuration for a substrate for a semiconductor device which makes it possible to achieve further stabilization of the voltage for driving a semiconductor element (5) to be mounted is provided. The substrate for a semiconductor device is provided with a base (1) and an electrically insulating film (3) formed on at least a portion of the surface of this base (1). The base (1) is made of one type of material selected from the group consisting of an alloy including copper and tungsten, an alloy including copper and molybdenum, an alloy including copper, tungsten and molybdenum, a composite material including aluminum and silicon carbide, and a composite material including silicon and silicon carbide. The electrically insulating film (3) includes plural layers made of at least one type of film selected from the group consisting of a diamond-like carbon film, an aluminum oxide film and a silicon oxide film.

Abstract: A semiconductor device includes an intermediate layer provided between a semiconductor element and a heat sink. The intermediate layer moderates thermal stress resulting from a difference between thermal expansion of the semiconductor element and thermal expansion of the heat sink arising due to heat produced by the semiconductor element. This thermal stress moderation reduces warping of the semiconductor device as a whole.

Abstract: Embodiments of the present invention provide an apparatus, a system, and a method, and include a generally rectilinear body having a first surface and a second surface. The second surface is substantially perpendicular to the first surface. An electrically operative element is disposed on the first surface, and has opposite ends. Spaced apart terminations are disposed on the second surface, and are electrically coupled with the opposite ends of the electrically operative element. The terminations are designed to be coupled with a substrate.

Abstract: Disclosed are embodiments of a far back end of the line solder connector and a method of forming the connector that eliminates the use aluminum, protects the integrity of the ball limiting metallurgy (BLM) layers and promotes adhesion of the BLM layers by incorporating a thin conformal conductive liner into the solder connector structure. This conductive liner coats the top of the via filling in any divots in order to create a uniform surface for BLM deposition and to, thereby, protect the integrity of the BLM layers. The liner further coats the dielectric sidewalls of the well in which the BLM layers are formed in order to enhance adhesion of the BLM layers to the well.

Abstract: A mounting structure is provided. The mounting structure includes: a substrate; a line formed on the substrate; an electronic component in which a terminal having a protrusion protruded to the substrate and made of an elastic material and a conductive member disposed on the protruded surface of the protrusion and electrically connected to the line is disposed on a mounting surface of the electronic component opposed to the substrate; and an adhesive in which metal powders, a part of which is interposed between the conductive member and the line, are mixed and which serves to bond and fix the electronic component to the substrate. Here, the conductive member and the line interpose the metal powders therebetween and come in surface-contact with each other.

Abstract: A confronting surface of a substrate faces a first surface of a semiconductor element. Extension layers are formed on the substrate at positions facing electrodes on the semiconductor element. A levee film is disposed on one of the confronting surface and the first surface. Openings are formed through the levee film. Connection members which is filled but is not completely filled in the openings connect the electrodes and the extension layers.

Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer.

Abstract: This invention pertains to electronic/optoelectronic devices with reduced extended defects and to a method for making it. The device includes a substrate, a semiconductor active material deposited on said substrate, and electrical contacts. The semiconductor active material defines raised structures having atomically smooth surfaces. The method includes the steps of depositing a dielectric thin film mask material on a semiconductor substrate surface; patterning the mask material to form openings therein extending to the substrate surface; growing active material in the openings; removing the mask material to form the device with reduced extended defect density; and depositing electrical contacts on the device.

Abstract: A circuitized substrate including a composite layer including a first dielectric sub-layer including a plurality of fibers having a low coefficient of thermal expansion and a second dielectric sub-layer of a low moisture absorptivity resin, the second dielectric sub-layer not including continuous or semi-continuous fibers or the like as part thereof. The substrate further includes at least one electrically conductive layer as part thereof. An electrical assembly and a method of making the substrate are also provided, as is an information handling system (e.g., computer) incorporating the circuitized substrate of the invention as part thereof.

Abstract: The present invention provides an integrated high voltage capacitor, a method of manufacture therefore, and an integrated circuit chip including the same. The integrated high voltage capacitor, among other features, includes a first capacitor plate (120) located over or in a semiconductor substrate (105), and an insulator (130) located over the first capacitor plate (120), at least a portion of the insulator (130) comprising an interlevel dielectric layer (135, 138, 143, or 148). The integrated high voltage capacitor further includes capacitance uniformity structures (910) located at least partially within the insulator (130) and a second capacitor plate (160) located over the insulator (130).

Abstract: A barrier layer stack. The barrier layer stack includes a semiconductor process wafer comprising an exposed conductive region, a first barrier layer stack comprising at least one TiN and one Ti layers overlying and contacting the conductive region, wherein the TiN layer is contacted with the Ti layer, and an overlying aluminum alloy layer in contact with the first barrier layer stack.

Abstract: A semiconductor component has a semiconductor body and also a metal/insulation structure arranged above the semiconductor body and having a plurality of metal regions and insulation regions laterally adjoining one another. The metal regions serve for supplying the semiconductor body with electric current. Furthermore, the semiconductor component has a passivation layer arranged on the metal/insulation structure. The passivation layer includes a metal or a metal-containing compound.

Abstract: A semiconductor device includes a substrate with a dielectric layer thereon, a stack of interconnection structures in the dielectric layer, each interconnection structure including a conductive layer and a layer of plugs connecting the conductive layer, at least a layer of plugs including a crack stopper, and a bonding pad structure with a predetermined bump area thereon, overlying the stack of interconnection structures, wherein the crack stopper is formed along an edge of a projection area corresponding to the predetermined bump area.

Abstract: An integrated circuit (IC) carrier assembly includes a printed circuit board (PCB). A carrier is soldered to the PCB. The carrier includes a plurality of electrical contact islands surrounding a receiving zone for receiving an IC. Pairs of adjacent islands are interconnected by respective resilient suspension means. The IC is received in the receiving zone and is electrically coupled to some of the plurality of islands adjacent to the receiving zone.

Abstract: A packaging method includes ultrasonically bonding a semiconductor device and a substrate together via bumps that include gold as a main component thereof. A contact surface of a primary bump on a surface of an aluminum pad on one side of the substrate contacts and is ultrasonically bonded to a distal end surface of each opposed secondary bump on one side of the semiconductor device. An area of the contact surface is larger than that of the opposed distal end surface. By this method, damage to the substrate from the ultrasonic can be reduced without using a reinforcing layer.

Abstract: In the present invention, copper interconnection with metal caps is extended to the post-passivation interconnection process. Metal caps may be aluminum. A gold pad may be formed on the metal caps to allow wire bonding and testing applications. Various post-passivation passive components may be formed on the integrated circuit and connected via the metal caps.

Abstract: The present invention relates to a semiconductor device in which an electrode of a device formed on a substrate such as a semiconductor wafer and an electrode of a wiring structure such as an interposer are connected to each other through a connecting electrode extending through the substrate, and a method of manufacturing the same. A semiconductor device according to the present invention comprises a first substrate including a front surface and a back surface, a first device having a first electrode being formed on the front surface; and a wiring structure formed with a second electrode, the wiring structure having a principal surface. The first electrode of the first device and the second electrode of the wiring structure are connected to each other by a connecting electrode extending through the first substrate from the front surface to the back surface thereof. Substantially all the back surface of the first substrate is bonded to the principal surface of the wiring structure.

Abstract: An object of the invention is to provide glass for semiconductor encapsulation and an outer tube for semiconductor encapsulation which are friendly to environment and allow semiconductor electronic parts to have a heat resistance of 700° C. or higher as normal maximum temperature, and semiconductor electronic parts. The glass for semiconductor encapsulation according to the invention contains essentially no lead and the temperature at which viscosity reaches 1010 dPa·s is 700° C. or higher. According to such a constitution, since the glass contains essentially no lead, no harmful ingredients are discharged in the production of the outer tube for semiconductor encapsulation and in the production of the semiconductor electronic parts and thus the glass is friendly to environment. Moreover, since the temperature at which viscosity reaches 1010 dPa·s is 700° C. or higher, semiconductor electronic parts such as a bead thermistor using the same has a heat resistance of 700° C.

Abstract: A portable battery charger that is powered by a gasoline, diesel, or propane engine. The portable device incorporates a recoil or electric starter and an engine throttle lever that can be used to vary the RPM of the engine and therefore the voltage/current output of the charger. The charger uses a permanent magnet alternator equipped with a belt tension adjustor arm and a heavy duty diode rectifier. The components of the charger (the engine and the alternator) are positioned on a wheeled, heavy-gauge steel, roll around cart that makes the charger easily portable. The two-wheeled cart includes an extended handle, allowing the user to move and steer the charger into position for use. Positioned on this handle is a control box with an anti-spark keyed switch that blocks any charging current from traveling through the charging cables until the switch is thrown. This control facilitates the safe hook-up of the charging clamps while the charger (engine) is running.

Abstract: In an internal combustion engine including an electronic engine control unit and electric consumers including an electric generator, a starter system, a performance module having integrated therein switching means for activating or deactivating consumers and monitoring means for the surveillance of the consumers and also power distribution means for the distribution of the electric power to the consumers is connected to the crankcase of the engine and wired via wiring harnesses to the engine and the consumers.

Abstract: A voltage controller has an integrated control circuit having a plurality of lead wires, a plurality of connecting terminals, and a terminal holding body holding the terminals such that a portion of each terminal is protruded from a surface of the body so as to be connected with one lead wire. The control circuit controls an output voltage of an alternator by receiving or outputting signals transmitted through the lead wires and the connecting terminals. The protruded terminals are disposed so as to be aligned along a plurality of lines on the surface of the body. Therefore, an on-surface distance between terminals adjacent to each other is sufficiently set at a large value, and the arrangement of the terminals prevents the terminals from being short-circuited.

Abstract: A protection operation control part switches a gate signal interruption switch for protection of power elements to a gate signal interruption side, and invalidates a switching signal from a hybrid control unit to place transistors into a nonconducting operation. A motor current signal from a motor current detector is converted into a current value by a motor current calculation unit, and is inputted to a short-circuit abnormality detection unit through a motor control arithmetic part, and a short-circuit abnormality is detected. At a time of detecting the short-circuit abnormality, an internal combustion engine operation instruction unit gives an instruction to an internal combustion engine control unit so as to limit output of an internal combustion engine, and releases a conduction state of an abnormal motor current.

Abstract: An AC generator comprises a rotor and a stator having a three-phase winding. A three-phase inverter is connected to the three-phase winding. Here, the three-phase winding comprises at least two independent three-phase windings. Switching elements for respective phases of the three-phase inverter are connected in parallel by the number of the independent three-phase windings, and in-phase windings are individually connected to their parallel switching elements.

Abstract: Methods and systems for an engine generator set that includes an electrical generator configured to provide electrical energy to a first load rated at a first voltage and a first frequency, and to provide electrical energy to a second load rated at a second voltage and a second frequency, a prime mover coupled to the generator through a shaft, and configured to rotate the shaft at a first rotational speed at the first frequency and to rotate the shaft at a second rotational at the second frequency, and an engine generator set control system that includes a generator control system configured to control an output of the electrical generator, an engine control system configured to control a rotational speed of the shaft, and an output selector configured to modify the output of the engine generator set from the first voltage and the first frequency to at least one of the second voltage and the second frequency.

Abstract: The present invention is a system for generating power using water current. In one embodiment, a subsurface power generating system includes a first power generating node, with at least one cross-flow turbine, at least one universal gear coupled to the at least one cross-flow turbine, at least one modular generator; and at least one clutch for engaging and disengaging the at least one modular generator and the at least one universal gear.

Abstract: The invention relates to Method of operating a wind turbine, wherein rotor windings of an induction generator, which comprises stator coils coupled to a voltage grid, fed with rotor currents by a feed-in unit are driven by a rotor of the wind turbine; wherein the frequencies of the fed-in rotor currents are controlled depending on the rotor rotation frequency and the feed-in unit is electrically decoupled from the rotor windings in the case predetermined variations of the grid voltage amplitude and the rotor current feed-in is resumed after the decoupling caused by the variation of the grid voltage amplitude, when the currents generated in the rotor windings by the variation have declined to a predetermined value.

Abstract: A system and method controls a rotational speed of a rotor or shaft of a turbogenerator in accordance with a present voltage level on a direct current bus. A lower threshold and a higher threshold are established for a speed of a rotor or shaft of a turbogenerator. A speed sensor determines speed data or a speed signal for the rotor or shaft associated with a turbogenerator. A voltage regulator adjusts a voltage level associated with a direct current bus within a target voltage range if the speed data or speed signal indicates that the speed is above the higher threshold or below the lower threshold.

Abstract: An apparatus is disclosed for a turbine for generating electrical power from water or air flow comprising at least one rotor disk having a plurality of hydrofoil blades, a guide vanes, a cylindrical housing, and a generator means. A rim generator comprising a magnet race rotor rim and fixed stator coils in the housing is used. The apparatus is fitted with a screen to stop the ingress of debris and marine life, and a skirt augmenter device to reduce the Betz effect. The apparatus is preferably for sub-sea deployment and driven by tidal currents, but may be powered by river current or wave driven air or by wind. The apparatus may be deployed on at least one telescoping pole, tethered to the sea-bed and kept buoyant by buoyant concrete in the housing, inserted in a dam, under a barge or in a tidal power array.

Abstract: A wind turbine tower assembly for storing compressed gas such as hydrogen. The tower assembly includes a wind turbine having a rotor, a generator driven by the rotor, and a nacelle housing the generator. The tower assembly includes a foundation and a tubular tower with one end mounted to the foundation and another end attached to the nacelle. The tower includes an in-tower storage configured for storing a pressurized gas and defined at least in part by inner surfaces of the tower wall. In one embodiment, the tower wall is steel and has a circular cross section. The in-tower storage may be defined by first and second end caps welded to the inner surface of the tower wall or by an end cap near the top of the tower and by a sealing element attached to the tower wall adjacent the foundation, with the sealing element abutting the foundation.

Abstract: The present invention relates to s wind turbine having a power generator for generating power for a first power line of a power grid; said wind turbine comprising a first transformer having a first primary coil connected to said power generator and a first secondary coil connected to said first power line for transforming a first primary voltage (vp1) across said first primary coil to a first secondary voltage (vs1) across said first secondary coil; further, the wind turbine according to the invention comprises a first electric circuit connected to said first primary coil; said first electric circuit having a first switching element for providing a first current path parallel to said first primary coil if said first secondary voltage (vs1) exceeds a predetermined first voltage limit value.