Abstract: An instrument for checking quality of therapeutic x-ray and electron radiation provides modes optimized for both electrons and for photons obtained by physically flipping the unit to interpose the necessary build-up material between the radiation beam and contained detectors. The invention provides an improved method of constructing ionization detectors for improved energy discrimination using such detectors and wire-free operation.

Abstract: In a preferred embodiment, a radiation detector, including: one or more anode wires disposed within a body of the radiation detector, connections to and suspension of the one or more anode wires being made externally of active volume of said radiation detector.

Abstract: Disclosed is a dual array detector module adapted to radiation-imaging, comprising: a first detector array consisting of a plurality of first detectors and arranged on a first surface of a heavy metal plate; a second detector array consisting of a plurality of second detectors and arranged on a second surface of the heavy metal plate opposite to the first surface; and a mounting frame, in which the first detector away and the second detector array arranged on the first and second surfaces of the heavy metal plate respectively are mounted in the mounting frame, a housing which has a substantially elbow shape in cross-section, wherein an electronic circuit board having an output terminal and an input terminal is disposed inside the housing, in which the input terminal of the electronic circuit board is connected to signal output terminals of the first and second detector arrays and the output terminal of the electronic circuit board is connected to a socket mounted on the housing.

Abstract: A system for detecting secondary and backscattered electrons in a scanning electron microscope includes a microporous plate (9) that is disposed between a lower scintillator (5) and an upper scintillator (12). The lower scintillator (5) faces toward a specimen stage (11). A movable diaphragm (14) having an aperture (15) is located between the front end of a photomultiplier (7) and the respective ends of an upper light guide (13) and lower light guide (6). Inside an intermediate chamber (3), at least one focusing electrode (8) is placed, with its hole positioned coaxially with the hole in the microporous plate (9). The focusing electrode (8) is located on the surface of the lower scintillator (5).

Abstract: A collector is disclosed that is constructed to receive radiation from a radiation source and to transmit radiation to an illumination system, the collector comprising a reflective element which is internally provided with a fluid channel.

Abstract: A submersible fluorometer for measuring a fluorescence of a photosynthetic material in a liquid, the fluorometer includes a set of light emitting diodes (LEDs) for supplying light to direct towards the liquid and a photodiode for measuring a detected light emitted from the liquid. The light is used for measuring the fluorescence of the photosynthetic material in the liquid. The fluorometer also has a water-tight volume for protecting the photodiode from the liquid.

Abstract: An object of the invention is to realize a method and an apparatus for processing and observing a minute sample which can observe a section of a wafer in horizontal to vertical directions with high resolution, high accuracy and high throughput without splitting any wafer which is a sample. In an apparatus of the invention, there are included a focused ion beam optical system and an electron optical system in one vacuum container, and a minute sample containing a desired area of the sample is separated by forming processing with a charged particle beam, and there are included a manipulator for extracting the separated minute sample, and a manipulator controller for driving the manipulator independently of a wafer sample stage.

Abstract: Embodiments of the invention generally provide a substrate support assembly. In one embodiment, a substrate support assembly includes a substrate support plate, a thermal regulating plate coupled in a spaced-apart relation to the substrate support plate and a main actuator coupled in a spaced-apart relation to the thermal regulating plate. The main actuator is adapted to move the substrate support plate laterally. The substrate support assembly is configured to limit the thermal influence of the main actuator on a substrate positioned on the substrate support plate.

Abstract: A display of wavelength elements can be produced from resonant structures that emit light (and other electromagnetic radiation having a dominant frequency higher than that of microwave) when exposed to a beam of charged particles, such as electrons from an electron beam. An exemplary display with three wavelengths per pixel utilizes three resonant structures per pixel. The spacings and lengths of the fingers of the resonant structures control the light emitted from the wavelength elements. Alternatively, multiple resonant structures per wavelength can be used as well.

Abstract: A UV LED device may be used for curing fluids. In one embodiment, LEDs are positioned on faces defined by an inverted recess in a base portion. The LEDs are configured such that the light beams emitted from the LEDs converge at a single area or point to provide a single, focused area or point of amplified power from the LEDs. In another embodiment, the base portion is elongated to provide a single, focused line or region of amplified power from the LEDs. In another embodiment, the curing process occurs in an inert atmosphere. In one embodiment, a printed circuit is disposed in the base portion to provide power to the LEDs.

Abstract: A phase change material is formed over a dielectric material. An impurity is introduced into the dielectric to improve the adherence of said dielectric to said phase change material.

Abstract: With a high-speed nonvolatile phase change memory, reliability in respect of the number of refresh times is enhanced. In a memory cell forming area of a phase change memory using a MISFET as a transistor for selection of memory cells, a phase change material layer of a memory cell comprising a resistor element, using a phase change material, is formed for common use. As a result, variation in shape and a change in composition of the phase change material, caused by isolation of memory cell elements by etching, are reduced, thereby enhancing reliability of memory cells, in respect of the number of refresh times.

Abstract: A phase change RAM device, has a first metal wiring for a bit line that is separated from a second metal wiring for applying a supply voltage. A method for fabricating the phase change RAM device includes the steps of forming an isolation layer formed so as to define a T-shaped active area in the semiconductor substrate, forming a word line formed on the active area of the semiconductor substrate including the isolation layer, forming source/drain areas formed at both sides of the word line in the active area, forming an insulating interlayer on entire surface of the semiconductor substrate so as to cover the word line, and forming a first tungsten plug in a portion of the insulating interlayer on the source area and a second tungsten plug in a portion of the insulating interlayer on the drain area.

Abstract: A magnetic body composed of non-magnetic material, includes a plurality of localized electron regions in each of which at least one electron is confined to form a localized spin, a barrier potential region having a higher energy than a Fermi energy of an electron in the localized electron region and permitting an electron to be confined in the respective localized electron regions, and a conductive electron region including a conductive electron system having a lower energy than an energy of the barrier potential region, wherein the respective localized electron regions are disposed separate from one another via the barrier potential region and the conductive electron region.

Abstract: A solid-state optical device having: a solid-state element; a power supplying/retrieving portion that supplies or retrieves electric power to/from the solid-state element; and a glass sealing material that seals the solid-state element. The glass sealing material is made of a P2O5—ZnO-based low-melting glass that has 45 to 50 wt % of P2O5 and 15 to 35 wt % of ZnO.

Abstract: A method for fabricating a circuitry component includes providing a semiconductor substrate, a first coil over said semiconductor substrate, a passivation layer over said first coil; and depositing a second coil over said passivation layer and over said first coil. Said second coil may be deposited by forming a first metal layer over said passivation layer, forming a pattern defining layer over said first metal layer, a first opening in said pattern defining layer exposing said first metal layer, forming a second metal layer over said first metal layer exposed by said first opening, removing said pattern defining layer, and removing said first metal layer not under said second metal layer.

Abstract: Red phosphorescene compounds and organic electro-luminescence device using the same are disclosed. In an organic electroluminescence device including an anode, a hole injecting layer, a hole transport layer, a light emitting layer, an electron transport layer, an electron injecting layer, and a cathode serially deposited on one another, the organic electroluminescence device may use a compound as a dopant of the light emitting layer.

Abstract: Techniques are provided for fuse/anti-fuse structures, including an inner conductor structure, an insulating layer spaced outwardly of the inner conductor structure, an outer conductor structure disposed outwardly of the insulating layer, and a cavity-defining structure that defines a cavity, with at least a portion of the cavity-defining structure being formed from at least one of the inner conductor structure, the insulating layer, and the outer conductor structure. Methods of making and programming the fuse/anti-fuse structures are also provided.

Abstract: A silicon carbide semiconductor device includes a semiconductor element disposed in a semiconductor substrate having a first conductive type silicon carbide layer and a silicon substrate. The device includes: a trench on the silicon carbide layer to reach the silicon substrate; and a conductive layer in the trench between the silicon carbide layer and the silicon substrate to connect to both of them. The semiconductor element is a vertical type semiconductor element so that current flows on both of a top surface portion and a backside surface portion of the semiconductor substrate. The current flows through the conductive layer.

Abstract: A thin film transistor, and a flat panel display with the same, including a gate electrode, source and drain electrodes, an organic semiconductor layer, and a gate insulating layer. A first capacitance is a capacitance at a first point where the organic semiconductor layer, an electrode, and the gate insulating layer contact one another, a second capacitance is a capacitance at a second point where the organic semiconductor layer contacts the gate insulating layer, a third capacitance is a capacitance at a third point where the electrode contacts the gate insulating layer, and a fourth capacitance is a capacitance at a fourth point where the organic semiconductor layer contacts the electrode. The first capacitance is greater than one of the second capacitance, the third capacitance, and the fourth capacitance.

Abstract: A liquid crystal display (LCD) panel is fabricated in a simplified process. The LCD panel includes a thin film transistor (TFT) array substrate with a gate and data lines crossing each other to define a pixel area, a TFT at the crossings of the gate and data lines, a protective film, and a pixel electrode connected to the TFT and formed within a pixel opening that is arranged at the pixel area and formed through the protective film and a gate insulating film. A color filter array substrate is joined to the TFT array substrate. A pattern spacer is between the TFT and color filter array substrate and overlaps at least one of the gate line, the data line, and the thin film transistor. A rib is formed from the same layer as the pattern spacer and overlaps the pixel electrode. Liquid crystal material is provided within the LCD panel.

Abstract: An organic light emitting display device may include: a substrate having first, second and third pixel regions. A first electrode layer may be formed in each of the first, second and third pixel regions on the substrate. A hole injection layer may be formed over an entire surface of the substrate on the first electrode layers. A first hole transport layer may be formed on the first electrode layers in the first, second and third pixel region. A second hole transport layer may be formed on the first hole transport layer in any two adjacent pixel regions among the first, second and third pixel regions. A third hole transport layer may be formed on the second hole transport layer in any one of the two adjacent pixel region. A first, second and third organic emission layers may be formed on the first, second and third hole transport layer. A second electrode layer may be formed on the first, second and third organic emission layers.

Abstract: In a radiation-emitting optoelectronic semiconductor chip comprising an active layer (3) at least one p-doped layer (9) and a layer sequence (8) comprising a plurality of undoped layers (4, 5, 6, 7), which is arranged between the active layer (3) and the p-doped layer (9) and contains at least a first undoped layer (5) and a second undoped layer (6), the second undoped layer adjoining the first undoped layer (5) and succeeding the first undoped layer (5) as seen from the active layer (3), the first undoped layer (5) and the second undoped layer (6) in each case contain aluminum, the aluminum proportion being greater in the first undoped layer (5) than in the second undoped layer (6). The layer sequence (8) advantageously acts as a diffusion barrier for the dopant of the p-doped layer.

Abstract: An LED packaging construction has a chip embedded on a recessed carrier on substrate; conduction circuits with different electrodes being disposed to the peripheral of the carrier; electrode layer of chip being connected to conduction circuits with golden plated wire; fluorescent powder being filled in the carrier before mounting the colloid on the powder layer; coverage of colloid extending to substrate to complete LED packaging; larger binding range between colloid and substrate yielding better strength and increased light-emitting angle of the chip through the colloid.

Abstract: It is to be made easy to arrange light emitting diodes, each including a lens having a hemispherical light emitting surface, and cover the base of the light emitting diodes with resin material. A light emitting diode 1 has a light emitting element 2, a lead section 3 that supplies power to the light emitting element 2, a base 4 that covers the lead section 3, a lens 5 having a convex light emitting surface and connected to the base 4 to cover the light emitting element 2, and a step section 6 disposed such that it surrounds the outer side of the lens 5, part of the step 6 having a different width. The step section 6 has a height that defines the amount of resin material enough to cover the lead section 3. There is also provided a light emitting diode display device 10 using a plurality of such light emitting diodes.

Abstract: An optical module comprises: a stem; a protruding portion on a surface of the stem; an optical semiconductor device mounted on the protruding portion; a power supply terminal penetrating through the stem, the power supply terminal being insulated from the stem; a first dielectric substrate mounted on the protruding portion; a first signal line on the first dielectric substrate and connected to a first end of the power supply terminal; a second dielectric substrate on a rear surface of the stem; and a second signal line on the second dielectric substrate and connected to a second end of the power supply terminal. The second signal line has an electrical length of 23.0-36.2 mm and an impedance of 21.5-24.5?.

Abstract: In a nitride semiconductor light emitting device having patterns formed on the upper and lower surfaces of a substrate from which light is emitted in a flip chip bonding structure, the patterns are capable of changing light inclination at the upper and lower surfaces of the substrate to decrease total reflection at the interfaces, thereby improving light emitting efficiency.

Abstract: A semiconductor device is disclosed that includes a first and a second semiconductor package. Each semiconductor package includes a semiconductor element, a plurality of electrode members, and an encapsulating member. The semiconductor elements are interposed between the respective electrode members, and the electrode members are in electrical communication with and provide heat transfer for the respective semiconductor element. The encapsulating member encapsulates the respective semiconductor element between the respective electrode members, and an outer surface of each of the electrode members is exposed from the respective encapsulating member. Each semiconductor package includes a connecting terminal electrically coupled to one of the electrode members and extending outward so as to be exposed from the respective encapsulating member. The connecting terminals are electrically connected by abutment or via a conductive junction material.

Abstract: An UV detector, comprising: a sapphire substrate; a high temperature AlN buffer layer grown on the sapphire substrate; an intermediate temperature GaN buffer layer grown on the high temperature AlN buffer layer; a GaN epitaxial layer deposited on the intermediate temperature GaN buffer layer; a Schottky junction formed on top of the GaN epitaxial layer; and a plurality of ohmic contacts also formed on top of the GaN epitaxial layer, wherein, the high temperature AlN buffer layer and the intermediate temperature GaN buffer layer together form a double buffer layer structure so as to improve the reliability and radiation hardness of the UV detector; and wherein the high temperature AlN buffer layer and the intermediate temperature GaN buffer layer are formed by RF-plasma enhanced MBE growth technology.

Abstract: A method for fabricating heterojunction field effect transistors (HFET) and a family of HFET layer structures are presented. In the method, a step of depositing a HFET semiconductor structure onto a substrate is performed. Next, a photoresist material is deposited. Portions of the photoresist material are removed corresponding to source and drain pad pairs. A metal layer is deposited onto the structure, forming source pad and drain pad pairs. The photoresist material is removed, exposing the structure in areas other than the source and drain pad pairs. Each source and drain pad pair has a corresponding exposed area. The structure is annealed and devices are electrically isolated. The exposed area of each device is etched to form a gate recess and a gate structure is formed in the recess. Semiconductor layer structures for GaN/AlGaN HFETs are also presented.

Abstract: A thin film transistor array, an electrostatic discharge protective device thereof, and methods for fabricating the same are provided. The thin film transistor array comprises a plurality of scan lines, a plurality of data lines, a first shorting bar, and a second shorting bar. The electrostatic discharge protective device comprises a switching device and a resistance line in parallel. If static electricity accumulated on the TFT array is over a predetermined range, the accumulated static electricity will be conducted to the first or second shorting bar via the switching device. The resistance line can prevent signals applied to one of the scan lines or data lines from being conducted to other scan lines or data lines, to detect a defective pixel.

Abstract: The present invention relates to a semiconductor device that comprises at least one field effect transistor (FET) containing a source region, a drain region, a channel region, a gate dielectric layer, a gate electrode, and one or more gate sidewall spacers. The gate electrode of such an FET contains an intrinsically stressed gate metal silicide layer, which is laterally confined by one or more gate sidewall spacers and is arranged and constructed for creating stress in the channel region of the FET. Preferably, the semiconductor device comprises at least one p-channel FET, and more preferably, the p-channel FET has a gate electrode with an intrinsically stressed gate metal silicide layer that is laterally confined by one or more gate sidewall spacers and is arranged and constructed for creating compressive stress in the p-channel of the FET.

Abstract: A solid-state image sensor of the present invention has a plurality of pixel cells that generate signal charges in accordance with incident light. It is characterized by having a gettering region within the area of a pixel cell. The gettering region, which is disposed closely to the photoelectrical conversion layer, makes direct and efficient use of gettering capability in the pixel region in the solid-state image sensor. As a result, it is possible to effectively eliminate metal contaminant contained in the pixel region, thereby remarkably reducing dark outputs occurring from the metal contaminant.

Abstract: A CMOS image sensor is described, based on a substrate and including a transfer transistor, a reset transistor, a source follower transistor, a select transistor, a photodiode and a floating node structure. The substrate includes a floating node area between the transfer transistor and the reset transistor. The floating node structure includes a P-well in the substrate within the floating node area, an N-well in the substrate outside of the floating node region, a lightly N-doped region having a portion in the P-well and another portion connected with the N-well, a heavily N-doped region in the N-well, and a contact plug for coupling the heavily N-doped region to the source follower transistor.

Abstract: A triple-junction complimentary metal-oxide-semiconductor (CMOS) filterless color imager cell is provided. The imager cell is made from a bulk silicon (Si) substrate. A photodiode set including a first, second, and third photodiode are formed as a triple-junction structure in the Si substrate. A transistor set is connected to the photodiode set, and detects an independent output signal for each photodiode. Typically, the transistor set is formed in the top surface of the substrate. For example, the Si substrate may be a p-doped Si substrate, and the photodiode triple-junction structure includes the first photodiode forming a pn junction from an n+-doped region at the Si substrate top surface, to an underlying p-doped region. The second photodiode forms a pn junction from the p-doped region to an underlying n-well, and the third photodiode forms a pn junction from the n-well to the underlying p-doped Si substrate.

Abstract: A semiconductor memory includes memory cell transistors comprising a tunnel insulating film, a floating gate electrode, a first insulating film, a control gate electrode, and a first metal salicide film; low-voltage transistors comprising a first p-type source region and a first p-type drain region, a first gate insulating film, and a first gate electrode of an n conductivity type having the same dose of a first p-type impurity as with the first p-type source region; and high-voltage transistors comprising a second p-type source region and a second p-type drain region, a second gate insulating film thicker than the first gate insulating film, and a second gate electrode of an n conductivity type having the same dose of a second p-type impurity as with the second p-type source region.

Abstract: A NAND-type non-volatile semiconductor memory device includes a gate insulating layer on an active region of a semiconductor substrate, first and second select gate structures on the active region, and a memory gate structure therebetween. The first and second select gate structures respectively include a plurality of select gate patterns, and the memory gate structure includes a plurality of storage gate patterns. The gate insulating layer includes a plurality of openings therein exposing portions of the active region between ones of the plurality of select gate patterns of the first and second select gate structures. The device may further include impurity regions in portions of the active region between the gate patterns, and halo regions adjacent ones of the impurity regions in the portions of the active region exposed by the openings in the gate insulating layer. Related fabrication methods are also discussed.

Abstract: A nonvolatile memory cell has a charge trapping layer for the storage of charges thereon. The cell is a bidirectional cell in a substrate of a first conductivity. The cell has two spaced apart trenches. Within each trench, at the bottom thereof is a region of a second conductivity. A channel extends from one of the region at the bottom of one of the trenches along the side wall of that trench to the top planar surface of the substrate, and along the sidewall of the adjacent trench to the region at the bottom of the adjacent trench. The trapping layer is along the sidewall of each of the two trenches. A control gate is in each of the trenches capacitively coupled to the trapping layer along the sidewall and to the region at the bottom of the trench. Each of the trenches can stored a plurality of bits.

Abstract: A TFT substrate with reduced pixel defect rate is presented. The TFT substrate includes a pixel electrode, a negative line to apply a reverse voltage to the pixel electrode, and a recovery transistor including a drain electrode overlapping a part of the negative line with a insulating layer disposed between the negative line and the drain electrode. A contact hole is formed on the negative line and the drain electrode, and a bridge electrode connects the negative line and the drain electrode through the contact hole. The thin film transistor substrate and a display apparatus presented herein protect a data line assembly metal layer and decrease pixel defect. An improved reverse voltage efficiency is applied to a pixel electrode to protect a drain electrode.

Abstract: A semiconductor device (51) is provided herein. The semiconductor device comprises (a) a substrate (57), a semiconductor layer (53) disposed on said substrate and comprising a horizontal region (54) and a fin which extends above, and is disposed adjacent to, said horizontal region, and (c) at least one channel region (63) defined in said fin and in said horizontal region.

Abstract: A power IGBT includes a semiconductor body having an emitter zone of a first conduction type and a drift zone of a second conduction type proximate to the emitter zone. The IGBT further includes a cell array, each transistor cell of the array having a source zone, a body zone disposed between the source zone and the drift zone, the body zone and source zone short-circuited, and a gate electrode configured to be insulated with respect to the source zone and the body zone. The cell array has a first cell array section with a first cell density and a second cell array section with a second cell density that is lower than the first cell density. The emitter zone has a lower emitter efficiency in a region corresponding to the second cell array section than in a region corresponding to the first cell array section.

Abstract: The invention is intended to present an insulated gate type semiconductor device that can be manufactured easily and its manufacturing method while realizing both higher withstand voltage design and lower on-resistance design. The semiconductor device comprises N+ source region 31, N+ drain region 11, P? body region 41, and N? drift region 12. By excavating part of the upper side of the semiconductor device, a gate trench 21 is formed. The gate trench 21 incorporates the gate electrode 22. A P floating region 51 is provided beneath the gate trench 21. A further trench 35 differing in depth from the gate trench 21 may be formed, a P floating region 54 being provided beneath the trench 25.

Abstract: A method and resultant device, in which metal nanoparticles are self-assembled into two-dimensional lattices. A periodic hole pattern (wells) is fabricated on a photoresist substrate, the wells having an aspect ratio of less than 0.37. The nanoparticles are synthesized within inverse micelles of a polymer, preferably a block copolymer, and are self-assembled onto the photoresist nanopatterns. The nanoparticles are selectively positioned in the holes due to the capillary forces related to the pattern geometry, with a controllable number of particles per lattice point.

Abstract: An integrated circuit (IC) with negative potential protection includes at least one double-diffused metal-oxide semiconductor (DMOS) cell formed in a first-type epitaxial pocket, which is formed in a second-type substrate. The IC also includes a second-type+ isolation ring formed in the substrate to isolate the first-type epitaxial pocket and a first-type+ ring formed through the first-type epitaxial pocket between the second-type+ isolation ring and the DMOS cell.

Abstract: A semiconductor device has a semiconductor base, an anode electrode, and a cathode electrode. The semiconductor base includes a P type semiconductor substrate, an insulating film, an N? type semiconductor region formed on the insulating film, an N+ type semiconductor region, and a P+ type semiconductor region facing the N+ type semiconductor region via the N? type semiconductor region. The semiconductor device further has an N type diffusion layer which is formed, in the N? type semiconductor region at the interface between the insulating film and the N? type semiconductor region, so as to have a concentration gradient such that the N type impurity concentration increases from the side of the anode electrode to the side of the cathode electrode.

Abstract: An electrostatic discharge (“ESD”) protection device, which includes a thyristor circuit, in the ESD case increases a resistance of the ESD protection device in comparison with a non-ESD case, by means of a switch. An ESD protection arrangement may include a ESD protection device to protects circuits with multiple voltage potentials. An ESD protection system may also include an ESD protection arrangement, to which an ESD signal is fed via a bus of the ESD protection system. The ESD protection device and ESD protection arrangement, and thus the ESD protection system, can be provided in a compact semiconductor arrangement.

Abstract: A semiconductor device includes a field effect transistor and a pn junction diode formed on a substrate. The field effect transistor has a source electrode, a drain electrode and a gate electrode formed on an element forming layer including a plurality of nitride semiconductor layers. The diode includes a p-type nitride semiconductor layer selectively formed on the element forming layer and an ohmic electrode, and has a pn junction formed between an n-type region of a two-dimensional electron gas generated on a heterojunction interface and a p-type region of the p-type nitride semiconductor layer. The diode is electrically connected to the gate electrode and forms a current path for allowing an excessive current caused in the gate electrode to pass.

Abstract: Disclosed is a circuit for preventing charging damage in an integrated circuit design, for example, a design having silicon over insulator (SOI) transistors. The circuit prevents damage from charging during processing to the gate of IC devices by assigning regions to the IC design such that the devices located within the regions have electrically independent nets, identifying devices that may have a voltage differential between the source or drain, and gate as susceptible devices within a given region, and connecting an element across the source or drain, and the gate of each of the susceptible devices such that the element is positioned within the region. Alternatively, the method/circuit provides for connecting compensating conductors to an element to eliminate potential charging damage.

Abstract: A semiconductor device which eases an electric field at a drift portion without a reduction in impurity concentrations, and has a high withstand voltage and a low on-resistance, wherein, when a rated voltage is applied between a body region and a drain region formed on an insulating semiconductor substrate, the thicknesses of two, p-type and n-type, drift regions sandwiched between the body and drain regions are selected so as to completely deplete the drift regions.

Abstract: A semiconductor device provided with a semiconductor silicon substrate and gate wiring provided on the semiconductor silicon substrate via a gate oxide film, where the gate wiring has a gate electrode, a gate wiring upper structure provided in contact with the gate electrode, and a side wall spacer, the side wall spacer is comprised of one kind or two or more kinds of inorganic compound insulating layers, and at least one kind of the inorganic compound insulating layer is comprised of silicon oxynitride with a nitrogen content ranging from 30 to 70%.