Patents Issued in January 19, 2010
  • Patent number: 7648820
    Abstract: Antireflective hardmask compositions and techniques for the use of antireflective hardmask compositions for processing of semiconductor devices are provided. In one aspect of the invention, an antireflective hardmask layer for lithography is provided. The antireflective hardmask layer comprises a carbosilane polymer backbone comprising at least one chromophore moiety and at least one transparent moiety; and a crosslinking component. In another aspect of the invention, a method for processing a semiconductor device is provided. The method comprises the steps of: providing a material layer on a substrate; forming an antireflective hardmask layer over the material layer. The antireflective hardmask layer comprises a carbosilane polymer backbone comprising at least one chromophore moiety and at least one transparent moiety; and a crosslinking component.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: January 19, 2010
    Assignee: International Business Machines Corporation
    Inventors: Katherina Babich, Elbert Huang, Arpan P. Mahorowala, David R. Medeiros, Dirk Pfeiffer, Karen Temple
  • Patent number: 7648821
    Abstract: A multiple layer photosensitive element having at least three differently sensitised photosensitive layers on one side of a support, such as a, transparent flexible support, is imagewise exposed according to a desired circuit pattern and developed to form two layers of conductive track patterns from each photosensitive layer, which may then be connected together by forming vias by drilling or in situ generation. The resulting multiple layer conductive element has application in the field of printed circuit board manufacture or as the backplane electronic element of a flexible display device.
    Type: Grant
    Filed: March 24, 2006
    Date of Patent: January 19, 2010
    Assignee: Eastman Kodak Company
    Inventors: Sean D. Slater, John R. Fyson, Christopher B. Rider, David T. Clarke, Jurjen F. Winkel, Peter Hewitson
  • Patent number: 7648823
    Abstract: Systems, methods, compositions and apparatus relating to genome selection are disclosed.
    Type: Grant
    Filed: April 30, 2007
    Date of Patent: January 19, 2010
    Assignee: Searete LLC
    Inventors: W. Daniel Hillis, Roderick A. Hyde, Edward K. Y. Jung, Robert Langer, Nathan P. Myhrvold, Lowell L. Wood, Jr.
  • Patent number: 7648824
    Abstract: The present invention provides a method of identifying a base at a target position in a sample nucleic acid sequence, said method comprising: subjecting a primer hybridised to said sample nucleic acid immediately adjacent to the target position, to a polymerase primer extension reaction in the presence of a nucleotide, whereby the nucleotide will only become incorporated if it is complementary to the base in the target position, and determining whether or not said nucleotide is incorporated by detecting whether PPi is released, the identity of the target base being determined from the identity of any nucleotide incorporated, wherein, where said nucleotide comprises an adenine base, an ?-thio triphosphate analogue of said nucleotide is used, ant the Rp isomer of said analogue and/or the degradation products of said analogue are eliminated from the polymerase reaction step.
    Type: Grant
    Filed: November 26, 2008
    Date of Patent: January 19, 2010
    Assignee: Qiagen GmbH
    Inventors: Pal Nyren, Mostafa Ronaghi, Annika Tallsjo
  • Patent number: 7648825
    Abstract: Biomarkers that are diagnostic of type 1 diabetes, type 2 diabetes and/or diabetic disorder are identified. Detection of different biomarkers of the invention are also diagnostic of the degree of severity of type 1 diabetes, type 2 diabetes and/or diabetic disorder. An analysis includes the parameters of matching for BMI and Tanner stage. Receiver-operator characteristic (ROC) curves were established to assess association of the biomarkers with a disease.
    Type: Grant
    Filed: June 21, 2004
    Date of Patent: January 19, 2010
    Assignee: University of Florida Research Foundation, Inc.
    Inventors: Tamir M. Ellis, Alba Esther Morales, Mark A. Atkinson, Clive H. Wasserfall
  • Patent number: 7648826
    Abstract: This invention pertains to the discovery that an amplification of the CYP24 gene or an increase in CYP24 activity is a marker for the presence of, progression of, or predisposition to, a cancer (e.g., breast cancer). Using this information, this invention provides methods of detecting a predisposition to cancer in an animal. The methods involve (i) providing a biological sample from an animal (e.g. a human patient); (ii) detecting the level of CYP24 within the biological sample; and (iii) comparing the level of CYP24 with a level of CYP24 in a control sample taken from a normal, cancer-free tissue where an increased level of CYP24 in the biological sample compared to the level of CYP24 in the control sample indicates the presence of said cancer in said animal.
    Type: Grant
    Filed: April 2, 1999
    Date of Patent: January 19, 2010
    Assignee: The Regents of the University of California
    Inventors: Donna G. Albertson, Daniel Pinkel, Colin Collins, Joe W. Gray, Bauke Ystra
  • Patent number: 7648827
    Abstract: The present invention relates to the significant functional role of several C. elegans genes and of their corresponding gene products in cell cycle progression during cell division that could be identified by means of RNA-mediated interference (RNAi) and to the identification and isolation of functional orthologs of said genes including all biologically functional derivatives thereof. The invention further relates to the use of said genes and gene products (including said orthologs) in the development or isolation of anti-proliferative agents, particularly their use in appropriate screening assays, and their use for diagnosis and treatment of proliferative and other diseases. In particular, the invention relates to the use of small interfering RNAs derived from said genes for the treatment of proliferative diseases.
    Type: Grant
    Filed: September 15, 2004
    Date of Patent: January 19, 2010
    Assignee: Cenix BioScience GmbH
    Inventors: Christophe Echeverri, Anthony Hyman, Pierre Gönczy, Birte Sönnichsen, Steven Jones, Andrew Walsh, Liisa Koski
  • Patent number: 7648828
    Abstract: The invention is directed to a new class of biomarker in patient samples comprising dimers of ErbB cell surface membrane receptors. In one aspect, the invention includes a method of determining the status of a disease or healthful condition by correlating such condition to amounts of one or more dimers of ErbB cell surface membrane receptors measured directly in a patient sample, in particular a fixed tissue sample. In another aspect, the invention includes a method of determining a status of a cancer in a specimen from an individual by correlating measurements of amounts of one or more dimers of ErbB cell surface membrane receptors in cells of the specimen to such status, including presence or absence of a pre-cancerous state, presence or absence of a cancerous state, prognosis of a cancer, or responsiveness to treatment.
    Type: Grant
    Filed: January 21, 2005
    Date of Patent: January 19, 2010
    Assignee: Monogram Biosciences, Inc.
    Inventors: Po-Ying Chan-Hui, Rajiv Dua, Ali Mukherjee, Sailaja Pidaparthi, Hossein Salimi-Moosavi, Yining Shi, Sharat Singh
  • Patent number: 7648829
    Abstract: A method and kit for detecting Trichomonas vaginalis infection in a human subject are disclosed. In the method, a body-fluid sample such as a vaginal-swab sample or urine is obtained from the subject and contacted with an antibody specific against a Trichomonas adhesin peptide, forming an antibody-adhesin peptide complex if the subject is infected with Trichomonas. The presence or absence of the complex establishes, with a reliability of at least 80%, in the case of a vaginal swab sample, and with a reliability of at least 40% in the case of a urine sample, the presence or absence, respectively, of Trichomonas infection in the subject. A preferred test kit employs a dry-strip, sandwich assay, format.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: January 19, 2010
    Assignee: Xenotope Diagnostics, Inc.
    Inventors: John P. Alderete, Paul C. Castella
  • Patent number: 7648830
    Abstract: A method is provided for determining the presence of a target bacteria based on its resistance to a cell lysing antibiotic. Said antibiotic is used to lyse cells of non-target bacteria in a sample and hence facilitate isolation of the target prior to detection by known means.
    Type: Grant
    Filed: September 2, 2002
    Date of Patent: January 19, 2010
    Assignee: The Secretary of State for Defence in Her Britannic Majesty's Government of the United Kingdom of Great Britain and Northern Ireland
    Inventors: David James Squirrell, Rachel Louise Leslie, Kevin J Bown
  • Patent number: 7648831
    Abstract: The purpose of the present invention is to provide a process for protection of enzymatic biocatalysts, constituted by a primary support, wrapped by a secondary matrix. More particularly, the invention is embodied as a bioreactor with a configuration that preserves the physical integrity and catalytic activity of the biocatalyst after long runs, and at the same time allows an easy separation of the protected biocatalyst from the solid, precipitated during the reaction course. Still more particularly, the invention refers to the use of the bioreactor herein described for the enzymatic synthesis of ?-lactam antibiotics, including the insoluble enzymatic catalysts, which have a primary matrix for immobilization involved by a secondary matrix, which is able to preserve 100% of the catalyst physical integrity and approximately 100% of its catalytic activity.
    Type: Grant
    Filed: November 24, 2003
    Date of Patent: January 19, 2010
    Assignees: Fundacao Universidade Federal de Sao Carlos, Fundacao de Amparo a Pesquisa do Estado de Sao Paulo
    Inventors: Roberto de Campos Giordano, Raquel de Lima Camargo Giordano, Andrea Lopes de Oliveira Ferreira
  • Patent number: 7648832
    Abstract: This invention relates to a method for producing cells which are competent for transformation and which may be stably stored for extended periods of time at various temperatures. The method involves growing cells in a growth conducive medium, rendering said cells competent, and lyophilizing said competent cells. The invention further relates to competent cells produced by such a method, to methods of transforming said cells with a DNA molecule, and to a method of producing a desired protein or polypeptide from said transformed cells.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: January 19, 2010
    Assignee: Life Technologies, Corp.
    Inventors: Joel A. Jessee, Fredric R. Bloom, Thuan Trinh
  • Patent number: 7648833
    Abstract: The invention relates to a vessel for embryoid formation used for forming embryoid bodies from ES cells easily without complicated technique, and to a method for forming embryoid bodies easily and efficiently using the vessel. The method includes the steps of (A) providing a vessel for embryoid formation having a coating layer formed from a compound having a particular PC-like group on a vessel surface defining a region for floating culture of ES cells, and (B) floating culturing ES cells in the vessel to form embryoid bodies.
    Type: Grant
    Filed: June 25, 2004
    Date of Patent: January 19, 2010
    Assignee: NOF Corporation
    Inventors: Hiroshi Kurosawa, Shujiro Sakaki
  • Patent number: 7648834
    Abstract: The sensitivity and durability of fluorescent assays may be increased through structures and methods using plasmon fluorescence augmentation and sealing of the structure against degradation by reagents used in the assay. The resulting structures make practical extremely sensitive fluorescent assays for DNA and other biological analytes.
    Type: Grant
    Filed: January 17, 2006
    Date of Patent: January 19, 2010
    Inventor: Wayne E. Moore
  • Patent number: 7648835
    Abstract: An integrated heat exchange system on a microfluidic card. According to one aspect of the invention, the portable microfluidic card has a heating, cooling and heat cycling system on-board such that the card can be used portably. The microfluidic card includes one or more reservoirs containing exothermic or endothermic material. Once the chemical process of the reservoir material is activated, the reservoir provides heat or cooling to specific locations of the microfluidic card. Multiple reservoirs may be included on a single card to provide varying temperatures. The assay chemicals can be moved to the various reservoirs to create a thermal cycle useful in many biological reactions, for example, Polymerase Chain Reaction (PCR) or rtPCR.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: January 19, 2010
    Assignee: Micronics, Inc.
    Inventors: Wayne L. Breidford, Christy A. Lancaster, Jon W. Hayenga, Ronald L. Bardell, Jeffrey F. Tonn, Bernhard H. Weigl
  • Patent number: 7648836
    Abstract: Systems and methods for measuring the moisture and sediment content of a sample. In one embodiment, a sample to be tested is collected in a field bottle. The sample from the field bottle is then transferred from the field bottle, and into and through an analysis bottle containing a desiccant material. As the sample is being pulled through the analysis bottle, a microwave measurement system (or other scattering parameter measuring system) is used to measure the effects of the sample on the scattering parameters of the desiccant material. By measuring the effects of the sample on the scattering parameters of the desiccant material, the sample's moisture content can be determined. The sample's moisture can also be determined by measuring the expanded volume of the desiccant. A filter section having a sight glass with graduations is used to determine the sediment content of the sample.
    Type: Grant
    Filed: January 28, 2005
    Date of Patent: January 19, 2010
    Assignee: Phase Dynamics, Inc.
    Inventor: Bentley N. Scott
  • Patent number: 7648837
    Abstract: A method for determining oxidation stability for a plurality of different lubricating oil composition samples is provided. The methods can advantageously be optimized using combinatorial chemistry, in which a database of combinations of lubricating oil compositions is generated. As market conditions vary and/or product requirements or customer specifications change, conditions suitable for forming desired products can be identified with little or no downtime.
    Type: Grant
    Filed: April 9, 2008
    Date of Patent: January 19, 2010
    Assignee: Chevron Oronite Company, LLC
    Inventors: Robert H. Wollenberg, Thomas J. Balk
  • Patent number: 7648838
    Abstract: Provided is a lysis method for cells or viruses, including: immobilizing a metal-ligand complex on a solid support; and mixing the complex immobilized on the support with a cell or virus solution. According to the lysis method, by immobilizing a chemical on a solid support to perform cell lysis, the dilution problem according to the addition of a cell lysis solution can be resolved and a separate process of removing the chemical is not required so as to reduce the steps upon LOC implementation. In addition, since a variety of solid supports, such as chips, beads, nanoparticles etc. can be used, cell lysis apparatuses of various forms can be fabricated.
    Type: Grant
    Filed: November 4, 2005
    Date of Patent: January 19, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-eun Yoo, Joon-ho Kim, Kyu-youn Hwang, Hun-joo Lee, Hee-kyun Lim, Soo-min Ma, Nam Huh, Soo-suk Lee
  • Patent number: 7648839
    Abstract: To provide a novel copper ion indicator which is less influenced by interfering metal ions and which is useful for measurement of copper ion within a wide concentration range. The invention provides a copper ion indicator containing a compound represented by formula (1): [wherein each of R1, R2, R3, R4, R5, and R6 represents a hydrogen atom or an alkali metal atom], and a method for determining copper ion concentration, which employs the indicator.
    Type: Grant
    Filed: June 21, 2005
    Date of Patent: January 19, 2010
    Assignee: Kowa Co., Ltd.
    Inventors: Maria Sakairi, Katsumi Yabusaki
  • Patent number: 7648840
    Abstract: The invention features methods and compositions for diagnosis, including prognosis, of conditions associated with decreased arginine bioavailability (which can result from dysregulated arginine metabolism, e.g., due to increased arginase activity) by assessing in a sample from a subject the ratio of arginine to one or more, usually two or more, modulators of arginine bioavailability. In one embodiment, the ratio of arginine to (ornithine+citrulline) is assessed to aid in diagnosis.
    Type: Grant
    Filed: December 1, 2005
    Date of Patent: January 19, 2010
    Assignees: Children's Hospital & Research Center at Oakland, The Cleveland Clinic Foundation
    Inventors: Claudia R. Morris, Stanley L. Hazen
  • Patent number: 7648841
    Abstract: The present invention relates to a reagent for determining the absolute configuration of a chiral compound containing as an active ingredient a metalloporphyrin dimer, wherein the metalloporphyrin dimer has an alkaline-earth metal ion as a central metal and has a carbon chain-crosslinked structure in which at least one of the two porphyrin rings has a substituent bulkier than methyl at least one of the second carbon atoms from a carbon atom bonded to the crosslinking carbon chain along the outer periphery of the porphyrin ring and a method for determining the absolute configuration of an asymmetric carbon atom of the chiral compound using the reagent.
    Type: Grant
    Filed: January 10, 2003
    Date of Patent: January 19, 2010
    Assignee: Japan Science and Technology Agency
    Inventors: Yoshihisa Inoue, Victor Borovkov, Juha Lintuluoto
  • Patent number: 7648842
    Abstract: The present invention relates to a unique dual color security paper authentication system. The authenticating system comprises the combination of a security paper together with a coordinated applicator. The paper contains a starch, an iodide salt and an acidic developer resin. The applicator of the system comprises two authenticating solutions. The first authenticating solution comprises one or more of a sulfonamide and a copper salt dispersed in a solvent. The second authenticating solution comprises one or more of a leuco and fluoran dye precursor dispersed in a solvent. On applying the authenticating solutions to authentic security paper, a first color of a starch iodine is expressed and a second color of a leuco or fluoran dye is expressed.
    Type: Grant
    Filed: April 4, 2007
    Date of Patent: January 19, 2010
    Assignee: Appleton Papers Inc.
    Inventor: Tianyan Xie Hartlep
  • Patent number: 7648843
    Abstract: This invention pertains to a surface ligand; preparation of the ligand; colloidal nanoparticle, such as quantum dot bearing one or more of the ligand; and a bioconjugate characterized by a nanoparticle bearing one or more of the ligand conjugated to a biomolecule. The ligand is characterized by the presence of a first module containing atoms that can attach to an inorganic surface; a second module that imparts water-solubility to the ligand and to the inorganic surface that may be attached to the ligand; and a third module that contains a functional group that can, directly or indirectly, conjugate to a biomolecule. Order of the modules can be different and other modules and groups can be on the ligand. Preparation of the ligand includes the steps of reacting a compound having atoms that can attach to an inorganic surface with a water-solubilizing compound that imparts the property of water-solubility to the ligand and the inorganic surface to which it may be attached and purification thereof.
    Type: Grant
    Filed: July 10, 2007
    Date of Patent: January 19, 2010
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Harry Tetsuo Uyeda, Hedi M Mattoussi, Igor L Medintz
  • Patent number: 7648844
    Abstract: Methods for detecting analytes in a sample are provided. A plurality of particles, each of which is coated with a capture agent having an affinity for the analyte, is combined with the sample to form a plurality of analyte-particle complexes. The system also includes a transport arrangement for transporting the sample to the sensor surface, and a magnetic field inducing structure constructed and arranged to establish a magnetic field at and adjacent to the sensor surface. The resonant sensor produces a signal corresponding to an amount of analyte-particle complexes that are bound to the sensor surface.
    Type: Grant
    Filed: May 2, 2006
    Date of Patent: January 19, 2010
    Assignee: BioScale, Inc.
    Inventors: Alok Srivastava, Wayne U. Wang, Michael Miller, Brett P. Masters, Mark Lundstrom
  • Patent number: 7648845
    Abstract: Briefly described, embodiments of this disclosure include structures, methods of forming the structures, and methods of using the structures. One exemplary structure, among others, includes a nanospecies and a porous material. The nanospecies has a first characteristic and a second detectable characteristic. In addition, a second detectable energy is produced corresponding to the second detectable characteristic upon exposure to a first energy. The porous material has the first characteristic and a plurality of pores. The first characteristic causes the nanospecies to interact with the porous material and become disposed in the pores of the porous material.
    Type: Grant
    Filed: March 20, 2006
    Date of Patent: January 19, 2010
    Assignee: Emory University
    Inventors: Shuming Nie, Xiaohu Gao
  • Patent number: 7648846
    Abstract: An active matrix substrate including a substrate, a plurality of pixel units, a plurality of driving lines, an electron static discharge (ESD) protection circuit and a floating line is provided. The substrate has an active region and a peripheral region connected with the active region. The pixel units are arranged in a matrix in the active region. The driving lines electrically connected to the pixels are disposed in the active region and the peripheral region. The ESD protection circuit and the floating line are disposed in the peripheral region of the substrate. The ESD protection circuit is electrically connected to the driving lines. The ESD protection circuit includes an outer short ring (OSR) and an inner short ring (ISR) disposed between the pixel units and the OSR. The floating line is located beside the outer driving line.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: January 19, 2010
    Assignee: Au Optronics Corporation
    Inventor: Han-Chung Lai
  • Patent number: 7648847
    Abstract: A monitoring system includes a monitor chip or chips soldered to a printed wiring board. By mirroring a function IC chip interface with the monitor chip, the consumed and remaining thermal/and or vibration-fatigue life of the function IC chip based on the life-environment actually experienced through monitoring of the monitor chip is readily determined. The monitor chip includes monitoring interconnections and/or circuitry which determines the number and/or location of failed-open solder terminations of the monitor chip.
    Type: Grant
    Filed: June 26, 2006
    Date of Patent: January 19, 2010
    Assignee: Hamilton Sundstrand Corporation
    Inventor: Ted R. Schnetker
  • Patent number: 7648848
    Abstract: A semiconductor integrated circuit production method prepares an SOI layer thickness database that correlates measurement data of each SOI layer thickness with each SOI substrate identification data. The production method extracts the measurement data for each SOI substrate from the SOI layer thickness database, and carries out layer thickness adjustment surface treatment for the SOI substrates based on these data. A semiconductor integrated circuit production device includes an SOI layer thickness database storage unit for storing the SOI layer thickness database, and a layer thickness adjustment conditions control unit for extracting the measurement data for each SOI substrate from the SOI layer thickness database and deciding conditions for the layer thickness adjustment surface treatment based on these data.
    Type: Grant
    Filed: March 6, 2008
    Date of Patent: January 19, 2010
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Michihiro Ebe, Masao Okihara
  • Patent number: 7648849
    Abstract: A flip chip-type nitride semiconductor light emitting diode includes a light transmittance substrate, an n-type nitride semiconductor layer, an active layer, a p-type nitride semiconductor layer and a mesh-type DBR reflecting layer. The mesh-type DBR reflecting layer has a plurality of open regions. The mesh-type DBR reflecting layer is composed of first and second nitride layers having different Al content. The first and second nitride layers are alternately stacked several times to form the mesh-type DBR reflecting layer. An ohmic contact layer is formed on the mesh-type DBR reflecting layer and on the p-type nitride semiconductor layer.
    Type: Grant
    Filed: November 1, 2007
    Date of Patent: January 19, 2010
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jae Hoon Lee, In Eung Kim, Yong Chun Kim, Hyun Kyung Kim, Moon Heon Kong
  • Patent number: 7648850
    Abstract: A method for producing many semiconductor chips, each having a semiconductor circuit disposed on the face thereof and a die bonding film stuck to the back thereof, from a semiconductor wafer in which many rectangular regions are defined on its face by streets arranged in a lattice pattern, and the semiconductor circuit is disposed in each of the rectangular regions.
    Type: Grant
    Filed: February 13, 2007
    Date of Patent: January 19, 2010
    Assignee: Disco Corporation
    Inventor: Toshiyuki Yoshikawa
  • Patent number: 7648851
    Abstract: A method for fabricating a back-side illuminated image sensor includes providing a semiconductor substrate having a front surface and back surface, providing a plurality of transistors, metal interconnects, and metal pads on front surface of the substrate, bonding a supporting layer to the front surface of the substrate, thinning-down the semiconductor substrate from the back surface, clearing-out a region of the semiconductor substrate from the back surface that covers a fine alignment mark by performing registration from the back surface and using a global alignment mark as a reference, and processing the back surface of the substrate by performing registration from the back surface and using the fine alignment mark as a reference.
    Type: Grant
    Filed: March 6, 2006
    Date of Patent: January 19, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Chu Fu, Gwo-Yuh Shiau, Liang-Lung Yao, Yuan-Chih Hsieh, Feng-Jia Shiu
  • Patent number: 7648852
    Abstract: The present invention provides an organic thin film transistor (OTFT) being operatable at a low-voltage. The OTFT has a gate dielectric layer of ultra-thin metal oxide or a dual gate dielectric layer of metal oxide and organic dielectric. The metal oxide layer is self-grown to a thickness lower than 10 nm by direct oxidation of a metal gate electrode in O2 plasma process at a temperature lower than 100° C. The gate electrode is deposited with pattern on a plastic or glass substrate. An organic semiconductor layer is deposited on the gate dielectric layer, and source/drain electrodes are formed thereon. In case the dual gate dielectric layer is used, the source/drain electrodes can be disposed under the organic semiconductor layer to realize a bottom contact structure.
    Type: Grant
    Filed: April 5, 2007
    Date of Patent: January 19, 2010
    Assignee: Dong-A University Research Foundation For Industry-Academy Cooperation
    Inventors: Jae Woo Yang, Chung Kun Song, Kang Dae Kim, Gi Seong Ryu, Yong Xian Xu, Myung Won Lee
  • Patent number: 7648853
    Abstract: Dual channel heterostructures comprising strained Si and strained Ge-containing layers are disclosed, along with methods for producing such structures. In preferred embodiments, a strain-relaxed buffer layer is deposited on a carrier substrate, a strained Si layer is deposited over the strain-relaxed buffer layer and a strained Ge-containing layer is deposited over the strained Si layer. The structure can be transferred to a host substrate to produce the strained Si layer over the strained Ge-containing layer. By depositing the Si layer first, the process avoids Ge agglomeration problems.
    Type: Grant
    Filed: July 11, 2006
    Date of Patent: January 19, 2010
    Assignee: ASM America, Inc.
    Inventor: Matthias Bauer
  • Patent number: 7648854
    Abstract: Provided herein are methods of forming a metal oxide layer that include providing an organometallic compound and an oxidizing agent to the substrate to form the metal oxide layer on the substrate. The organometallic compound may have the general formula of M(NR1R2)3R3, wherein M is a metal; R1 and R2 are each independently hydrogen or alkyl; and R3 is selected from the group consisting of alkyl, cycloalkyl, heterocycloalkyl, aryl and heteroaryl.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: January 19, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Ho Lee, Jun-Hyun Cho, Youn-Joung Cho, Seung-Min Ryu, Kyoo-Chul Cho, Jung-Sik Choi
  • Patent number: 7648855
    Abstract: A process for manufacturing a device including a packaged microsystem. The manufactured device is in a form of a plane wafer, the microsystem being buried in the wafer. Therefore, the process is used to make a compound that may be used as a basis for other micro technology processes. Moreover, the process co-integrates electronic compounds when the device is being manufactured. The device is particularly suitable for MEMS, and particularly radiofrequency resonators.
    Type: Grant
    Filed: August 10, 2005
    Date of Patent: January 19, 2010
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Charlotte Gillot, Nicolas Sillon, Emmanuelle Lagoutte
  • Patent number: 7648856
    Abstract: Methods for attaching microfeature dies to external devices are disclosed. The external devices can include other microfeature dies, support members or other suitable devices. A particular method includes attaching the solder to the at least one of the microfeature die in the support member by changing a phase of the solder. The method can further include contacting the solder with the other of the microfeature die and the support member and urging the microfeature die and the support member toward each other to provide a first bond between the die and the support member via the solder. The method can still further include changing a phase of the solder to provide a second bond between the microfeature die and the support member, with the second bond being stronger than the first bond.
    Type: Grant
    Filed: August 28, 2006
    Date of Patent: January 19, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Rick C. Lake
  • Patent number: 7648857
    Abstract: The present invention provides a process for manufacturing an integrated circuit (IC) package and an integrated circuit (IC) package. The process, without limitation, includes providing an integrated circuit chip having a configuration, and forming a layer of overcoat material over the integrated circuit chip based upon the configuration.
    Type: Grant
    Filed: August 11, 2006
    Date of Patent: January 19, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Sean M. Malolepszy, Rex W. Pirkle
  • Patent number: 7648858
    Abstract: Methods and structures provide a shielded multi-layer package for use with multi-chip modules and the like. A substrate (102) (e.g., chip carrier) has an adhesive layer (104), where electronic components (106, 108) are attached. An insulating layer (110) is formed over the plurality of electronic components, and a conductive encapsulant structure (115) is formed over the insulating layer. The adhesive layer is detached from the electronic components, and multi-layer circuitry (140) is formed over, and in electrical communication with, the plurality of electronic components. A shielding via (150) is formed through the multilayer circuitry such that it contacts the conductive encapsulant.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: January 19, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jinbang Tang, Jong-Kai Lin
  • Patent number: 7648859
    Abstract: The microcavity is delineated by a cover, comprising a first layer, in which at least one hole is formed. A second layer hermetically seals the microcavity. A third layer is arranged between the first and the second layer. An additional microcavity, communicating with the hole, is arranged between the first and the third layer. At least one additional hole, adjacent to the additional microcavity, formed in the third layer and offset with respect to the hole, is sealed by the second layer, after sacrificial layers have been removed through the additional hole. The microcomponent includes at least one mechanically stressed layer arranged above the first layer.
    Type: Grant
    Filed: December 14, 2004
    Date of Patent: January 19, 2010
    Assignee: Commissariat A l'Energie Atomique
    Inventor: Philippe Robert
  • Patent number: 7648860
    Abstract: A method of manufacturing a thin-film transistor or like structure provides conductive “tails” below an overhang region formed by a top gate structure. The tails increase in thickness as they extend outward from a point under the overhang to the source and drain contacts. The tails provide a low resistance conduction path between the source and drain regions and the channel, with low parasitic capacitance. The thickness profile of the tails is controlled by the deposition of material over and on the lateral side surfaces of the gate structure.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: January 19, 2010
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Rene Lujan, William S. Wong
  • Patent number: 7648861
    Abstract: The invention provides a method of fabricating a semiconductor device having an inversely staggered TFT capable of high-speed operation, which has few variations of the threshold. In addition, the invention provides a method of fabricating a semiconductor device with high throughput where the cost reduction is achieved with few materials.
    Type: Grant
    Filed: August 1, 2005
    Date of Patent: January 19, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Shinji Maekawa, Tatsuya Honda, Hironobu Shoji, Osamu Nakamura, Yukie Suzuki, Ikuko Kawamata
  • Patent number: 7648862
    Abstract: A semiconductor device having a semiconductor element (a thin film transistor, a thin film diode, a photoelectric conversion element of silicon PIN junction, or a silicon resistor element) which is light-weight, flexible (bendable), and thin as a whole is provided as well as a method of manufacturing the semiconductor device. In the present invention, the element is not formed on a plastic film. Instead, a flat board such as a substrate is used as a form, the space between the substrate (third substrate (17)) and a layer including the element (peeled layer (13)) is filled with coagulant (typically an adhesive) that serves as a second bonding member (16), and the substrate used as a form (third substrate (17)) is peeled off after the adhesive is coagulated to hold the layer including the element (peeled layer (13)) by the coagulated adhesive (second bonding member (16)) alone. In this way, the present invention achieves thinning of the film and reduction in weight.
    Type: Grant
    Filed: May 3, 2007
    Date of Patent: January 19, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junya Maruyama, Toru Takayama, Yuugo Goto
  • Patent number: 7648863
    Abstract: A manufacturing method of a semiconductor device which can decrease the degradation of an element due to plasma in the LDD formation process is provided. The degradation of an element due to plasma is decreased by forming an element having an LDD structure according to a manufacturing method of a semiconductor device using a hard mask. Covering the substrate by an electrically conductive film allover, the density of electric charge accumulated in a gate electrode in the plasma process such as anisotropic etching can be reduced, and the degradation due to plasma process can be reduced.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: January 19, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Akira Isikawa
  • Patent number: 7648864
    Abstract: A method (and resultant structure) of forming a semiconductor structure, includes forming a mixed rare earth oxide on silicon. The mixed rare earth oxide is lattice-matched to silicon.
    Type: Grant
    Filed: August 22, 2008
    Date of Patent: January 19, 2010
    Assignee: International Business Machines Corporation
    Inventors: Nestor Alexander Bojarczuk, Jr., Douglas Andrew Buchanan, Supratik Guha, Vijay Narayanan, Lars-Ake Ragnarsson
  • Patent number: 7648865
    Abstract: A method for manufacturing a pixel structure is provided. First, a gate and a gate insulating layer are sequentially formed on the substrate. A channel layer and a second metal layer are sequentially formed on the gate insulating layer. The second metal layer is patterned to form a source and a drain by using a patterned photoresist layer formed thereon, wherein the source and the drain are disposed on a portion of the channel layer. The gate, the channel, the source and the drain form a thin film transistor. A passivation layer is formed on the patterned photoresist layer, the gate insulating layer and the thin film transistor. Then, the patterned photoresist layer is removed, such that the passivation layer thereon is removed simultaneously to form a patterned passivation layer and the drain is exposed. A pixel electrode is formed on the patterned passivation layer and the drain.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: January 19, 2010
    Assignee: Au Optronics Corporation
    Inventors: Chih-Chun Yang, Ming-Yuan Huang, Han-Tu Lin, Chih-Hung Shih, Ta-Wen Liao, Kuo-Lung Fang, Chia-Chi Tsai
  • Patent number: 7648866
    Abstract: Provided is a method of manufacturing a driving-device for a unit pixel of an organic light emitting display having an improved manufacturing process in which the driving device can be manufactured with a smaller number of processes and in simpler processes.
    Type: Grant
    Filed: December 18, 2007
    Date of Patent: January 19, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-sim Jung, Jung-seok Hahn, Sang-yoon Lee, Jong-man Kim, Jang-yeon Kwon, Kyung-bae Park
  • Patent number: 7648867
    Abstract: A method for fabricating a semiconductor device includes: forming a dummy gate that defines a region in which a gate electrode should be formed on a semiconductor substrate; forming a surface film on the semiconductor substrate by directional sputtering vertical to a surface of the semiconductor substrate, the directional sputtering being one of collimate sputtering, long throw sputtering and ion beam sputtering; removing the surface film formed along a sidewall of the dummy gate; removing the dummy gate; and forming the gate electrode in the region from which the dummy gate on the semiconductor substrate has been removed.
    Type: Grant
    Filed: February 7, 2008
    Date of Patent: January 19, 2010
    Assignee: Eudyna Devices Inc.
    Inventors: Masataka Watanabe, Hiroshi Yano
  • Patent number: 7648868
    Abstract: Metal-oxide semiconductor field effect transistor (MOSFET) devices having metal gate stacks and techniques for improving performance thereof are provided. In one aspect, a metal-oxide semiconductor device is provided comprising a substrate having a buried oxide layer at least a portion of which is configured to serve as a primary background oxygen getterer of the device; and a gate stack separated from the substrate by an interfacial oxide layer. The gate stack comprises a high-K layer over the interfacial oxide layer; and a metal gate layer over the high-K layer.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: January 19, 2010
    Assignee: International Business Machines Corporation
    Inventors: Amlan Majumdar, Renee Tong Mo, Zhibin Ren, Jeffrey Sleight
  • Patent number: 7648869
    Abstract: Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The structure comprises a first doped well formed in a substrate of semiconductor material, a second doped well formed in the substrate proximate to the first doped well, and a deep trench defined in the substrate. The deep trench includes sidewalls positioned between the first and second doped wells. A buried conductive region is defined in the semiconductor material bordering the base and the sidewalls of the deep trench. The buried conductive region intersects the first and second doped wells. The buried conductive region has a higher dopant concentration than the first and second doped wells. The buried conductive region may be formed by solid phase diffusion from a mobile dopant-containing material placed in the deep trench. After the buried conductive region is formed, the mobile dopant-containing material may optionally remain in the deep trench.
    Type: Grant
    Filed: January 12, 2006
    Date of Patent: January 19, 2010
    Assignee: International Business Machines Corporation
    Inventors: Shunhua Thomas Chang, Toshiharu Furukawa, Robert J. Gauthier, Jr., David Vaclav Horak, Charles William Koburger, III, Jack Allan Mandelman, William Robert Tonti
  • Patent number: 7648870
    Abstract: A method of forming a fuse region in a semiconductor damascene process in which a specific layer is formed to prevent corrosion and re-connection of a severed part of the fuse region to prevent malfunction. A first conductive layer is formed over a substrate and an interlayer dielectric layer is deposited over the first conductive layer. A second conductive layer is buried in the interlayer dielectric layer by a dual damascene process to simultaneously form an interconnection and a fuse. The resultant structure is coated with a passivation layer. The fuse is cut to form a severed portion. A selective metal layer is deposited over the severed portion.
    Type: Grant
    Filed: December 26, 2006
    Date of Patent: January 19, 2010
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Se Yeul Bae