Abstract: The present invention is an SOI wafer comprising at least: an SOI layer; a silicon oxide film; and a base wafer, wherein the SOI layer has a plane orientation of (100), and the base wafer has a resistivity of 100 ?·cm or more and a plane orientation different from (100). As a result, there is provided the SOI wafer and the manufacturing method thereof that have no complicated manufacturing step, defects on a bonding interface which are not practically a problem in number and a high interface state density (Dit) for trapping carriers on an interface of a BOX layer and the base wafer.

Abstract: This invention relates to methods and devices for the production of optical microstructures or domains in dielectric substrates based on electrothermal focussing. More specifically, the invention relates to a method of introducing a change of dielectric and/or optical properties in a region of an electrically insulating or electrically semiconducting substrate, and to substrates produced by such method.

Abstract: Organic anti-stiction coatings such as, for example, hydrocarbon and fluorocarbon based self-assembled organosilanes and siloxanes applied either in solvent or via chemical vapor deposition, are selectively etched using a UV-Ozone (UVO) dry etching technique in which the portions of the organic anti-stiction coating to be etched are exposed simultaneously to multiple wavelengths of ultraviolet light that excite and dissociate organic molecules from the anti-stiction coating and generate atomic oxygen from molecular oxygen and ozone so that the organic molecules react with atomic oxygen to form volatile products that are dissipated, resulting in removal of the exposed portions of the anti-stiction coating. A hybrid etching process using heat followed by UVO exposure may be used. A shadow mask (e.g., of glass or quartz), a protective material layer, or other mechanism may be used to selective expose the portions of the anti-stiction coating to be UVO etched.

Abstract: A semiconductor component (such as a semiconductor wafer or semiconductor die) includes a substrate having a front side and a back side. The semiconductor die/wafer also includes a stress balance layer on the back side of the substrate. An active layer deposited on the front side of the substrate creates an unbalanced stress in the semiconductor wafer/die. The stress balance layer balances stress in the semiconductor wafer/die. The stress in the stress balance layer approximately equals the stress in the active layer. Balancing stress in the semiconductor component prevents warpage of the semiconductor wafer/die.

Abstract: An apparatus and method uses a first Faraday cage portion and a second Faraday cage portion to provide a Faraday cage enclosure surrounding at least one circuit device.

Abstract: A semiconductor device having a digital region and an analog region embedded therein has an annular seal ring which surrounds the outer circumference of the digital region and the analog region in a plan view; a guard ring which is provided in the area surrounded by the seal ring, between the digital region and the analog region, so as to isolate the analog region from the digital region, and so as to be electrically connected to the seal ring; and an electrode pad which is electrically connected to the guard ring in the vicinity of the guard ring.

Abstract: A leadless integrated circuit (IC) package comprising an IC chip mounted on a metal leadframe and a plurality of electrical contacts electrically coupled to the IC chip. The leadframe having a spiral inductor etched therein.

Abstract: The present invention provides a stacked chip package structure with leadframe having inner leads with transfer pad, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the plurality of inner leads arranged in rows facing each other and vertically distant from the plurality of inner leads; an offset chip-stacked structure formed with a plurality of chips stacked together, the offest chip-stacked structure being set on the die pad and electrically connected to the plurality of inner leads arranged in rows facing each other; and an encapsulant covering the offset chip-stacked structure and the leadframe, the plurality of outer leads extending out of said encapsulant; the improvement of which being that the inner leads of the leadframe are coated with an insulating layer and a plurality of metal pads are selectively formed on the insulating layer.

Abstract: An integrated circuit (IC) device is provided. The IC device includes a first die having a surface with a first pad formed thereon, a second die having a surface with a second pad formed thereon, and a substrate interposer that couples the first pad to the second pad. The substrate interposer is coupled to the surface of the first die and the surface of the second die.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a leadframe with a tiebar and an outer lead having an outer lead outer pad; forming an inner lead on a peel strip; attaching the leadframe to the peel strip around the inner lead; wire bonding a die to the outer lead and the inner lead; encapsulating the die and portions of the outer lead and the inner lead; removing the peel strip to expose a bottom surface of the inner lead; and removing the leadframe to have the outer lead outer pad of the outer lead coplanar with the bottom surface of the inner lead.

Abstract: A semiconductor including a selectively plated lead frame is disclosed. The lead frame contains a die pad and a plurality of lead fingers, where each lead finger is formed with a bonding pad on the center portion of the lead finger by selective plating. The surface area of the lead finger material is increased so the adhesion to molding material is improved. The edges of the lead finger tips are half etched to further increase the surface area of lead finger material. A method of manufacturing the lead frame is also provided.

Abstract: Apparatus and methods to protect circuitry from moisture ingress, e.g., using a metallic structure as part of a moisture ingress barrier.

Abstract: The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. In another embodiment, the present chip assembling provides high density interconnect wires between bond pads, enabling cost-effective assembling of small chip components. In an aspect, the present process bonds multiple interconnect wires to bond pads with electrical linkages between the bond pads and then subsequently separates the adjacent bond pads.

Abstract: The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. In another embodiment, the present chip assembling provides high density interconnect wires between bond pads, enabling cost-effective assembling of small chip components. In an aspect, the present process coats the component surfaces to facilitate the bonding of the bond pads. In another aspect, the present process coats the bond pads with shelled capsules to facilitate the bonding of the bond pads.

Abstract: A method of manufacture an integrated circuit packaging system includes: providing a base substrate; mounting a first base integrated circuit over the base substrate; mounting a second base integrated circuit over the first base integrated circuit; attaching a stacking interconnect to the base substrate and adjacent to the first base integrated circuit; and forming a base encapsulation, having a recess portion from a corner of the base encapsulation and a step portion adjacent to the recess portion, with the step portion over the second base integrated circuit and the recess portion exposing the stacking interconnect.

Abstract: A semiconductor die includes: a body portion with a plurality of circuit components, a front side including electrical couplings to the plurality of circuit components, a back side having a redistribution layer with a first electrical terminal coupled to the plurality of circuit components by a first through-silicon via, and a second through-silicon via electrically coupled to a third through-silicon via by a trace on the back side redistribution layer. Also, disclosed is a method of coupling circuit components on a die using through-silicon vias and a back side redistribution layer.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a stack board; connecting a device over the stack board; forming a stack encapsulant having a cavity and a pedestal over the device and having a shaped perimeter side from a pedestal surface of the pedestal to the stack board; and attaching a stack adhesive to a base package and the pedestal, the cavity and the shaped perimeter side providing a space for connections to the stack board.

Abstract: Methods, systems, and apparatuses for wafer-level package-on-package structures are provided herein. A wafer-level integrated circuit package that includes at least one die is formed. The wafer-level integrated circuit package includes redistribution interconnects that redistribute terminals of the die over an area that is larger than an active-surface of the die. Electrically conductive paths are formed from the redistribution interconnects at a first surface of the wafer-level integrated circuit package to electrically conductive features at a second surface of the wafer-level integrated circuit package. A second integrated circuit package may be mounted to the second surface of the wafer-level integrated circuit package to form a package-on-package structure. Electrical mounting members of the second package may be coupled to the electrically conductive features at the second surface of the wafer-level integrated circuit package to provide electrical connectivity between the packages.

Abstract: A multi-chip package device can include a plurality of integrated circuit device chips stacked on one another inside a multi-chip package including the device. The device can include an electrically isolated multi-chip support structure that is directly connected to first and second electrically active integrated circuit structures via respective first and second adhesive layers located on opposing sides of the electrically isolated multi-chip support structure.

Abstract: A method of manufacture of an integrated circuit package stacking system including: forming a base frame includes: providing a support panel, and forming a coupling pad, a mounting pad, a base frame trace, a discrete component pad, or a combination thereof on the support panel; fabricating a package substrate; coupling an integrated circuit die to the package substrate; mounting the base frame over the integrated circuit die and the package substrate; and removing the support panel from the base frame.

Abstract: A semiconductor package includes a semiconductor chip having two or more regions that partially overlap so as to define an overlapping region. Through-holes are defined through the two or more partially overlapping regions. One or more first electrodes are disposed on inner surfaces of the semiconductor chip within the through-holes. One or more second electrodes are disposed so as to be insulated from the first electrodes. The one or more second electrodes are at least partially disposed in the overlapping region. Insulation members are disposed in the through-holes.

Abstract: In one aspect, an embodiment of an IC package includes an IC chip electrically connected to a substrate, a heatspreader disposed over the IC chip, wherein the heatspreader does not directly contact the IC chip, and an encapsulant material encapsulating at least a portion of the IC chip and a portion of the heatspreader such that a top portion of the heatspreader is exposed to the surroundings of the IC package. In another embodiment, the heatspreader comprises at least one castellation to improve adhesion to the encapsulation compound. A method of manufacturing such IC package is also disclosed.

Abstract: A chip package structure includes a substrate, a die, and a package body. The substrate includes a single patterned, electrically conductive layer, and a patterned dielectric layer adjacent to an upper surface of the electrically conductive layer. A part of a lower surface of the electrically conductive layer forms first contact pads for electrical connection externally. The patterned dielectric layer exposes a part of the upper surface of the electrically conductive layer to form second contact pads. The electrically conductive layer exposes the lower surface of the patterned dielectric layer on a lower periphery of the substrate. The die is electrically connected to the second contact pads, the patterned dielectric layer and the die being positioned on the same side of the electrically conductive layer. The package body is disposed adjacent to the upper surface of the electrically conductive layer and covers the patterned dielectric layer and the die.

Abstract: A semiconductor device assembly can include a semiconductor chip, a receiving substrate, and a spacer structure interposed between the semiconductor chip and the receiving substrate. The spacer provides an unoccupied space between a pillar and a bond finger for excess conductive material, which can otherwise flow from between the pillar and bond finger and result in a conductive short. The spacer can also provide an offset between the pillar and bond finger.

Abstract: A semiconductor package and a manufacturing method thereof are provided. A carrier having an adhesion layer is provided. A plurality of chips are disposed on the adhesion layer, wherein an active surface of each chip faces the adhesion layer. A molding compound is formed for encapsulating the chips to form a chip-redistribution encapsulant having a first surface and a second surface, wherein the first surface has a chip area and a peripheral area. The carrier and the adhesion layer are removed, so that the chip-redistribution encapsulant exposes the active surface of each chip. A plurality of solder balls are uniformly formed in the chip area and the peripheral area. The second surface of the chip-redistribution encapsulant is grinded to reduce the thickness of the chip-redistribution encapsulant, wherein the solder balls provide the chip-redistribution encapsulant with a uniform support. The chip-redistribution encapsulant is sawn to form a plurality of packages.

Abstract: A method of manufacturing an electronic device package. Coating a first side of a metallic layer with a first insulating layer and coating a second opposite side of the metallic layer with a second insulating layer. Patterning the first insulating layer to expose bonding locations on the first side of the metallic layer, and patterning the second insulating layer such that remaining portions of the second insulating layer on the second opposite side are located directly opposite to the bonding locations on the first side. Selectively removing portions of the metallic layer that are not covered by the remaining portions of the second insulating layer on the second opposite side to form separated coplanar metallic layers. The separated coplanar metallic layers include the bonding locations. Selectively removing remaining portions of the second insulating layer thereby exposing second bonding locations on the second opposite sides of the separated coplanar metallic layers.

Abstract: The present invention relates to a chip packaging method and structure, in which bonding pads provided on the chip are connected by a plurality of metal wires via bonding, each of the metal wires is bending in the middle part to be higher than a predetermined height, and its ends are respectively electrically connected with two of the bonding pads. A molding layer is packaged on the chip and the molding layer is higher than the predetermined height. The molding layer is sliced at the predetermined height. Two upper breakpoints of each metal wire are exposed and a substrate is attached onto the molding layer. A plurality of circuit contacts of the substrate are respectively electrically coupled with the upper breakpoints. Whereby, the invention is capable of reducing the length of the metal wires in order to improve transmission speed, but also to reduce the volume of the packaging structure.

Abstract: The semiconductor device 100 comprises a first semiconductor element 113 provided on a face on one side of a flat plate shaped interconnect component 101, an insulating resin 119 covering a face of a side where the first semiconductor element 113 of the interconnect component 101 is provided and a side face of the first semiconductor element 113, and a second semiconductor element 111 provided on a face on the other side of the interconnect component 101. The interconnect component 101 has a constitution where an interconnect layer 103, a silicon layer 105 and an insulating film 107 are sequentially formed. The interconnect layer 103 has a constitution where the interconnect layer 103 has a flat plate shaped insulating component and a conductive component extending through the insulating component. The first semiconductor element 113 is electrically connected with the second semiconductor element 111 through the conductive component.

Abstract: An integrated circuit package comprises a package substrate (210, 410), an electrically insulating material (220, 420) adjacent to the package substrate, and a mark (230, 420) on the electrically insulating material. The mark is such that a visual contrast between the mark and the electrically insulating material is maximized when the mark and the electrically insulating material are exposed to coaxial illumination. In one embodiment the electrically insulating material over the package substrate has a first surface roughness and a mark on the solder resist material has a second surface roughness that is no more than approximately twenty times greater than the first surface roughness.

Abstract: The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. The present process can fabricate multiple components separately before assembling them into a complete integrated circuit. In an aspect, the ready-for-assembling components are taken directly from processed wafers without any additional assembling processes, and/or having lateral dimensions less than 1 mm.

Abstract: A method of forming a photonic crystal (PhC) structure and a PhC structure formed by such method. The method comprises forming holes in a Si-based host layer; filling the holes with a high-density plasma (HDP) deposited Si-based oxide and such that a surface of the Si-based host layer is directly covered with the Si-based oxide; performing at least a selective wet etching step for etching the Si-based oxide such that a surface of the resulting PhC structure is planarized.

Abstract: A semiconductor device includes a substrate, a memory cell formed on the substrate, and a contact to the substrate. The contact is formed in an area away from the memory cell and functions to raise the potential of the substrate.

Abstract: A method of forming a wire bond in a semiconductor device includes forming a first bump of a first composition proximate to a probe mark on a bond pad. A second bump of the first composition is formed adjacent to the first bump such that the first and second bumps are formed away from the probe mark. A wire of a second composition that is harder than the first composition is attached on top of the first and second bumps to form an interconnection.

Abstract: Disclosed is a printed circuit board, which includes a first circuit layer embedded in one surface an insulating layer and including a bump pad and a wire bonding pad, thus realizing a high-density wire bonding pad. A semiconductor device including the printed circuit board and a method of manufacturing the printed circuit board are also provided.

Abstract: An integrated circuit structure includes a semiconductor substrate, and a polyimide layer over the semiconductor substrate. An under-bump-metallurgy (UBM) has a first portion over the polyimide layer, and a second portion level with the polyimide layer. A first solder bump and a second solder bump are formed over the polyimide layer, with a pitch between the first solder bump and the second solder bump being no more than 150 ?m. A width of the UBM equals one-half of the pitch plus a value greater than 5 ?m.

Abstract: In a POP semiconductor device, a technology is provided which can increase the degree of freedom of semiconductor packages to be combined. A first metal conductive member is placed on a first wiring substrate which is a lower mounting substrate and a second metal conductive member is placed on a second wiring substrate which is an upper mounting substrate. By joining the corresponding portions of the first and second conductive members, the first and second wiring substrates are electrically coupled to each other. An electrode pad which is electrically coupled to the second conductive member and will have an upper semiconductor member 32 mounted thereon is formed on the main surface side of the second wiring substrate, and the electrode pad is also placed at a position planarly overlapping the lower semiconductor chip.

Abstract: A through-silicon via (TSV) structure and process for forming the same are disclosed. A semiconductor substrate has a front surface and a back surface, and a TSV structure is formed to extend through the semiconductor substrate. The TSV structure includes a metal layer, a metal seed layer surrounding the metal layer, a barrier layer surrounding the metal seed layer, and a metal silicide layer formed in a portion sandwiched between the metal layer and the metal seed layer.

Abstract: Various semiconductor chip passivation structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes applying a polymeric passivation layer to a side of a semiconductor chip. The side of the semiconductor chip includes plural conductor pads. Plural openings are formed in the polymeric passivation layer to expose the plural conductor pads. Plural conductor structures are formed on the plural conductor pads.

Abstract: A semiconductor package includes a base substrate, a semiconductor chip mounted on the base substrate and including bonding pads, first and second connection terminals disposed adjacent to the semiconductor chip on the base substrate and electrically connected to the bonding pads, a first ball land disposed on the base substrate and electrically connected to the first connection terminal, a second ball land spaced apart from the connection terminals, the first ball land disposed between the second ball land and at least one of the first and second connection terminals, a first insulating layer covering the first ball land but exposing at least a part of the second ball land, and a first conductive wire extending onto the first insulating layer and connecting the second connection terminal to the second ball land.

Abstract: Mutual inductance from an external output signal system to an external input signal system, in which parallel input/output operation is enabled, is reduced. A semiconductor integrated circuit has a plurality of external connection terminals facing a package substrate, and has an external input terminal and an external output terminal, in which parallel input/output operation is enabled, as part of the external connection terminals. The package substrate has a plurality of wiring layers for electrically connecting between the external connection terminals and module terminals corresponding to each other. A first wiring layer facing the semiconductor integrated circuit has a major wiring for connecting between the external input terminal and a module terminal corresponding to each other, and a second wiring layer in which the module terminals are formed has a major wiring for connecting between an external output terminal and a module terminal corresponding to each other.

Abstract: The interlayer connection of the substrate is formed by a contact-hole filling (4) of a semiconductor layer (11) and metallization (17) of a recess (16) in a reverse-side semiconductor layer (13), wherein the semiconductor layers are separated from each other by a buried insulation layer (12), at whose layer position the contact-hole filling or the metallization ends.

Abstract: A method of manufacture of an integrated circuit system includes: fabricating a substrate having an integrated circuit; applying a low-K dielectric layer over the integrated circuit; forming a via and a trench, in the low-K dielectric layer, over the integrated circuit; forming a structure surface by a chemical-mechanical planarization (CMP) process; and applying a direct implant to the structure surface for forming an implant layer and a metal passivation layer including repairing damage, to the low-K dielectric layer, caused by the CMP process.

Abstract: A structure and methods of fabricating the structure. The structure comprising: a trench in a dielectric layer; an electrically conductive liner, an electrically conductive core conductor and an electrically conductive fill material filling voids between said liner and said core conductor.

Abstract: An interconnection structure includes a lower layer metal wire in a first inter-metal dielectric layer on a substrate; a second inter-metal dielectric layer on the first inter-metal dielectric layer and covering the lower layer metal wire; an upper layer metal wire on the second inter-metal dielectric layer; and a via interconnection structure in the second inter-metal dielectric layer for interconnecting the upper layer metal wire with the lower layer metal wire, wherein the via interconnection structure comprises a tungsten stud on the lower layer metal wire, and an aluminum plug stacked on the tungsten stud.

Abstract: An object of the present is to provide a ULSI micro-interconnect member having a seed layer which, particularly on the inner sidewalls of vias and trenches, is formed with a sufficient coverage and a film thickness uniform with that on surface portion, and which has a low level of impurities. Further objects of the invention are to provide a ULSI micro-interconnect member in which, by utilizing such a seed layer to subsequently effect copper electroplating, micro-interconnects have been formed without generating voids; a process for forming the same; and a semiconductor wafer in which such ULSI micro-interconnects have been formed.

Abstract: A self-aligned interconnect structure is provided that includes a first patterned and cured low-k material located on a surface of a substrate, wherein the first patterned and cured low-k material includes at least one first interconnect pattern (via or trench pattern) therein. A second patterned and cured low-k material having at least one second interconnect pattern that is different from the first interconnect pattern is located atop the first patterned and cured low k material. A portion of the second patterned and cured low-k material partially fills the at least one first interconnect within the first patterned and cured low-k material. A conductive material fills the at least one first interconnect pattern and the at least one second interconnect pattern. A method of forming such a self-aligned interconnect structure is also provided.

Abstract: An interconnect structure within a microelectronic structure and a method for fabricating the interconnect structure within the microelectronic structure use a developable bottom anti-reflective coating layer and at least one imageable inter-level dielectric layer located thereupon over a substrate that includes a base dielectric layer and a first conductor layer located and formed embedded within the base dielectric layer. Incident to use of the developable bottom anti-reflective coating layer and the at least one imageable inter-level dielectric layer, an aperture, such as but not limited to a dual damascene aperture, may be formed through the at least one imageable inter-level dielectric layer and the developable anti-reflective coating layer to expose a capping layer located and formed upon the first conductor layer, absent use of a dry plasma etch method when forming the interconnect structure within the microelectronic structure.

Abstract: An integrated circuit comprising one or more dielectric layers the or each dielectric layer being provided with one or more interconnects wherein the interconnect comprises metallic atoms moving from a first region of the interconnect to a second region of the interconnect when a current flows, characterised in that the interconnect comprises a donor zone in the first region of the interconnect for providing metallic atoms in order to compensate for movement of atoms from the first region and a receptor zone at the second region of the interconnect for receiving metallic atoms in order to compensate for movement of atoms to the second region.

Abstract: A mounting substrate having a structure allowing reduction of the cost and an electronic apparatus formed by surface-mounting a semiconductor device thereon are provided. The mounting substrate is a mounting substrate mounted with a semiconductor device having external terminals alignedly arrayed in the form of a matrix, and includes junctions arrayed on a surface to which the semiconductor device is opposed so that the external terminals are bonded thereto respectively and wires connected to the junctions respectively and extracted out of a region to which the semiconductor device is bonded. The wires connected to inwardly arrayed 4 rows by n columns (n: integer of not less than 5) of the junctions respectively are formed on a first wiring layer. The wires connected to the junctions set in two annular arrays surrounding the outer sides of the 4 rows by n columns of junctions respectively are formed on a second wiring layer different from the first wiring layer.

Abstract: A semiconductor device includes first to third lines. The second line has a width equal to the first line. The second line is arranged with a space equal to the width from the first line, and partially has a gap. The third line is connected to one end of the first line and to a side of one end of the second line.