Abstract: An LED recessed light with reflection board includes a heat sink base, an LED illumination module mounted on the heat sink base, a sleeve, a reflection board and a transparent board. The sleeve having a fixed end, which is mounted on the heat sink base, an open end and a side wall, so that the LED illumination module is located within the sleeve. The reflection board is arranged at the side wall of the sleeve, then, the light from the LED illumination module may reflected by the reflection board. And the transparent board is located on the open end of the sleeve to cover the open end.

Abstract: The present invention is embodied an a dual-chamber passive cooling system for a light-emitting diode (LED) lamp and in a lighting fixture comprising such a system. The system comprises a printed circuit board (PCB) having a hole formed therein and extending through the PCB, and a shell defining a recess configured to receive the PCB. An LED may be positioned on one side of the PCB. The PCB is a thermally conductive PCB, such as a metal-core or graphite-core PCB, and is positioned within the recess so that it divides the recess into a first chamber defining a first volume and a second chamber defining a second volume that is less than the first volume. The shell has a first opening formed therein proximate the first chamber and a second opening formed therein proximate the second chamber, so that air can flow into and out of the chambers, cooling the LED and PCB through convection.

Abstract: A heat dissipating device for a lighting module includes a frame having connecting portions and assembling portions each interconnected between two adjacent connecting portions. Each end of each connecting portion is connected to an adjacent assembling portion. A plurality of air-guiding members is located on the same side of the frame and each mounted on one of the connecting portions. Each air-guiding member includes an air guiding channel having an opening in each end thereof. Each of several heat dissipating fans is mounted to one of the assembling portions and located between two adjacent openings respectively of two adjacent air-guiding members. Each heat dissipating fan includes a first air guiding hole in communication with an environment and at least one second air guiding hole in communication with the two adjacent openings. The air guiding channels and the heat dissipating fans together form a cycling air channel.

Abstract: A vehicle light can include a light emitting diode (LED) serving as a light source and an optical system for controlling a light distribution pattern of the light beams from the LED light source utilizing a light guide (such as a lens body having an inner reflecting surface). The vehicle light can project illumination light with a low beam light distribution pattern. The vehicle light can include an LED light source and a lens body serving as a light guide. The lens body can include a light incident surface, a reflecting surface, and a light exiting surface. The LED light source can have a rearmost end light emitting point from which light beams are emitted to form a bright-dark boundary line.

Abstract: A lamp unit includes at least one light source that emits light in a predetermined direction, and a light guide body including at least one incident surface where light emitted from the light source enters, a first emission surface that emits light entering from the incident surface in a horizontal direction, and a plurality of second emission surfaces that emits light entering the incident surface in a horizontal direction and emits light entering the incident surface to the upper side of the horizontal direction. The second emission surfaces are formed above the first emission surface at different positions in an up-down direction, and are positioned on the back side of the first emission surface so as to be spaced apart from one another in the horizontal direction.

Abstract: A motor vehicle lighting and/or signalling device comprising a housing comprising a rear opening in which a light source can be fitted to the housing and a ventilation hole opening into the rear opening of the housing.

Abstract: Adjustment device of the position of a first part of a lighting and/or signalling device of a motor vehicle in relation to a second part of this device. The adjustment device has a screw in mechanical liaison with the first part and in helical liaison with the second part, the helical liaison comprising: a sliding pivot liaison linking the screw to the second part, the screw being clipped into a bore which has an opening according to a first axis (X) and a conformation completed on the second part which matches the threads of the screw.

Abstract: A vehicular headlamp apparatus includes: a lamp body; a translucent cover having a slanted portion; and a lamp unit. A semiconductor light-emitting element is mounted on a mounting surface so that its irradiation axis intersects with lamp unit's optical axis. Reflector's reflective surface reflects light from the semiconductor light-emitting element toward a vehicle front. One end of the reflective surface is located on a vehicle rear side of the light-emitting element. The other end protrudes toward a vehicle front from a front side end of the mounting portion. The reflective surface has a portion protruding toward the vehicle front from the front side end to face the slanted portion. Within a light distribution pattern, rays of light reflected by first area, second area adjacent to the first area and third area on the reflective surface respectively form a horizontal cut-off line, an oblique cut-off line and a diffusion portion.

Abstract: A high efficiency fiber optic illuminator comprises a light emitting device with wide angular light distribution, such as an LED, and an outwardly tapered fiber optic waveguide rod with a large calculated numerical aperture, preferably equal to or greater than 0.7 and a ratio of the output diameter to the input diameter of between 1.4:1 and 2.2:1. The smaller, input end of the tapered rod is supported close to the light emitting surface so as to collect the maximum amount of energy. The input end is capable of accepting light at very high angles of incidence, and reducing those angles of incidence so that when the light exits the larger, output end the light may be accepted by standard fiber optic devices with typical numerical aperture values ranging between 0.4 and 0.7.

Abstract: An optical film includes a body and a plurality of first linear protrusions. The body has a first surface and a second surface opposite to the first surface. The first linear protrusions are disposed on the first surface, and each first linear protrusion is extended along a first direction and has a first curvy ridge line departing from the first surface, wherein the first curvy ridge lines are concave towards a fixed direction. When the first curvy ridge line is located on a suppositional plan, the suppositional plan is not parallel to the first surface. The above-mentioned optical film is not easy to be worn.

Abstract: A light guide plate includes a transparent substrate and a plurality of micro structures. The transparent substrate has a first surface and a second surface opposite the first surface, and the micro structures are disposed at least on the first surface of the transparent substrate and are separate from each other. Each of the micro structures includes a first coating layer and a second coating layer. The first coating layer is formed on the first surface and includes an adhesive material. The second coating layer is formed on at least a part of the first coating layer and includes a light-diffusing material.

Abstract: The invention relates to an illumination system (10), a backlighting system and a display device. The illumination system comprises a light source (20) configured to emit light via a light guide (30) to a light exit window (40) of the illumination system. The light guide has a front wall (32) arranged opposite a rear wall (34) so as to guide light in a direction substantially parallel to the front wall. A distance (D) between the light guide (30) and the light exit window (40) reduces towards an edge (42) of the light exit window (40). The light guide (30) further comprises a light entrance window (36) for receiving the light from the light source which is arranged away from the edge of the light exit window. The illumination system according to the invention has, inter alia, the effect that its thickness may be reduced at the edge of the light exit window.

Abstract: A light emitting device includes: a substrate having a main surface; a phosphor layer provided on the main surface and containing an LED element that emits primary light and a fluorescent particle that absorbs a part of the primary light and emits secondary light; and a transparent resin layer having a refractive index n and covering the phosphor layer. The transparent resin layer has an outer circumferential surface that forms a boundary between the transparent resin layer and the atmosphere. When a minimum circumference that includes the overall phosphor layer and is concentric with the outer circumferential surface has a radius r in a cut surface where at least a part of the outer circumferential surface takes a shape of an arc having a radius R, a relationship of R>r·n is satisfied. With such configuration, the light extraction efficiency is enhanced.

Abstract: A frame structure of a backlight module includes a body and a mold frame. A side wall surrounds a bearing surface of the body, and the side wall has at least one stopper and at least one positioning hole. A side edge of the mold frame has at least one positioning post. When the mold frame is disposed on the side wall, the side edge of the mold frame leans against the stopper, and the positioning post of the mold frame is embedded in the positioning hole.

Abstract: A burst mode resonant power converter with high conversion efficiency has a rectifier, a power factor correction circuit, a resonant circuit, a controller, and a burst mode triggering unit. The maximum frequency switching end of the controller is connected to a maximum frequency variable circuit. When the load is medium or heavy, the maximum frequency variable circuit increases the maximum switch frequency of the controller. When the load is in the no-load or the light conditions, it reduces the maximum switch frequency thereof. Therefore, the controller reduces the number of times that the resonant circuit switches the bridge switch circuit. The conduction cycle of the 50% pulse signal output to the bridge switch circuit becomes longer. Larger energy can be transmitted at a time to the secondary coil of the transformer. This increases the overall efficiency.

Abstract: A control device for a switching circuit of a resonant converter having a direct current at the output, the switching circuit having at least one half bridge of at least first and second transistors connected between an input voltage and a reference voltage. The half bridge is adapted to generate a periodic square wave voltage to drive the resonant circuit of the resonant converter; The control device has a circuit to proportionally generate a first voltage to a switching period, and a circuit adapted to limit the voltage at the ends of a capacitor between a reference voltage and the first voltage, and a further circuit structured to control the switching off of a first or second transistor at the time instant in which the voltage across the capacitor has reached the first voltage.

Abstract: A switching element driving control circuit includes: a regulator circuit which generates a power supply voltage having an amplitude; a capacitor which smoothes the power supply voltage generated by the regulator circuit to remove a high frequency component; a circuit power supply line to which the smoothed power supply voltage is supplied; an oscillation circuit which generates a periodic signal according to an oscillation of the power supply voltage supplied from the circuit power supply line; a control circuit which generates a control signal for controlling the switching operation of the switching element, based on the periodic signal; and a driver circuit which supplies the switching element with the control signal.

Abstract: A flyback converter controller with forced primary regulation is disclosed. An example flyback converter controller includes a secondary control circuit to be coupled to a switched element coupled to a second winding of a coupled inductor of a flyback converter. The secondary control circuit is to be coupled across an output of the second winding to switch the switched element in response to a difference between an actual output value at the output of the second winding and a desired output value to force a current in a third winding of the coupled inductor that is representative of the difference between the actual output value at the output of the second winding and the desired output value. A primary control circuit is also included and is to be coupled to a primary switch coupled to a first winding of the coupled inductor. The primary control circuit is to be coupled to receive the current forced in the third winding by the secondary control circuit.

Abstract: A power supply control circuit for use in a power supply is disclosed. An example power supply control circuit includes a power switch coupled between first and second terminals. The first terminal is to be coupled to a positive input supply rail of the power supply. The second terminal is to be coupled to an energy transfer element input of the power supply. A sampling circuit is coupled to a third terminal. The sampling circuit coupled to sample a signal across the energy transfer element input of the power supply during an off time of the power switch to provide a sampled output of the power supply. The sampled output of the power supply is disabled from being be resampled by the sampling circuit during an on time of the power switch. A control circuit coupled to the sampling circuit and the power switch, the control circuit coupled to switch the power switch in response to the sampled output of the power supply.

Abstract: In order to convert an input power to one or more DC power levels that are provided to an output load, some aspects of the present disclosure relate to techniques for driving a switching regulator as a function of a pulsed voltage signal. In particular, this pulsed voltage signal is provided substantially at a target frequency, but exhibits frequency jitter that causes the pulsed voltage to vary slightly from the target frequency in time. The frequency jitter has a frequency range that varies as a function of the output load.

Abstract: A power supply controller circuit is disclosed. An example power supply controller circuit includes a control circuit coupled to generate a switching waveform to be used to regulate an output of a power supply. A current input circuit is coupled to receive a current representative of an input of the power supply. The current input circuit is to generate a sense signal in response to the current representative of the input of the power supply. A first comparator is coupled to the current input circuit to receive the sense signal. The first comparator coupled to generate a first signal in response to the sense signal being above a first threshold. An enable/disable logic circuit is coupled to the first comparator. The enable/disable logic circuit is coupled to deactivate the control circuit in response to the first signal.

Abstract: Controlled by switching is which reactor in a reactor group present between a power source and a three-level converter is to be connected to an intermediate point that outputs a midpoint potential. In the switching, the closer to the command value of the midpoint potential the command values of input potentials of the converter are, the greater the duty at which corresponding reactors are connected to the intermediate point is for pulse width modulation. Additionally, a predetermined range to be compared with the command values has a predetermined potential width with respect to an AC waveform centered around the command value of the midpoint potential.

Abstract: A drive unit for electrical loads is provided. The drive unit may include an insulating transformer having a secondary winding for an alternate current to flow therethrough, wherein said secondary winding of said insulating transformer is coupled to electronic switches in a synchronous rectifier arrangement, said electronic switches to be alternatively switched on and off as a function of a trigger signal to produce a rectified output signal from said alternate current flowing through said secondary winding, wherein the unit includes a sense inductance coupled via a set of conductive strips to the secondary winding of said insulating transformer to sense the zero crossings of said alternate current flowing through said secondary winding and generate therefrom said trigger signal for said synchronous rectifier arrangement.

Abstract: A system for using an IGBT module, electrically rated for use in a traction inverter used with a powered system, in an auxiliary inverter used with the powered system which requires a different electrically rated IGBT module than the traction inverter, the system including an IGBT module, including plurality of IGBTs as part of the IGBT module, electrically rated for use with a traction inverter, and a plurality of gate drives each configured to singularly connect to a respective one of the plurality of IGBTs within the IGBT module. All three phases of three-phase electrical power of the auxiliary inverter are associated with the IGBT module.

Abstract: A pair of operator cells each having a series-coupled circuit of first and second transistors is used as a storage unit. To-be-retrieved data and retrieval data are respectively stored in the first and second transistors, and mutually complementary data items are stored in the operator cells of the storage unit. The operator cells supply currents according to the result of an AND operation between the stored data items to corresponding bit lines, and the read data from the storage unit corresponds to the result of an EXOR operation between the retrieval data and the to-be-retrieved data. The currents flowing in the corresponding bit lines are amplified with sense amplifier circuits to drive local match lines. In the individual sub-blocks of an operator cell array, data items having different pattern lengths can be stored. The potentials of the local match lines are selected according to the data pattern lengths, and match retrieval is performed for the data items having the different pattern lengths.

Abstract: A semiconductor device includes a substrate including a cell area and a sense amplifier area, a first bit line connected to a bit line contact of the cell area and a first contact of the sense amplifier area, and a second bit line located on the first bit line to overlap with the first bit line on a plan view and connected to a second contact of the sense amplifier area. The semiconductor device applies a folded bit line structure to a 6F2 structure so as to promote competitiveness of a net die, resulting in reduction of production costs. The semiconductor device implements various test patterns for defect analysis, wherein a conventional 6F2-layout open bit line has difficulty in using the test patterns, resulting in an increased production yield. The semiconductor device reduces noise of a sense amplifier, and performs mat-basis repairing, resulting in an increased production yield.

Abstract: A device includes first to N-th (N is an integer of 2 or more) semiconductor chips stacked. These semiconductor chips have substantially the same configuration, and each includes an identification flag memory circuit including first to N-th memory units and a plurality of through electrodes connected to the identification flag memory circuit. Each of the through electrodes is connected to or masked with respect to the corresponding one of the through electrodes of the underlying semiconductor chip, such that an identification flag is stored in n-th (n indicates 1, 2, . . . , and N) memory units of the n-th semiconductor chips sequentially in the stacking order in response to a clock signal input in common to the first to N-th semiconductor chips, and the storage of the identification flag in the N-th memory unit of the N-th semiconductor chip can be detected from the lower side of the first semiconductor chip.

Abstract: A data storage system includes a plurality of memory devices for storing data. The plurality of memory devices is classified into a plurality of groups of memory devices. A control circuit is adapted to provide concurrent memory access operations to the plurality of memory devices. Each of a plurality of data channels is configured to provide a data path between the control circuit and one of the groups of memory devices. A plurality of switches is configured to connect and disconnect one of the memory devices in a select one of the groups of memory devices to one of the plurality of data channels and concurrently connect and disconnect another of the memory devices in the select group of memory devices to a different one of the plurality of data channels.

Abstract: The non-volatile memory device may include a substrate, a plurality of first signal lines on the substrate in a vertical direction, a plurality of memory cells having ends connected to the plurality of first signal lines, a plurality of second signal lines perpendicular to the plurality of first signal lines on the substrate and each connected to other ends of the plurality of memory cells, and a plurality of selection elements on the substrate and connected to at least two of the plurality of first signal lines.

Abstract: One embodiment of the present invention relates to a method by which the imprint of a ferroelectric random access memory (FRAM) array is reduced. The method begins when an event that will cause imprint to the memory array is anticipated by an external agent to the device comprising the chip. The external agent sends a command to the control circuitry that the data states are to be written to a particular data state. Upon receiving a signal the control circuitry writes all of the ferroelectric memory cells in the FRAM array to a preferred memory data state. The memory data states are held in the preferred data state for the entire duration of the event to minimize imprint of the FRAM memory cells. When the event ends the external agent sends a command to the control circuitry to resume normal memory operation. Other methods and circuits are also disclosed.

Abstract: A method and system for forming reversible resistivity-switching elements is described herein. Forming refers to reducing the resistance of the reversible resistivity-switching element, and is generally understood to refer to reducing the resistance for the first time. Prior to forming the reversible resistivity-switching element it may be in a high-resistance state. A first voltage is applied to “partially form” the reversible resistivity-switching element. The first voltage has a first polarity. Partially forming the reversible resistivity-switching element lowers the resistance of the reversible resistivity-switching element. A second voltage that has the opposite polarity as the first is then applied to the reversible resistivity-switching element. Application of the second voltage may further lower the resistance of the reversible resistivity-switching element. Therefore, the second voltage could be considered as completing the forming of the reversible resistivity-switching element.

Abstract: A six-transistor SRAM cell with dual word line and dual bit line is provided. Each word line is used to separately control an access transistor of the SRAM cell. A six-transistor SRAM cell with dual word line and a single bit line is also provided. The dual word line SRAM cells reduce word line and bit line switching power, and thus reduces the overall power consumption.

Abstract: A SRAM cell having two cross-coupled inverters formed by CMOS technology and first and second chalcogenic elements integrated with the SRAM cell to add nonvolatile properties to the storage cell. The PCM resistors are programmed to the SET state and the RESET state, and upon power-up the SRAM cell takes on the data contained in the PCM cells.

Abstract: Self-reference reading a magnetic tunnel junction data cell methods are disclosed. An illustrative method includes applying a read voltage across a magnetic tunnel junction data cell and forming a read current. The magnetic tunnel junction data cell has a first resistance state. The read voltage is sufficient to switch the magnetic tunnel junction data cell resistance. The method includes detecting the read current and determining if the read current remains constant during the applying step. If the read current remains constant during the applying step, then the first resistance state of the magnetic tunnel junction data cell is the resistance state that the read voltage was sufficient to switch the magnetic tunnel junction data cell to.

Abstract: There is provided a semiconductor device that enables high-speed data read and reduces the area of a drive circuit for activating a word line. By signal transmission through a common word line having a low resistance and coupled at a plurality of points to a word line, it is possible to read data at high speed. Further, since the common word line is provided common to a plurality of memory blocks, a word line driver can be provided common to the memory blocks. Further, by disposing a latch circuit, corresponding to a sub-digit line, for holding the active state of the common word line, it is possible to transmit a row selection signal during data write through the common word line and thereby reduce a metal wiring layer.

Abstract: Methods for measuring the resistance of multiple memory elements are disclosed. The memory elements may be multi-bit memory and through precise measurement of resistance of the multi-bit memory elements, determination of how many and which memory elements fall into specific memory ranges can be accomplished. Furthermore, storage and/or display of this information may allow for the creation of resistance distribution histograms for modeling of one or more memory arrays.

Abstract: By using a resistive film as a shunt, the snapback exhibited when transitioning from the reset state or amorphous phase of a phase change material, may be reduced or avoided. The resistive film may be sufficiently resistive that it heats the phase change material and causes the appropriate phase transitions without requiring a dielectric breakdown of the phase change material.

Abstract: According to an aspect of the present invention, there is provided, a nonvolatile semiconductor storage device including: a substrate; a stacked portion that includes a plurality of conductor layers and a plurality of insulation layers alternately stacked on the substrate, at least one layer of the plurality of conductor layers and the plurality of insulation layers forming a marker layer; a charge accumulation film that is formed on an inner surface of a memory plug hole that is formed in the stacked portion from a top surface to a bottom surface thereof; and a semiconductor pillar that is formed inside the memory plug hole through the charge accumulation film.

Abstract: In an operation method for a memory including a plurality of memory cells, a first reading is performed on the memory cells by applying a reference voltage; the reference voltage is moved if it is checked that the first reading result is not correct; a second reading is performed on the memory cells by applying the moved reference voltage; a first total number of a first logic state in the first reading is compared with a second total number of the first logic state in the second reading if it is checked that the second reading result is not correct; and the moving of the reference voltage is stopped if the first reading result has the same number of the first logic state as the second reading result, and the moved reference voltage is stored as a target reference voltage.

Abstract: A nonvolatile memory device detects a first memory cell to be successfully programmed in a program operation for multiple memory cells connected to a wordline, and then detects a number of program loops required to successfully program the remaining memory cells connected to the wordline. An initial program voltage of subsequent program operations is then adjusted based on the detected number of loops.

Abstract: A method of programming a memory, wherein the memory includes many memory regions having multiple multi-level cells. Each memory region includes a first bit line, a second bit line, a data buffer and a protecting unit. The protecting unit, coupled to the first and second bit lines, and the data buffer, prevents a programming error from occurring. In an embodiment of the programming method, corresponding data are inputted to the data buffers respectively. The data corresponding to an nth phase are programmed into the targeted multi-level cells. Data corresponding to an (n+1)th phase is modified to make the data corresponding to the (n+1)th phase be the same as the data corresponding to the nth phase if the targeted multi-level cells pass a programming verification process according to an nth programming verification voltage. The above steps are repeated until n is equal to a maximum, n being a positive integer.

Abstract: A device comprises an impurity ion disposed in an insulating region, a semiconductor region adjacent to the insulating region, an electrometer arranged to detect charge carriers in the semiconductor region and at least one control gate configured to apply an electric field to the insulating region and semiconductor region. The at least one control gate is operable to cause at least one charge carrier in the semiconducting material region to bind to the impurity ion without the at least one charge carrier leaving the semiconductor material region. The electrometer is operable to detect whether the at least one charge carrier is bound to the impurity ion.

Abstract: A NOR flash memory cell is formed of dual serially connected charge retaining transistors. A drain/source of a first of the dual charge retaining transistors connected to a local bit line and a source/drain of a second of the dual charge retaining transistors connected to a local source line. The drain/sources of the commonly connected dual serially connected charge retaining transistors are connected solely together. The drain/sources and source drains are formed in a diffusion well. In some embodiments, the diffusion well is formed in a deep diffusion well. The dual serially connected charge retaining transistors are N-channel or P-channel charge retaining transistors with the charge retaining layers being either floating gate or SONOS charge trapping layers. Selected charge retaining transistors are programmed by a combination of a band-to-band tunneling and a Fowler-Nordheim tunneling and erased by a Fowler Nordheim tunneling.

Abstract: Source-side sensing techniques described herein determine the data value stored in a memory cell based on the difference in current between the read current from the source terminal of the memory cell and a sink current drawn from the read current. The sink current is drawn in response to the magnitude of a reference current provided by a reference current source such as a reference cell.

Abstract: Source-side sensing techniques described herein determine the data value stored in a memory cell based on the difference in current between the read current from the source terminal of the memory cell and a sink current drawn from the read current. The sink current is drawn in response to the magnitude of a reference current provided by a reference current source such as a reference cell.

Abstract: Provided are nonvolatile memory devices and methods of operating thereof. The nonvolatile memory devices include: dummy cells connected to a dummy bit line; and a dummy bit line bias circuit providing a dummy bit line voltage to the dummy bit line during a program operation, wherein, due to the dummy bit line voltage, at least one of the dummy cells is programmed with a threshold voltage lower than the top programmed state and higher than an erased state during the program operation.

Abstract: Methods are disclosed to compensate for a second-bit effect during programming and reading of charge-trapping memory cells having left and right data regions. When only one of the left and right data regions is to be programmed, a two-step programming procedure is performed on the data region to be programmed. When the memory cell is to be read, threshold voltages for the left and right data regions are sensed with a joint decision regarding left and right data bit values being reached depending upon both sensed threshold voltage values.

Abstract: A semiconductor memory apparatus includes an internal tuning unit configured to tune a generation timing of a data input strobe signal according to a phase difference between an external clock signal and a data strobe clock signal, and a data input sense amplifier configured to transmit data bits to a global line in response to the data input strobe signal.

Abstract: This invention provides a system in package integrated circuit with self-generating reference voltage, in which includes a logic circuit chip and a memory chip. The logic circuit chip generates a plurality of output signals, and the memory chip includes a plurality of input circuit receiving the plurality of output signals from the logic circuit chip. The memory chip further includes a voltage generator generating an input reference voltage based on an output supply voltage. The memory chip is compatible with DDR standard and the plurality of input circuit thereof is compatible with SSTL_2 standard. Wherein, each input circuit comprises a comparator with a first input terminal receiving one of the plurality of output signals and a second input terminal receiving the input reference voltage.

Abstract: A method and system to lower the minimum operating voltage of a memory array during read and/or write operations of the memory array. In one embodiment of the invention, the voltage of the read and/or write word line of the memory array is boosted or increased during read and/or write operations of the memory array. By doing so, the NMOS devices in the memory array are strengthened and the contention between the NMOS and PMOS devices are reduced during read and/or write operations of the memory array. This helps to lower or reduce the required VCCmin of the memory array during read and/or write operations of the memory array.