Abstract: A dual word-line level shifter circuit and associated SRAM. A circuit is disclosed that includes a first transistor gated by a data input at the lower voltage, and a second transistor gated by a restore input at the higher voltage, wherein the first and second transistors are coupled along a series path to a source at the higher voltage; a control node along the series path; an output node coupled to the control node via a first pair of parallel transistors; and a feedback circuit having a second pair of parallel transistors and a feedback transistor, wherein the feedback transistor couples the second pair of parallel transistors to the control node and is gated by the output node.

Abstract: A static random access memory is disclosed.

Abstract: A method is provided for writing data to a memory array operating in synchronization with a clock signal having a transition edge. A data strobe signal having a transition edge corresponding to the transition edge of the clock signal is provided. The transition edge of the clock signal is used to relay the data corresponding to the transition edge of the data strobe signal if the transition edge of the data strobe signal is coming in earlier than the transition edge of the clock signal, wherein the clock signal has a rising edge and a falling edge, the data strobe signal has a rising edge and a falling edge respectively corresponding to the rising and the falling edges of the clock signal, and the transition edge of the clock signal is one of the rising and the falling edges of the clock signal.

Abstract: A semiconductor memory apparatus includes: a first bit line of to a first memory bank; a first middle input/output line configured to be electrically connected to the first bit line; a second bit line of a second memory bank; a second middle input/output line configured to be electrically connected to the second bit line; and a shared local input/output line configured to be electrically connected to the first and second middle input/output lines. A bank selection signal controls both the electrical connection between the shared local input/output line and the first middle input/output line and the electrical connection between the shared local input/output line and the second middle input/output line.

Abstract: A latency circuit comprises a latency control block, an internal read command generator, and a latency signal generation unit. The latency control block generates a plurality of first control clocks by delaying a delay sync signal generated based on an external clock, and generates a second control clock having a margin with respect to a read command decoded based on the delay sync signal. The internal read command generator samples the second control clock using the decoded read command and generates an internal read command based on a sampled second control clock. The latency signal generation unit generates a latency signal based on a shifting operation performed on the internal read command using the plurality of first control clocks.

Abstract: An output enable signal generating circuit for a semiconductor memory apparatus includes an output control unit configured to receive CAS latency information and to generate an output control signal having enable timing according to a DLL on/off mode, and an output enable signal output unit configured to receive the output control signal and to output an output enable signal in response to a read command and a DLL clock signal.

Abstract: A repair fuse device is provided. The repair fuse device remarkably reduces the number of the enable fuse cuttings by making initial states of all repair fuse sets to a repair state, cutting an address fuse corresponding to a defective cell, and cutting an enable fuse corresponding to a defective redundancy cell.

Abstract: A semiconductor device includes plural core chips and an interface chip that controls the plural core chips. Each of the plural core chips includes a layer address generating circuit that generates a second chip address by incrementing a value of a first chip address and a layer address comparing circuit that compares a third chip address supplied from the interface chip and the second chip address, and activates a chip selection signal when the third chip address and the second chip address are matched with each other. When a non-used chip signal is in an inactivated state, the layer address generating circuit supplies the second chip address to another core chip, and when the non-used chip signal is in an activated state, the layer address generating circuit supplies the first chip address to another core chip without a change.

Abstract: A memory system that reduces the memory cycle time of a memory cell by performing an incomplete write operation. The voltage on a storage node of the memory cell does not reach a full supply voltage during the incomplete write operation. The incomplete write operation is subsequently completed by one or more additional accesses, wherein the voltage on the storage node is pulled to a full supply voltage. The incomplete write operation may be completed by: subsequently writing the same data to the memory cell during an idle cycle; subsequently writing data to other memory cells in the same row as the memory cell; subsequently reading data from the row that includes the memory cell; or refreshing the row that includes the memory cell during an idle cycle. One or more idle cycles may be forced to cause the incomplete write operation to be completed in a timely manner.

Abstract: An integrated circuit includes a positive power supply node, a current tracking circuit, and a current mirroring circuit including a plurality of current paths coupled in parallel. The currents of the plurality of current paths mirror a current of the current tracking circuit. The current mirroring circuit is configured to turn off the plurality of current paths one-by-one in response to a reduction in a positive power supply voltage on the positive power supply node. The integrated circuit further includes a charging node receiving a summation current of the plurality of current paths, wherein a voltage on the charging node is configured to increase through a charging of the summation current.

Abstract: A technology that makes it possible to reduce fluctuation in operating voltage for operating the circuits formed in the core region of a semiconductor device is provided. This semiconductor device is so arranged that the core region is divided into multiple functional blocks and power can be supplied and this power supply can be interrupted with respect to each of the divided functional blocks. The core region formed in the semiconductor chip is divided into multiple functional blocks. A power switch row in which multiple power switches are arranged is disposed in the boundaries between the divided functional blocks. These power switches have a function of controlling the supply of reference potential to each of functional blocks and the interruption of this supply. A feature of the invention is that reference pads are disposed directly above the power switch rows. This shortens the wires coupling together the reference pads and the power switches.

Abstract: A semiconductor memory device includes: a first address buffer configured to be used in a test mode and a normal mode and to receive more addresses in the test mode than in the normal mode; and a second address buffer configured to be used in the normal mode and disabled in the test mode.

Abstract: A chip system that has reduced power consumption under specific operational modes includes: a DDR3 chip that includes: a plurality of pads, disposed at the centre of the DDR3 chip; and an array of banks, each bank having a specific logical address, surrounding the pads. The chip system further includes: a clock, coupled to the DDR3 chip, for controlling a rate of data transmission; and a memory controller, coupled to the clock, for coordinating transmitted data with relevant processes, and for selectively reassigning the bank logical addresses according to a specific operational mode.

Abstract: The semiconductor memory device includes plural core chips that are allocated with different chip identification information from each other and an interface chip that controls the plural core chips. A bit number of external unit data that is simultaneously input and output between an external device and the interface chip changes in the interface chip, and the interface chip changes chip selection information for comparison with the chip identification information, according to the bit number of the external unit data. As a result, the page configuration does not need to be changed, when the I/O configuration is changed.

Abstract: The semiconductor memory device includes plural core chips that are allocated with different chip identification information from each other and an interface chip that controls the plural core chips. The interface chip receives address information to specify memory cells and commonly supplies a part of the address information as chip selection information for comparison with the chip identification information to the plural core chips. As a result, since the controller recognizes that an address space is simply enlarged, the same interface as that in the semiconductor memory device according to the related art can be used.

Abstract: A semiconductor memory device includes a row decoding block for decoding an inputted address to thereby generate a logical unit cell block address and a decoded word line address; a tag block for converting the logical unit cell block address into a physical unit cell block address; a decoded address latching block for latching the decoded word line address to thereby output the decoded word line address as a word line activation signal in response to the physical unit cell block; and a cell area for outputting a data, which is stored therein, in response to the word line activation signal.

Abstract: A circuit is configured to be mounted on a memory module connectable to a computer system so as to be electrically coupled to a plurality of memory devices on the memory module. The memory module has a first number of ranks of double-data-rate (DDR) memory devices activated by a first number of chip-select signals. The circuit is configurable to receive bank address signals, a second number of chip-select signals, and row/column address signals from the computer system. The circuit is further configurable to generate phase-locked clock signals in response to clock signals received from the computer system, to selectively isolate one or more loads of the first number of ranks from the computer system, and to translate between a system memory domain and a physical memory domain of the memory module.

Abstract: The present invention provides a kneading device 1 including a hopper 2 having a hopper body 4 that stores raw powder, and a mixer 3 that kneads material to be kneaded, which contains the raw powder, wherein the hopper 2 includes a stirring device 5 that stirs the raw powder in the hopper body, and a temperature-controlled air supply device 6 that supplies temperature-controlled air into the hopper body 4. This kneading device can stably prepare high-quality kneaded dough.

Abstract: An apparatus and method for melting polymer is provided. In at least one embodiment, the apparatus includes a housing, two or more rotatable members at least partially contained within the housing, where each rotatable member having a shaft coupled thereto. The apparatus also includes a motor having a drive shaft directly coupled to the shaft of the rotatable members such that the rotatable members rotate at a speed of the motor drive shaft. The rotatable members are preferably non-intermeshing and counter-rotating.

Abstract: The invention provides a storage device with storage racks and a shaker where the undesired horizontal oscillations of the upper ends of the storage racks are small. In a first embodiment a vertical shaking motion is generated. In a second embodiment, a moving counterweight assembly is provided that counteracts the oscillations.

Abstract: An automated laboratory system, which includes a vessel supply rack for supplying vessels in a vessel supply position, a movable vessel pick-up table for picking up and moving a vessel from the vessel supply position to the vessel filling position, a movable metering table disposed above the vessel pick-up table and configured for picking up and moving at least two metering containers configured to hold chemical substances, the metering containers being able to be positioned above the vessel filling position to fill chemical substances into a vessel, a scale, disposed underneath the vessel filling position for determining a substance quantity filled into a vessel, and a stirrer, disposed above the vessel filling position, for mixing of substances filled into a vessel. Also described is a method for operating such a laboratory system.

Abstract: A cartridge in which bone cement is mixed and from which the cement is discharged. A blade with plural vanes is disposed in the cartridge for mixing the cement. A piston located in one end of the cartridge is actuated to push the mixed cement out of the cartridge. The blade has plural vanes, one for scraping cement off the side of the cartridge, one for scraping cement off the piston and one for scraping cement off the end of the cartridge opposite the end in which the piston is normally located. The blade is collapsible so that when the piston is actuated the blade compresses to allow the cement in the cartridge to be pushed out.

Abstract: A rotary beater is provided which comprises a drive shaft (2) adapted to be coupled to a drive arrangement and defining a longitudinal axis (16) about which the beater is rotatable. The beater has a beater body (6), comprising a wire loop (8) which is coupled to the drive shaft (2) and which extends from the drive shaft in the direction of the longitudinal axis (16) and is led back to the drive shaft (2). The wire loop (8) comprises a first section, (I) a second section (II) comprising two upper segments (8b, 8g) and two lower segments (8c, 8f). Each upper segment (8b, 8g) is connected to the first section (I), and to a respective lower segment (8c, 8f) of the second section (II). The wire loop (8) further comprises a third section (III) for connecting the lower segments (8c, 8f) of the second section (II). Mutually connected upper (8b, 8g) and lower segments (8c, 8f) of the second section (II) define a plane (xa, xb) which is substantially parallel to the longitudinal axis (16).

Abstract: A technique includes receiving seismic data acquired by an array of seismic sensors during a towed marine survey of a subsurface and performing migration velocity analysis to determine a background velocity model of the subsurface based at least in part on particle motion derived from the seismic data.

Abstract: A seismic information processing method and apparatus includes attenuating flexural wave noise information from seismic information. Flexural wave information removal includes receiving the seismic information using an information processing device interface, the seismic information having a plurality of directional components acquired using a multi-axis motion sensor coupled to ice floating on a body of water, the seismic information including desired seismic information and the flexural wave information. A noise model of the flexural wave information may be generated using at least one of the plurality of seismic information directional components using an information processing device. The noise model is improved using an adaptive correction filter, and the improved noise model is applied to at least one directional component of the received seismic information to attenuate the flexural wave information wave in the seismic information.

Abstract: A method for synchronizing recordings of seismic sensor signals between at least two time indexed recording units includes cross-correlating signals recorded by each of a first and a second recording unit from a same reference sensor. The reference sensor is deployed proximate a subsurface volume to be evaluated and generates at least one of an optical and an electrical signal in response to seismic amplitude. Peaks in a power spectrum of the cross correlated signals are determined. The reference signals recorded by each of the first and second recording units are notch filtered using at least one notch frequency selected from the power spectrum. The notch filtered reference signals are cross correlated and a time offset between recordings made by the first recording unit and the second recording unit is determined from the cross-correlated, notch filtered signals.

Abstract: A sweep generator is employed to generate a sweep to be used by a seismic vibrator device for generating a desired target output spectrum, wherein the frequency sweep is designed so as to comply with one or more constraints imposed by the seismic vibrator device and/or imposed by the environment in which the device is to be used. In one embodiment, a sweep generator determines a sweep for achieving a desired target output spectrum by a given seismic vibrator device in compliance with at least a pump flow constraint imposed by the seismic vibrator device. In another embodiment, a sweep generator determines a sweep for achieving a desired target output spectrum by a given seismic vibrator device in compliance with all of multiple operational constraints of the seismic vibrator device, such as both mass displacement and pump flow constraints. Environmental constraints may also be accounted for in certain embodiments.

Abstract: A system includes an electrical medium and a string of sensor assemblies having corresponding outputs connected to the electrical medium, where at least one of the sensor assemblies includes a seismic sensor to measure seismic waves propagated through a subterranean structure, and a pressure sensor. The sensor assembly further includes at least one matching circuit connected to an output of at least one of the seismic sensor and pressure sensor, where the at least one matching circuit is configured to suppress noise. An output signal of the at least one matching circuit is connected to the electrical medium to produce a combined signal that is representative of characteristics of the subterranean structure and in which the noise is suppressed.

Abstract: A computer implemented technique for use in seismic data interpretation and, more particularly, with respect to near-surface geological structures, includes a computer-implemented method, including: jointly interpreting a plurality of complementary data sets describing different attributes of a near-surface geologic structure; and ascertaining a near-surface geomorphology from the joint interpretation. In another aspect, the technique includes a program storage medium encoded with instructions that, when executed, perform such a method. In yet another aspect, the method includes a computing apparatus programmed to perform such a method.

Abstract: A sensor assembly includes a housing structure, a seismic sensor in the housing structure to measure seismic waves propagated through a subterranean structure, and a pressure sensor in the housing structure. A processor in the housing structure is configured to receive a first signal based on an output of the seismic sensor, and a second signal based on an output of the pressure sensor. First and second digital filters are applied to the first and second signals. Application of the first and second digital filters to the first and second signals causes production of a substantially zero output in response to input that includes just noise data detected at the seismic sensor and the pressure sensor.

Abstract: A passive method for exploring a region below the surface of the earth. The method comprises using a single sensor located in turn at a plurality of locations to obtain seismic data obtained by recording ambient seismic interface waves in a frequency range whose lower limit is greater than 0 Hz, and whose upper limit is less than or equal to substantially 1 Hz. The data are processed so as to obtain a measure of the energy in a frequency band within the frequency range. For example, the seismic data may be filtered and may be subjected to amplitude normalization before being transformed into the frequency domain. The energy measure may then be calculated by integrating the spectrum in the frequency domain over a desired frequency range. The resulting calculated energy provides information about the region of the earth being explored.

Abstract: A method and system is described for reducing unwanted noise components/interfering targets detected through an ambiguous beam-steer direction, such as the ambiguous ‘back-lobe’ of a sensor array. A pressure sensor array 52 and a plurality of pressure gradient sub-arrays 541-N are beamformed individually at processing stages 56, 581-N to derive signals indicative of directional responses, one from each group or sub-group. The signals are scaled and weighted (60, 620-N) and processed to define a cardioid beam with nulls pointing in the ambiguous beam-steer direction.

Abstract: A low frequency sound source has a radiating piston (3) of the order of a few metres across backed by a gas spring (13, 15) containing a fixed mass of gas. The gas pressure in the spring is kept at levels for which the natural frequency of the piston (3) loaded by the fluid (41) lies in the seismic band and may be as low as 0.5 Hz. The piston (3) is given an initial displacement and begins to oscillate. Its oscillations are sustained by an actuator (27, 29) whose drive signal is derived from the velocity of the piston (5) via a velocity or displacement sensor. The sound source is caused to perform a frequency sweep by gradually compressing the gas in the gas spring (13, 15) so that the spring becomes stiffer both because of the rising pressure and because of the reducing length of the gas spring spaces (13, 15). This double effect allows large changes in stiffness to be produced and hence allows the source to operate over at least three octaves of frequency.

Abstract: An alarm clock with bedpost pressure sensor including an alarm clock in data communication with a pressure sensor that can be placed under a bedpost. The pressure sensor determines whether or not a bed is occupied based on the weight of the bed and its contents. If the pressure sensor detects that a bed is occupied then an alarm may sound, and if detects that the bed is unoccupied then the alarm is terminated.

Abstract: The invention relates to a device for operating a horological or other time-related function comprising at least two push-buttons (28A, 28B), each having a stem (30A, 30B) and a head (32A, 32B), these push-buttons (28A, 28B) being movable axially between a first or inactive rest position and a second position in which they operate the function, said device being characterized in that the stems (30A, 30B) of the two push-buttons (28A, 28B) extend side by side, parallel to each other. The invention also relates to a timepiece with such an operating device.

Abstract: Incident light can be efficiently converted into near-field light whose spot size is small. A waveguide 10 includes: a metallic member 11 made of a metallic material; and a dielectric member 12 made of a dielectric material. The metallic member 11 includes a first interface 16 and a second interface 18 so as to sandwich the dielectric member 12. The first interface and the second interface are provided so that an inter-interface distance therebetween may decrease from ends 16c and 18c to ends 16d and 18d. The first interface 16 and the second interface 18 have flections P16 and P18, respectively.

Abstract: A recording medium on which data is recorded in units of clusters, a method and apparatus for reproducing data on the recording medium, and a method and apparatus for recording data on the recording medium, wherein each of the clusters includes a plurality of address fields, each address field includes 32-bit address unit number (AUN) address information, and the AUN address information includes a reserved area recorded on 4 bits, layer information, recorded on 3 bits, indicating a layer on which data corresponding to the AUN address information is recorded, and location information, recorded on 25 bits, indicating a location of the data corresponding to the AUN address information. In the recording medium of the present invention, a space in which addresses are recorded is expanded, thereby securing an address area in which addresses of data can be recorded in a data structure.

Abstract: A focus position control apparatus includes a memory unit configured to sequentially store a control signal for controlling a focus position of an optical beam to a desired position in synchronization with a clock signal at an associated one of clock addresses whose one round is completed as an optical disc rotates once, a memory data output unit configured to sequentially read the memory data stored in the memory unit in synchronization with the clock signal, a phase correction unit configured to correct, when the memory data output unit reads the memory data from the memory unit, a phase shift between a clock address for reading and a clock address for storing, and an adding unit configured to add an output signal of the memory data output unit to the control signal.

Abstract: An information storage medium according to the present invention has n information storage layers (where n is an integer and n?3), on which data can be written with a laser beam and which are stacked one upon the other. Each of the n storage layers has a test write zone for determining the recording power of the laser beam. When those n layers are counted from the one that is located most distant from the surface of the medium on which the laser beam is incident, there is a bigger radial location difference between the outer peripheral end of the inner one of the test write zones of ith and (i+1)th information storage layers (where i is an integer that satisfies 2?i?n?1) and the inner peripheral end of the other outer test write zone than between the outer peripheral end of the inner one of the test write zones of jth and (j+1)th information storage layers (where j is an integer that satisfies 1?j?i?1) and the inner peripheral end of the other outer test write zone.

Abstract: A recording unit records data read from a buffer for storing therein data reproduced by a CD drive apparatus capable of adjusting a data reproduction volume which is a volume of data to be reproduced per unit time. A decision unit generates a signal which adjusts the data reproduction volume based on a buffering quantity in the buffer or a volume of dataflow in the recording unit, and outputs the generated signal to the CD drive apparatus.

Abstract: An optical disc drive having an optical pickup head emitting a light beam to an optical storage medium, detecting the light beam reflected from the optical storage medium, and outputting a signal based on the received reflected light, having a jitter measuring unit measuring jitter in signals output from the optical pickup head and having an evaluation unit determining from the measured jitter if the optical storage medium is good or defective. The jitter measuring unit measures jitter in a train of 3T or longer marks or spaces from an optical storage medium to which digital information is recorded as a train of marks or spaces of length kT based on a period T and an integer k of two or more.

Abstract: An optical drive apparatus includes: a phase-difference detection-signal generating unit that generates PEDr based on PEROd and PEFOd obtained by delaying a phase-lead output signal indicating a phase lead amount of DA with respect to DB and X that is changed to high at a timing at which NAND of the DA and the DB is changed from high to low and changed to low at a timing at which OR of the DA and the DB is changed from high to low, and generates PADr based on PAROd and PAFOd obtained by delaying a phase-lag output signal indicating a phase lag amount of the DA with respect to the DB by a predetermined time and the X; and a DPD signal generating unit that generates a phase difference signal indicating a phase difference between the DA and the DB based on the PEDr and the PADr, and generates a DPD signal based on the phase difference signal.

Abstract: A grating element is provided with diffraction members wherein protrusions and recesses are periodically arranged, respectively, on one surface of each of transparent substrates. The diffraction members are laminated in the substantially perpendicular direction to the transparent substrates, the protrusions of the diffraction members are made of a dielectric multilayer film, and the dielectric multilayer film has dielectric films of two or more types laminated in the substantially perpendicular direction on the transparent substrates. The wavelengths of laser beams diffracted at predetermined diffraction efficiencies by the diffraction members are different from one another.

Abstract: Provided are an optical pickup apparatus and an objective lens which can record and/or reproduce information for discs with different recording densities and can realize simplification of the structure of themselves and reducing cost. When the expression (1) is satisfied, step differences of a step structure can be further reduced than those in the case that d1=?1(n?1) holds, and fine grooves corresponding to a steps structure, formed on an optical-surface transfer surface of a mold for molding the objective lens become shallow, to be easily processed. In addition, the moldability is enhanced because the material of the objective lens easily enters the inner portion of the grooves. Further, a fluctuation of a diffraction efficiency caused when wavelength of a light flux changes or temperature changes is reduced so that information can be recorded and/or reduced stably.

Abstract: According to one embodiment, single-sided dual-layer recordable disc 100 may be used. Information recording is performed by forming mark and space portions on data area DA using modulated laser power. Pp denotes the maximum laser power or peak power for forming the mark portion, and Pb denotes the bias power for forming the space portion. Power ratio Pb/Pp is calculated for each of recording layers L0 and L1. Information is recorded on any of the recording layers L0 and L1 based on the result of calculation. Here, the calculated power ratio Pb/Pp changes among the recording layers L0 and L1, thereby optimizing the recording condition for a multi-layer recordable optical disc within relatively short time.

Abstract: Imaging layers, optical disks, and methods of preparation of each, are disclosed.

Abstract: Imaging layers, optical disks, and methods of preparation of each, are disclosed.

Abstract: Disclosed is a sheet for producing a multilayer optical recording medium having a repeating structure wherein a plurality of optical recording layers are laminated. The sheet for a multilayer optical recording medium has a structure having a unit wherein an optical recording layer and an adhesive layer are laminated, or a structure having a unit wherein an optical recording layer, a barrier layer and an adhesive layer are laminated in this order. The maximum height roughness (Rz) of the optical recording layer or the barrier layer is not more than 500 nm. A multilayer optical recording medium is produced by using the sheet for a multilayer optical recording medium. Also disclosed is a sheet for producing, with high precision, a high-quality multilayer optical recording medium having a repeating unit wherein a plurality of optical recording layers containing a multiphoton absorbing material are laminated. A multilayer optical recording medium is also produced by using this sheet.

Abstract: Method and system for serially sending data signals captured from multiple sources through a single unidirectional isolation component. Data signals from respective multiple sources are captured in parallel. Such captured data signals are stored in respective storages. The stored data signals are transferred, in serial, from the storages to a single unidirectional isolation component. Multiple concurrent processes for parallel data signal capture and serial data signal transfer via a single unidirectional isolation component are implemented so that the sampling effect on a first of the multiple processes is minimized.

Abstract: In current hardware forwarding architectures, in which subscriber profiles are distributed across multiple cards in the network, lack of subscriber knowledge leads to loss of bandwidth on fabric links connecting multiple cards in a chassis, loss of device processing cycles, and loss of quality of service knowledge because the traffic is not classified. An example embodiment of the present invention employs a subscriber-aware switch programmed with a subscriber table that maps subscriber traffic to an “anchor” line card with the subscriber's profile. The subscriber table allows for traffic to reach the anchor line card directly, avoiding unnecessary hops and loss of traffic information. As a result, line card, fabric, and other resources are used efficiently, thereby enabling a gateway or other network node to support high traffic rate (e.g., 100 Gbps) network models.