Abstract: The surface morphology of an LED light emitting surface is changed by applying a reactive ion etch (RIE) process to the light emitting surface. High aspect ratio, submicron roughness is formed on the light emitting surface by transferring a thin film metal hard-mask having submicron patterns to the surface prior to applying a reactive ion etch process. The submicron patterns in the metal hard-mask can be formed using a low cost, commercially available nano-patterned template which is transferred to the surface with the mask. After subsequently binding the mask to the surface, the template is removed and the RIE process is applied for time duration sufficient to change the morphology of the surface. The modified surface contains non-symmetric, submicron structures having high aspect ratio which increase the efficiency of the device.

Abstract: A solid state lighting device includes a device-scale stamped heatsink with a base portion and multiple segments or sidewalls projecting outward from the base portion, and dissipates all steady state thermal load of a solid state emitter to an ambient air environment. The heatsink is in thermal communication with one or more solid state emitters, and may define a cup-like cavity containing a reflector. At least a portion of each one sidewall portion or segment extends in a direction non-parallel to the base portion. A dielectric layer and at least one electrical trace may be deposited over a metallic sheet to form a composite sheet, and the composite sheet may be processed by stamping and/or progressive die shaping to form a heatsink with integral circuitry. At least some segments of a heatsink may be arranged to structurally support a lens and/or reflector associated with a solid state lighting device.

Abstract: Provided is a package of a light emitting diode. The package according to an embodiment includes a package of a light emitting diode, the package comprising: a base layer including an entire top surface that is substantially flat; a light emitting diode chip on the base layer; a lead frame electrically connected to the light emitting diode chip; and a reflective coating layer comprising titanium oxide, wherein a top surface of the reflective coating layer is substantially parallel to a top surface of the base layer, and wherein ends of the reflective coating layer and base layer are aligned with each other.

Abstract: A semiconductor device and manufacturing method therefor, provided with the aims of constraining resin burr formation while having good electric connectivity and joining strength, and LED device, provided with the aim of improving adhesion between silicon resin and leads while having good luminescent characteristics. For these purposes, an organic film 110 is formed through self-assembly by functional organic molecules 11 at surface border regions of outer leads 301a of a QFP 10. The functional organic molecules 11 consist of a first functional group A1 bonding with metals, a principal chain B1, and a second functional group C1 inducing hardening in thermosetting resins. The principal chain B1 consists of a glycol chain, or else of a glycol chain and one or more among methylene, fluoromethylene, or siloxane chains. The principal chain B1 also preferably includes one or more among a hydroxyl radical, ketone, thioketone, primary amine, secondary amine, and aromatic compounds.

Abstract: A package structure includes a silicon substrate, a first insulating layer, a reflective layer, a second insulating layer, a first conductive layer, a second conductive layer and a die. The silicon substrate has a first surface and an opposite second surface. The first surface has a reflective opening, and the second surface has two electrode via holes connected to the reflective opening and a recess disposed outside the electrode via holes. The first insulating layer overlays the first surface, the second surface and the recess. The reflective layer is disposed on the reflective opening. The second insulating layer is disposed on the reflective layer. The first conductive layer is disposed on the second insulating layer. The second conductive layer is disposed on the second surface and inside the electrode via holes. The die is fixed inside the reflective opening and electrically connected to the first conductive layer.

Abstract: There is provided a light emitting device including: a package body having first and second circumferential surfaces and a plurality of side surfaces formed therebetween, the package body defined into first and second level areas including the first and second circumferential surfaces, respectively; first and second external terminal blocks each having an electrical contact part; an LED chip disposed between the first and second external terminal blocks in the first level area and having an electrode surface where first and second electrodes are formed; and wires electrically connected to first and second electrodes of the LED chip to the electrical contact parts of the first and second external terminal blocks, respectively.

Abstract: A high efficiency light emitting diode with a composite high reflectivity layer integral to said LED to improve emission efficiency. One embodiment of a light emitting diode (LED) chip comprises an LED and a composite high reflectivity layer integral to the LED to reflect light emitted from the active region. The composite layer comprises a first layer, and alternating plurality of second and third layers on the first layer, and a reflective layer on the topmost of said plurality of second and third layers. The second and third layers have a different index of refraction, and the first layer is at least three times thicker than the thickest of the second and third layers. For composite layers internal to the LED chip, conductive vias can be included through the composite layer to allow an electrical signal to pass through the composite layer to the LED.

Abstract: A wiring board for light-emitting element, comprising a ceramic insulating substrate, and a conductor layer formed on the surface or in the inside of the insulating substrate, and having a mounting region mounting a light-emitting element on one surface of the insulating substrate; wherein the insulating substrate is provided with a heat-conducting pole-like conductor having a thermal conductivity higher than that of said insulating substrate; and the heat-conducting pole-like conductor is extending through the insulating substrate in the direction of thickness thereof from the light-emitting element mounting region of the insulating substrate, and is formed by the co-firing with the insulating substrate.

Abstract: A method and apparatus for coating a plurality of semiconductor devices that is particularly adapted to coating LEDs with a coating material containing conversion particles. One method according to the invention comprises providing a mold with a formation cavity. A plurality of semiconductor devices are mounted within the mold formation cavity and a curable coating material is injected or otherwise introduced into the mold to fill the mold formation cavity and at least partially cover the semiconductor devices. The coating material is cured so that the semiconductor devices are at least partially embedded in the cured coating material. The cured coating material with the embedded semiconductor devices is removed from the formation cavity. The semiconductor devices are separated so that each is at least partially covered by a layer of the cured coating material.

Abstract: The present invention relates to a gallium nitride (GaN) compound semiconductor light emitting element (LED) and a method of manufacturing the same. The present invention provides a vertical GaN LED capable of improving the characteristics of a horizontal LED by means of a metallic protective film layer and a metallic support layer. According to the present invention, a thick metallic protective film layer with a thickness of at least 10 microns is formed on the lateral and/or bottom sides of the vertical GaN LED to protect the element against external impact and to easily separate the chip. Further, a metallic substrate is used instead of a sapphire substrate to efficiently release the generated heat to the outside when the element is operated, so that the LED can be suitable for a high-power application and an element having improved optical output characteristics can also be manufactured. A metallic support layer is formed to protect the element from being distorted or damaged due to impact.

Abstract: Disclosed are a light emitting device and a method of fabricating the same. The light emitting device comprises a substrate. A plurality of light emitting cells are disposed on top of the substrate to be spaced apart from one another. Each of the light emitting cells comprises a first upper semiconductor layer, an active layer, and a second lower semiconductor layer. Reflective metal layers are positioned between the substrate and the light emitting cells. The reflective metal layers are prevented from being exposed to the outside.

Abstract: Disclosed is a light emitting device. The light emitting device comprises a light emitting semiconductor layer comprising a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer, a first passivation layer on the light emitting semiconductor layer, and a second passivation layer on the first passivation layer and has an elastic modulus of 2.0 to 4.0 GPa.

Abstract: A light emitting diode package is provided, which includes a semiconductor substrate having a first surface and a second surface; at least a through-hole passing through the semiconductor substrate; a thermal via formed extending from the second surface toward the first surface of the semiconductor substrate, wherein the thermal via has a first end near the first surface and a second end near the second surface; an insulating layer overlying a sidewall of the through-hole and extending overlying the first surface and the second surface of the semiconductor substrate, wherein the insulating layer further covers at least one of the first end, the second end and a sidewall of the thermal via; a conducting layer overlying the insulating layer in the through-hole and extending to the first surface and the second surface of the semiconductor substrate; and an LED chip disposed overlying the semiconductor substrate.

Abstract: Provided are a light emitting device, a method of manufacturing the light emitting device, a light emitting device package, and a lighting system. The light emitting device comprises a light emitting structure layer including a first conductive type semiconductor layer, a second conductive type semiconductor layer, an active layer between the first conductive type semiconductor layer and the second conductive type layer. At least one lateral surface of the light emitting structure layer has cleavage planes of an A-plane and an M-plane.

Abstract: A light-emitting diode has a metal mesh pattern formed on an active layer without a transparent oxide conductive layer formed in between is disclosed. The mesh pattern is formed by using ion bombardment a metal layer so that myriad pits formed into the exposed portion of the active layer served as light emitting centers.

Abstract: An organic electroluminescence device includes a plurality of organic semiconductor layers including an organic light-emitting layer and layered or disposed between a pair of anode and cathode opposed to each other. The device includes n-type-dopant-containing electron transport layer disposed between the cathode and the organic light-emitting layer. The n-type-dopant-containing electron transport layer includes an organic compound capable of transporting electrons as a first component which mixed with an n-type dopant of an electron donor of metallic atom or ion thereof as a second component. The organic electroluminescence device further includes an n-type-dopant blocking layer having an interface contacting with the n-type-dopant-containing electron transport layer to block the n-type dopant. The n-type-dopant blocking layer includes a heavy atom compound including at least one kind of heavy atoms with an atomic weight of 79 or more.

Abstract: In a semiconductor device of the present invention, a first base region 16 is extended to a part under a gate electrode 7 while having a vertical concentration profile of an impurity that increases from the surface of a semiconductor layer 3 and becomes maximum under an emitter region 5, and the length in the lateral direction from a point where the impurity concentration becomes maximum located under an end of the gate electrode 7 to the boundary with a second base region 15 is not smaller than the length in the vertical direction from the point where the impurity concentration becomes maximum to the boundary with the second base region 15.

Abstract: A structure of power semiconductor device integrated with clamp diodes having separated gate metal pad is disclosed. The separated gate metal pads are wire bonded together on the gate lead frame. This improved structure can prevent the degradation of breakdown voltage due to electric field in termination region blocked by polysilicon or gate metal.

Abstract: Embodiments of detectors made using lattice matched photoabsorbing layers are disclosed. A photodiode apparatus in accordance with one or more embodiments of the present invention comprises an indium phosphide substrate, and a photoabsorbing region comprising at least an indium gallium arsenide antimonide nitride (InGaAsSbN) layer, wherein the InGaAsSbN layer has a thickness of at least 100 nanometers and is nominally lattice-matched to the indium phosphide substrate.

Abstract: A method for introducing species into a strained semiconductor layer comprising: providing a substrate comprising a first region comprising an exposed strained semiconductor layer, loading the substrate in a reaction chamber, then forming a conformal first species containing-layer by vapor phase deposition (VPD) at least on the exposed strained semiconductor layer, and thereafter performing a thermal treatment, thereby diffusing at least part of the first species from the first species-containing layer into the strained semiconductor layer and activating at least part of the diffused first species in the strained semiconductor layer.

Abstract: A method for fabricating an electronic device, comprising wafer bonding a first semiconductor material to a III-nitride semiconductor, at a temperature below 550° C., to form a device quality heterojunction between the first semiconductor material and the III-nitride semiconductor, wherein the first semiconductor material is different from the III-nitride semiconductor and is selected for superior properties, or preferred integration or fabrication characteristics in the injector region as compared to the III-nitride semiconductor.

Abstract: A method for fabricating a structure for use in fabrication of a PiN heterojunction tunnel field effect transistor (TFET) includes forming an alignment trench in a silicon wafer; forming a silicon germanium (SiGe) growth trench in the silicon wafer; growing a p-type SiGe region in the SiGe growth trench; forming a first oxide layer over the alignment trench and the p-type SiGe region; forming a hydrogen implantation region in the silicon wafer, the hydrogen implantation region dividing the silicon wafer into a upper silicon region and a lower silicon region; bonding the first oxide layer to a second oxide layer located on a handle wafer, forming a bonded oxide layer comprising the first oxide layer and the second oxide layer; and separating the lower silicon region from the upper silicon region at the hydrogen implantation region.

Abstract: A non-volatile field-effect device. The non-volatile field-effect device includes a source, a drain, a channel-formation portion and a memristive gate. The channel-formation portion is disposed between and coupled with the source and the drain. The memristive gate is disposed over the channel-formation portion and coupled with the channel-formation portion. The memristive gate includes a plurality of mobile ions and a confinement structure for the plurality of mobile ions. Moreover, the memristive gate is configured to switch the channel-formation portion from a first conductivity state to a second conductivity state in response to migration of the plurality of mobile ions within the confinement structure.

Abstract: A semiconductor device includes an undoped InGaAs layer; an Si-doped GaAs layer formed thereover and equipped with a first recess portion; a two-layered semiconductor layer formed between the undoped InGaAs layer and the Si-doped GaAs layer, equipped with a second recess portion provided in the first recess portion, and composed of an undoped ordered InGaP layer and an undoped GaAs layer formed thereover; a C-doped GaAs layer provided over the undoped InGaAs layer in the second recess portion; and a sidewall insulating film provided between the C-doped GaAs layer and the interface between the undoped GaAs layer and the undoped ordered InGaP layer, but not provided at a portion between the undoped ordered InGaP layer and the C-doped GaAs layer.

Abstract: A HEMT comprising a plurality of active semiconductor layers formed on a substrate. Source electrode, drain electrode, and gate are formed in electrical contact with the plurality of active layers. A spacer layer is formed on at least a portion of a surface of said plurality of active layers and covering the gate. A field plate is formed on the spacer layer and electrically connected to the source electrode, wherein the field plate reduces the peak operating electric field in the HEMT.

Abstract: A process and structure of a back side illumination (BSI) image sensor are disclosed. An n-type doped region is formed in a substrate, and a transfer gate is formed on top of the semiconductor substrate. A p-type doped region is formed in the n-type doped region either using the transfer gate as a mask or is non-self aligned formed.

Abstract: A hydrogen ion-sensitive field effect transistor and a manufacturing method thereof are provided. The hydrogen ion-sensitive field effect transistor includes a semiconductor substrate, an insulating layer, a transistor gate, and a sensing film. A gate area is defined on the semiconductor substrate having a source area and a drain area. The insulating layer is formed within the gate area on the semiconductor substrate. The transistor gate is deposited within the gate area and includes a first gate layer. Further, the first gate layer is an aluminum layer, and a sensing window is defined thereon. The sensing film is an alumina film formed within the sensing window by oxidizing the first gate layer. Thus, the sensing film is formed without any film deposition process, and consequently the manufacturing method is simplified.

Abstract: [Object] To provide a gas sensor having a self-diagnostic function with a simplified structure. [Means of Realizing the Object] A gas sensor (30) includes two field-effect transistors and gate electrodes on gate insulation films (24) of the two field-effect transistors to detect gas using the gate electrodes. The gas sensor (30) includes a first gate electrode (5), a second gate electrode (6), and voltage applying means. The first gate electrode (5) is provided on one of the field-effect transistors. The second gate electrode (6) is provided on another one of the field-effect transistors. The voltage applying means is for, with the first gate electrode (5) and the second gate electrode (6) coupled to one another by wiring, applying thereto one of a direct-current voltage and an alternating-current voltage having a same potential or a constant voltage difference. The first gate electrode (5) and the second gate electrode (6) are made of different metals.

Abstract: Embodiments of the invention provide a method of forming nickel-silicide. The method may include depositing first and second metal layers over at least one of a gate, a source, and a drain region of a field-effect-transistor (FET) through a physical vapor deposition (PVD) process, wherein the first metal layer is deposited using a first nickel target material containing platinum (Pt), and the second metal layer is deposited on top of the first metal layer using a second nickel target material containing no or less platinum than that in the first nickel target material; and annealing the first and second metal layers covering the FET to form a platinum-containing nickel-silicide layer at a top surface of the gate, source, and drain regions.

Abstract: Embodiments of the present invention describe a method of forming nickel sulfide layer on a semiconductor device. A nickel sulfide layer is formed on a substrate by alternatingly exposing the substrate to a nickel-containing precursor and a sulfur-containing precursor.

Abstract: Provided are a wire structure, a method for fabricating a wire, a thin film transistor (TFT) substrate and a method for fabricating a TFT substrate. The wire structure includes a barrier layer formed on a substrate and including a copper layer and a copper solid solution layer.

Abstract: The semiconductor device comprises a first region, a guard ring surrounding the first region, and a second region outside of the guard ring. The first region includes a first electrode made of a first film which has conductivity. A surface of the first electrode in the first region is not covered with the second film. The guard ring includes the first film covering an inner wall of a groove having a recess shape, and a second film as an insulating film covering at least one portion of a surface of the first film in the groove.

Abstract: A semiconductor device includes the following elements. An element isolation portion separates first and second diffusion regions in a semiconductor substrate each other. A first insulating film is formed over the element isolation portion and the first and second diffusion regions. First and second contact plugs are formed over the first and second diffusion regions, respectively. The first and second contact plugs penetrate the first insulating film. A first conductive layer is formed over the first insulating film over the element isolation portion. A second insulating film is formed over the first conductive layer. A third contact plug penetrates the second insulating film, the third contact plug connecting the first contact plug. A second conductive layer is formed over the second insulating film contacting the third contact plug. The first and second conductive layers partly overlap the element isolation portion.

Abstract: The invention includes a semiconductor structure having a gateline lattice surrounding vertical source/drain regions. In some aspects, the source/drain regions can be provided in pairs, with one of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. The source/drain regions extending to the digit line can have the same composition as the source/drain regions extending to the memory storage devices, or can have different compositions from the source/drain regions extending to the memory storage devices. The invention also includes methods of forming semiconductor structures. In exemplary methods, a lattice comprising a first material is provided to surround repeating regions of a second material. At least some of the first material is then replaced with a gateline structure, and at least some of the second material is replaced with vertical source/drain regions.

Abstract: A read transistor for single poly non-volatile memory using a body contacted SOI transistor and a method of manufacturing the same is provided. The non-volatile random access memory is formed in silicon on insulator (SOI). The non-volatile random access memory includes a read field effect transistor (FET) having a body contact formed in the silicon of the SOI. The body contact is in electrical contact with a diffusion region under a gate of the read FET.

Abstract: A device is provided that includes memory, logic and capacitor structures on a semiconductor-on-insulator (SOI) substrate. In one embodiment, the device includes a semiconductor-on-insulator (SOI) substrate having a memory region and a logic region. Trench capacitors are present in the memory region and the logic region, wherein each of the trench capacitors is structurally identical. A first transistor is present in the memory region in electrical communication with a first electrode of at least one trench capacitor that is present in the memory region. A second transistor is present in the logic region that is physically separated from the trench capacitors by insulating material. In some embodiments, the trench capacitors that are present in the logic region include decoupling capacitors and inactive capacitors. A method for forming the aforementioned device is also provided.

Abstract: Semiconductor devices and dynamic random access memory devices including a buried gate electrode are provided, the semiconductor devices include a substrate with a gate trench, a buried gate electrode partially filling the inside of the gate trench, a capping layer pattern in the gate trench and over the buried gate electrode, source/drain regions below an upper surface of the substrate and adjacent to both sides of the buried gate electrode, and a gate insulation layer interposed between the trench and the buried gate electrode. The capping layer pattern includes a high-k material layer that directly contacts an upper surface of the buried gate electrode.

Abstract: A microelectronic flash memory device including a plurality of memory cells including transistors fitted with a matrix of channels connecting a block of common source to a second block on which bit lines rest, the transistors also being formed by a plurality of gates including at least one gate material, including a first selection gate coating the channels, a plurality of control gates coating the channels, a plurality of second selection gates each coating the channels of the same row and the matricial arrangement, at least one or more of the gates based on superposition of layers including at least one first layer of dielectrical material, at least one charge store zone, and at least one second layer of dielectrical material.

Abstract: Provided are nonvolatile memory devices and a method of forming the same. A tunnel insulating pattern is provided on a substrate, and a floating gate is provided on the tunnel insulating pattern. A floating gate cap having a charge trap site is provided on the floating gate, and a gate dielectric pattern is provided on the floating gate cap. A control gate is provided on the gate dielectric pattern.

Abstract: Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions.

Abstract: For providing a cheap semiconductor memory device with improving reliability by level of a cell, in the place of escaping from defects on memory cells electrically, through such as ECC, and further for providing a cell structure enabling scaling-down in the vertical direction with maintaining the reliability, in a semiconductor memory device, upon which high-speeded read-out operation is required, a charge storage region is constructed with particles made from a large number of semiconductor charge storage small regions, each being independent, thereby increasing the reliability by the cell level.

Abstract: A memory string is formed to surround the side surface of a columnar portion and a charge storing layer, and includes plural first conductive layers functioning as gates of memory transistors, and a first protecting layer stacked to protect an upper portion of the plural first conductive layers. The plural first conductive layers constitute a first stairway portion formed stepwise such that their ends are located at different positions. Each first conductive layer constitutes a step of the first stairway portion. A top surface of a first portion of the first stairway portion is covered with the first protecting layer including a first number of layers, and A tope surface of a second portion of the first stairway portion located at a lower level than the first portion is covered with the first protecting layer including a second number of layers fewer than the first number of layers.

Abstract: A 3D nonvolatile memory device includes a plurality of channel structures each comprising a plurality of channel layers and interlayer dielectric layers which are alternately stacked, a plurality of channel contacts coupled to the plurality of channel layers, respectively, and a plurality of selection lines vertically-coupled to the plurality of channel contacts and crossing over the plurality of channel structures.

Abstract: Semiconductor transistor devices and related fabrication methods are provided. An exemplary transistor device includes a layer of semiconductor material having a channel region defined therein and a gate structure overlying the channel region. Recesses are formed in the layer of semiconductor material adjacent to the channel region, such that the recesses extend asymmetrically toward the channel region. The transistor device also includes stress-inducing semiconductor material formed in the recesses. The asymmetric profile of the stress-inducing semiconductor material enhances carrier mobility in a manner that does not exacerbate the short channel effect.

Abstract: A vertical channel transistor includes a plurality of active pillar patterns extending perpendicularly from the top surface of the substrate toward an upper part. A gate insulating layer is deposited on the side wall of the active pillar pattern and serves as an ion diffusion barrier between the pillar patterns and surrounding lower gate electrodes. The resultant pillar pattern structure is encapsulated with a metal. The resultant pillar pattern is surrounded on all sides by a specified height by a sacrificial layer of Spin-On Dielectric (SOD). The metal layer is etched-back to the height of the sacrificial layer, thus forming the lower gate electrodes. A spacer layer of an insulating mater is deposited surrounding the upper part of the pillar patterns and the sacrificial layer is removed exposing a part of the lower gate electrodes. The exposed gate electrode is etched to facilitate semiconductor integration.

Abstract: A trench MOSFET structure with ultra high cell density is disclosed, wherein the source regions and the body regions are located in different regions to save the mesa area between every two adjacent gate trenches in the active area. Furthermore, the inventive trench MOSFET is composed of stripe cells to further increase cell packing density and decrease on resistance Rds between the drain region and the source region.

Abstract: A power MOSFET is described. A trench is in a body layer and an epitaxial layer. An isolation structure is on the substrate at one side of the trench. An oxide layer is on the surface of the trench. A first conductive layer fills the trench and extends to the isolation structure. A dielectric layer is on the first conductive layer and isolation structure and has an opening exposing the first conductive layer. At least one source region is in the body layer at the other side of the trench. A second conductive layer is on the dielectric layer and electrically connected to the source region while electrically isolated from the first conductive layer by the dielectric layer. A third conductive layer is on the dielectric layer and electrically connected to the first conductive layer through the opening of the dielectric layer. The second and third conductive layers are separated.

Abstract: An apparatus is disclosed to increase a breakdown voltage of a semiconductor device. The semiconductor device includes a modified breakdown shallow trench isolation (STI) region to effectively reduce a drain to source resistance when compared to a conventional semiconductor device, thereby increasing the breakdown voltage of the semiconductor device when compared to the conventional semiconductor device. The modified breakdown STI region allows more current to pass from a source region to a drain region of the semiconductor device, thereby further increasing the break down voltage of the semiconductor device from that of the conventional semiconductor device. The semiconductor device may include a modified well region to further reduce the drain to source resistance of the semiconductor device.

Abstract: A disclosed power transistor, suitable for use in a switch mode converter that is operable with a switching frequency exceeding, for example, 5 MHz or more, includes a gate dielectric layer overlying an upper surface of a semiconductor substrate and first and second gate electrodes overlying the gate dielectric layer. The first gate electrode is laterally positioned overlying a first region of the substrate. The first substrate region has a first type of doping, which may be either n-type or p-type. A second gate electrode of the power transistor overlies the gate dielectric and is laterally positioned over a second region of the substrate. The second substrate region has a second doping type that is different than the first type. The transistor further includes a drift region located within the substrate in close proximity to an upper surface of the substrate and laterally positioned between the first and second substrate regions.

Abstract: According to one embodiment, a semiconductor device having an overlapping multi-well implant comprises an isolation structure formed in a semiconductor body, a first well implant formed in the semiconductor body surrounding the isolation structure, and a second well implant overlapping at least a portion of the first well implant. The disclosed semiconductor device, which may be an NMOS or PMOS device, can further comprise a gate formed over the semiconductor body adjacent to the isolation structure, wherein the first well implant extends a first lateral distance under the gate and the second well implant extends a second lateral distance under the gate, and wherein the first and second lateral distances may be different. In one embodiment, the disclosed semiconductor device is fabricated as part of an integrated circuit including a power management circuit or a power amplifier.