Abstract: A semiconductor device, includes a semiconductor device, a wiring layer provided on the semiconductor substrate, a high frequency wiring provided in the wiring layer, and plural dummy metals provided in the wiring layer apart from the high frequency wiring, wherein the wiring layer in plan view includes a high frequency wiring vicinity region and an external region surrounding the high frequency wiring vicinity region, wherein the high frequency wiring vicinity region includes a first region enclosed by an outer edge of the high frequency wiring, and a second region surrounding the first region, wherein the plural dummy metals are disposed dispersedly in the high frequency wiring vicinity region and in the external region respectively, and wherein an average interval between the dummy metals in the high frequency wiring vicinity region is wider than that in the external region.

Abstract: Solutions for forming a silicided deep trench decoupling capacitor are disclosed. In one aspect, a semiconductor structure includes a trench capacitor within a silicon substrate, the trench capacitor including: an outer trench extending into the silicon substrate; a dielectric liner layer in contact with the outer trench; a doped polysilicon layer over the dielectric liner layer, the doped polysilicon layer forming an inner trench within the outer trench; and a silicide layer over a portion of the doped polysilicon layer, the silicide layer separating at least a portion of the contact from at least a portion of the doped polysilicon layer; and a contact having a lower surface abutting the trench capacitor, a portion of the lower surface not abutting the silicide layer.

Abstract: A semiconductor device has a capacitor element in which a capacitance dielectric film is disposed between an upper electrode film (upper electrode film, an upper electrode film) and a lower electrode film, and the lower electrode film has polycrystalline titanium nitride at least to a portion in contact with the capacitance dielectric film.

Abstract: A wiring substrate includes a ceramic substrate including plural ceramic layers, an inner wiring, and an electrode electrically connected to the inner wiring, the electrode exposed on a first surface of the ceramic substrate, and a silicon substrate body having a front surface and a back surface situated on an opposite side of the front surface and including a wiring pattern formed on the front surface and a via filling material having one end electrically connected to the wiring pattern and another end exposed at the back surface. The back surface is bonded to the first surface of the ceramic substrate via a polymer layer. The via filling material penetrates through the polymer layer and is directly bonded to the electrode.

Abstract: A capacitor includes a pillar-type storage node, a supporter disposed entirely within an inner empty crevice of the storage node, a conductive capping layer over the supporter and contacting the storage node so as to seal an entrance to the inner empty crevice, a dielectric layer over the storage node, and a plate node over the dielectric layer.

Abstract: A semiconductor-storage-device manufacturing method of the present invention is a method for manufacturing a semiconductor storage device provided with a ferroelectric capacitor including a lower electrode, a ferroelectric film, and an upper electrode, and the method includes a step of embedding a first metal plug and a second metal plug in an insulating layer; a step of forming a covering layer that covers at least the second metal plug while securing apart that comes into electric contact with the first metal plug; a step of forming a deposit structure by sequentially depositing a material for the lower electrode, a material for the ferroelectric film, and a material for the upper electrode after forming the covering layer; and a step of forming the ferroelectric capacitor by etching and removing other parts except a part of the deposit structure such that the part of the deposit structure remains on the first metal plug.

Abstract: A memristor crossbar array and method of making employ an interstitial insulator. The memristor crossbar array includes a plurality of memristors in an array. The memristors include columns of memristor material disposed between and connecting to a first plurality of wire electrodes and a second plurality of wire electrodes at cross points between the respective wire electrodes. The memristor crossbar array further includes an insulator of a solid material in an interstitial space between the wire electrodes of the first plurality and between the columns of memristor material. The insulator isolates the memristors from one another and has a dielectric constant that is lower than a dielectric constant of the memristor material. The method of making includes forming the plurality of memristors and filling the interstitial space between adjacent memristors with the insulator material.

Abstract: An NPN bipolar junction transistor is disclosed that exhibits a collector-to-emitter breakdown voltage greater than 10 volts and a beta greater than 300. The large value of beta is obtained by fabricating the transistor with an extra N-type layer that reduces recombination of electrons and holes.

Abstract: A method of fabricating a p-type contact on a nonpolar or semipolar (Al,Ga,In)N device, includes the steps of growing a p-type layer on an (Al,Ga,In)N device, wherein the (Al,Ga,In)N device is a nonpolar or semipolar (Al,Ga,In)N device, and the p-type layer is a nonpolar or semipolar (Al,Ga,In)N layer; and cooling the p-type layer down, in the presence of Bis(Cyclopentadienyl)Magnesium (Cp2Mg), to form a magnesium-nitride (MgxNy) layer on the p-type layer. A metal deposition is performed to fabricate a p-type contact on the p-type layer of the (Al,Ga,In)N device, after the cooling step, wherein the p-type contact has a contact resistivity lower than a p-type contact of a polar (Al,Ga,In)N device with substantially similar composition. A hydrogen chloride (HCl) pre-treatment of the p-type layer may be performed, after the cooling step and before the metal deposition step.

Abstract: A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate, having a first surface and an opposite second surface. A through hole is formed on the first surface, extending from the first surface to the second surface. A conductive trace layer is formed on the first surface and in the through hole. A buffer plug is formed in the through hole and a protection layer is formed over the first surface and in the through hole.

Abstract: Roughly described, an integrated circuit device includes a substrate including a via passing therethrough, a strained electrically conductive first material in the via, the first material tending to introduce first stresses into the substrate, and a strained second material in the via, the second material tending to introduce second stresses into the substrate which at least partially cancel the first stresses. In an embodiment, SiGe is grown epitaxially on the inside sidewall of the via in the silicon wafer. SiO2 is then formed on the inside surface of the SiGe, and metal is formed down the center. The stresses introduce by the SiGe tend to counteract the stresses introduced by the metal, thereby reducing or eliminating undesirable stress in the silicon and permitting the placement of transistors in close proximity to the TSV.

Abstract: A method of creating insulating layers on different semiconductor materials includes providing a substrate having disposed thereon a first material and a second material, the second material having a chemical composition different from the first material; non-epitaxially depositing a continuous sacrificial layer of approximately constant thickness onto the first material and the second material, and then converting the sacrificial layer into a layer consisting essentially of SiO2 without oxidizing more than 10 angstroms into the second material. A structure includes a silicon nitride film disposed conformally on a silicon layer and a silicon germanium layer; a SiO2 layer is disposed on the silicon nitride film.

Abstract: Provided are a semiconductor device and a method for manufacturing the same. Since an additional space for forming a shield line is unnecessary, the critical dimension of metal lines is reduced, thereby improving data transfer characteristics, signaling characteristics and noise characteristics of the metal lines. The semiconductor device includes: a plurality of metal lines disposed on the semiconductor device; a plurality of insulation layers disposed on the metal lines; and a plurality of shield lines disposed between the insulation layers.

Abstract: A method for establishing and closing at least one trench of a semiconductor component, in particular a micromechanical or electrical semiconductor component, having the following steps: applying at least one metal layer over the trench to be formed; forming a lattice having lattice openings in the at least one metal layer over the trench to be formed; forming the trench below the metal lattice, and closing the lattice openings over the trench.

Abstract: A semiconductor die package and method of making the package. The package may have four semiconductor dies with one or more internally connected switch nodes, and may form a dual output or phase synchronous buck converter. The package may have control leads at opposite sides of the package from each other. Furthermore, the package may contain high side semiconductor dies that are oriented perpendicular to low side semiconductor dies.

Abstract: A lead frame substrate, including: a metal plate with a first surface and a second surface; a connection post formed on the first surface; wiring formed on the second surface; and a pre-molding resin layer, in which a thickness of the pre-molding resin layer is the same as a height of the connection post.

Abstract: Even when a mold part of an IC module is exposed from an opening provided in a substrate of an inlay, occurrence of malfunction, communication disorders or the like of the IC module due to the influence of an external impact or the like is prevented. By combining a sealing member including an insulating layer and an adhesive layer in a stacked manner to a shape covering a mold part of the IC module, occurrence of malfunction, communication disorders or the like of the IC module is prevented even if there is an influence of an external impact or the like. Meanwhile, by providing a sealing member, concentration of stress on the mold part in a line pressure test is alleviated by limiting the size of the sealing member, and also occurrence of cracks in the mold part can be prevented.

Abstract: A chip package structure for being disposed on a carrier includes a package substrate and a chip. The package substrate includes a laminated layer, a patterned conductive layer, a solder-mask layer, at least one outer pad and a padding pattern. The patterned conductive layer is disposed on a first surface of the laminated layer and has at least one inner pad. The solder resist layer is disposed on the first surface and has at least one opening exposed the inner pad. The outer pad is disposed on the solder resist layer, located within the opening, and is connected with the inner pad. The padding pattern is disposed on the solder resist layer. A height of the padding pattern relative to the first surface is greater than that of the outer pad. The chip is located on a second surface of the laminated layer and electrically connected to the package substrate.

Abstract: A tape wiring substrate may have dispersion wiring patterns. The dispersion wiring patterns may be provided between input/output wiring pattern groups to compensate for the intervals therebetween. Connecting wiring patterns may be configured to connect the dispersion wiring patterns to a first end of the adjacent input/output wiring pattern.

Abstract: A semiconductor package system, and method of manufacturing thereof, includes: a die having a contact pad; a lead finger having a substantially trapezoidal cross-section; a bump clamped on a top and a side of the lead finger, the bump connected to the contact pad; and an encapsulant over the lead finger and the die, the encapsulant with a bottom of the lead finger exposed.

Abstract: A semiconductor package includes a substrate unit, a die electrically connected to first contact pads, and a package body covering a first patterned conductive layer and the die. The substrate unit includes: (1) the first patterned conductive layer; (2) a first dielectric layer exposing a part of the first patterned conductive layer to form the first contact pads; (3) a second patterned conductive layer; (4) a second dielectric layer defining openings extending from the first patterned conductive layer to the second patterned conductive layer, where the second patterned conductive layer includes second contact pads exposed by the second dielectric layer; and (5) conductive posts extending from the first patterned conductive layer to the second contact pads through the openings, each of the conductive posts filling a corresponding one of the openings. At least one of the conductive posts defines a cavity.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead having an upper portion and a bottom portion with a first overhang portion from a top surface of the upper portion and the lead also having serrations along upper vertical sides intersecting the top surface; forming an upper contact plate on the top surface; forming a bottom contact plate on a bottom surface of the bottom portion; attaching an integrated circuit die over the upper portion; and encapsulating the upper portion and the integrated circuit die with an encapsulation leaving the bottom portion exposed.

Abstract: In one embodiment, a semiconductor package is formed to include a leadframe that includes a plurality of die attach areas for attaching a semiconductor die to the leadframe. The leadframe is positioned to overlie another leadframe that forms some of the external terminals or leads of the package.

Abstract: A method includes: forming a photoresist pattern to form each of a semiconductor element mounting section on which a semiconductor element is mounted, semiconductor element electrode connection terminals for connection with electrodes of the semiconductor element, and a first outer frame section on a first surface of a metal plate; forming a photoresist pattern to form each of external connection terminals, a second outer frame section, and grooves in at least a part of the second outer frame section on a second surface of the metal plate; etching a metal plate exposing section, in which the metal plate of the second surface is exposed, to form holes that do not pass through the metal plate exposing section and grooves that run from an inside to an outside of the second outer frame section; coating a pre-mold resin on the holes and the grooves, and heating the pre-mold resin under pressure using a flat-bed press to form a resin layer; and etching the first surface to form the semiconductor element mounting se

Abstract: Microelectronic devices and methods for manufacturing microelectronic devices are described herein. An embodiment of one such method includes attaching a plurality of singulated microelectronic dies to a removable support member with an active side of the individual dies facing toward the support member, depositing a flowable material onto the dies and a portion of the removable support member such that the flowable material covers a back side of the individual dies and is disposed between adjacent dies, and removing the support member from the active sides of the dies.

Abstract: A semiconductor apparatus includes: a wiring board; a lid; and gap filling resin. A semiconductor chip is mounted on the wiring board. The lid includes inlet portions for injecting resin. The semiconductor chip is covered with the lid on the wiring board. The gap filling resin bonds the wiring board and the lid inside the lid.

Abstract: A semiconductor package, a manufacturing method thereof and an encapsulating method thereof are provided. The semiconductor package includes a substrate, a semiconductor chip, a plurality of conductive parts and a sealant. The conductive parts electrically connect an upper surface of the substrate and an active surface of the semiconductor chip. The sealant covers a back surface of the semiconductor chip, wherein the space between the upper surface of the substrate and the active surface of the semiconductor chip is filled with a portion of the sealant. The back surface of the semiconductor is spaced apart from a top surface of the sealant by a first distance, the upper surface of the substrate is spaced apart from the active surface of the semiconductor chip by a second distance, and the ratio of the first distance to the second distance is smaller than or equal to 5.

Abstract: A flip-chip packaging substrate with gradational pad pitches for flip-chip jointing a bumped chip and a flip chip package utilizing the substrate are revealed. A plurality of connecting pads with non-equal pitches are disposed in an array on the substrate for jointing a plurality of equal-pitch bumps of a bumped chip. The pitches of the connecting pads are numbered according to the distance from a central line through a defined central point. When the defined pitch numbers increase by one, a substrate CTE compensation value is subtracted from the distance from the corresponding connecting pads to the center point so that the connecting pads are able to accurately align to the equal-pitch bumps during reflowing processes. Therefore, the expansion distance from the connecting pads of the substrate to the central point is equal to the expansion distance from the bumps of the bumped chip to the central point to avoid alignment shift between the bumps and the corresponding connecting pads due to CTE mismatch.

Abstract: A semiconductor packaging system includes a semiconductor die and a solder pillar on a side of the semiconductor die extending outwardly from a side of the semiconductor die. The solder pillar electrically couples to an electrical contact of a packaging substrate, even when access to the electrical contact is limited by a mask.

Abstract: A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate, having a first surface and an opposing second surface. A spacer is disposed under the second surface of the semiconductor substrate and a cover plate is disposed under the spacer. A recessed portion is formed adjacent to a sidewall of the semiconductor substrate, extending from the first surface of the semiconductor substrate to at least the spacer. Then, a protection layer is disposed over the first surface of the semiconductor substrate and in the recessed portion.

Abstract: A method, apparatus, system, and device provide the ability to form one or more solder bumps on one or more materials. The solder bumps are reflowed. During the reflowing, the solder bumps are monitored in real time. The reflow is controlled in real time, thereby controlling a morphology of each of the solder bumps. Further, the wetting of the solder bumps to a surface of the materials is controlled in real time.

Abstract: A semiconductor device, including: a semiconductor layer having an active region; a first conductive layer formed above the semiconductor layer and having a first width; a second conductive layer connected to the first conductive layer and having a second width smaller than the first width; an interlayer dielectric formed above the semiconductor layer; an electrode pad formed above the interlayer dielectric and covering the active region when viewed from a top side; and a forbidden region provided in the semiconductor layer in a specific range positioned outward from a line extending vertically downward from an edge of at least part of the electrode pad. A connection section at which the first conductive layer and the second conductive layer are connected is not provided in the forbidden region.

Abstract: The invention relates to an integrated circuit module (3) comprising a carrier substrate (4) with terminals for electrically contacting the carrier substrate (4) and a motherboard (2) and comprising at least one semiconductor chip (9) that is electrically contacted to the carrier substrate (4) and integrated into the substrate (4). The carrier substrate (4) comprises at least one cavity (8) that adjoins a mounting surface (10) for the motherboard (2) and holds at least one semiconductor chip (9). The cavity (8) is equipped with connection contacts (11a, 11b) for assigned connections of the semiconductor chip or chips (9), said contacts electrically contacting the semiconductor chip (9) and the carrier substrate (4). The carrier substrate (4) is multi-layered and comprises conductor tracks that extend transversally through several layers and the cavity (8) is hermetically sealed by a thermally conductive cover (12).

Abstract: Embodiments of the present disclosure provide a method comprising forming an electrically conductive structure on a surface of a semiconductor die, attaching the semiconductor die to a substrate, forming a molding compound to encapsulate the semiconductor die, forming an opening in the molding compound, the opening to at least partially expose the electrically conductive structure, and electrically coupling a passive component to the electrically conductive structure through the opening in the molding compound. Other embodiments may be described and/or claimed.

Abstract: A disclosed wiring substrate includes an insulating layer, a recess formed on a surface of the insulating layer, and an alignment mark formed inside of the recess, wherein a face of the alignment mark is roughened, recessed from the surface of the insulating layer, and exposed from the recess.

Abstract: A semiconductor device according to the present invention includes a substrate, an IC chip that is fixed over the substrate, a conductor that is disposed over a surface of the substrate, a solder resist that covers the surface of the substrate and the conductor and includes an opening that exposes the conductor in a section corresponding to a fixed surface of the IC chip, and an adhesive that contacts an exposed part of the conductor, in which the exposed part is made by the opening.

Abstract: A semiconductor device includes a first semiconductor chip having a pad electrode formed on an upper surface thereof; a resin section sealing the first semiconductor chip with the upper surface and a side surface of the first semiconductor chip being covered and a lower surface of die first semiconductor chip being exposed; a columnar electrode communicating between the upper surface and the lower surface of the resin section with the upper surface and the lower surface of the columnar electrode being exposed on the resin section and at least a part of the side surface of the columnar electrode being covered; and a bonding wire connecting the pad electrode and the columnar electrode with a part of the bonding wire being embedded in the columnar electrode as one end of the bonding wire being exposed on the lower surface of the columnar electrode and the remaining part of the bonding wire being covered with the resin section, and a method for manufacturing the same.

Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.

Abstract: An integrated circuit structure includes a semiconductor substrate, a through-silicon via (TSV) extending into the semiconductor substrate, a pad formed over the semiconductor substrate and spaced apart from the TSV, and an interconnect structure formed over the semiconductor substrate and electrically connecting the TSV and the pad. The interconnect structure includes an upper portion formed on the pad and a lower portion adjacent to the pad, and the upper portion extends to electrically connect the TSV.

Abstract: A method for providing and connecting a first contact area to at least one second contact area on a substrate, in particular in the case of a semiconductor component, which includes providing at least one insulation layer on the substrate, forming an opening in the at least one insulation layer over at least one insulation trench of a first contact area, applying at least one metal layer to the insulation layer, forming the first and second contact areas in the at least one metal layer and at least one printed conductor between the two contact areas, and forming the insulation trench.

Abstract: This invention provides a multi-pin semiconductor device as a low-cost flip-chip BGA. In the flip-chip BGA, a plurality of signal bonding electrodes in a peripheral area of the upper surface of a multilayer wiring substrate are separated into inner and outer ones and a plurality of signal through holes coupled to a plurality of signal wirings drawn inside are located between a plurality of rows of signal bonding electrodes and a central region where a plurality of bonding electrodes for core power supply are located so that the chip pad pitch can be decreased and the cost of the BGA can be reduced without an increase in the number of layers in the multilayer wiring substrate.

Abstract: A chip package transmitting slow speed signals via edge connectors and high speed signals by means of through-silicon-vias. The edge connectors are formed in recesses formed in the sidewalls of the package.

Abstract: A semiconductor device, includes a semiconductor substrate, a first wiring layer formed on the semiconductor substrate, the first wiring layer containing a first via having a first aspect ratio and a first wire having a second aspect ratio, the first aspect ratio being equal to or larger than the second aspect ratio, and a second wiring layer overlying the first wiring layer, the second wiring layer containing a second via having a third aspect ratio and a second wire having a fourth aspect ratio, the third aspect ratio being smaller than the fourth aspect ratio.

Abstract: A wiring substrate for a semiconductor chip includes a substrate having a first surface and a second surface opposite to the first surface. The substrate has at least one slot from the first surface to the second surface that exposes chip pads of a semiconductor chip mounted to the first surface. The substrate has first and second regions divided by the slot. A plurality of bonding pads is arranged along both side portions of the slot and the bonding pads are connected to bonding wires that are drawn from the chip pads through the slot. First and second conductive patterns are respectively formed in the first and second regions and respectively connected to the at least one bonding pad. A merging pattern extends from the first region to the second region to electrically connect the first conductive pattern and the second conductive pattern. A merging wire electrically connects the merging pattern and the at least one chip pad.

Abstract: A method for forming a semiconductor device is disclosed. A method for forming a semiconductor device includes forming a first bit line contact over a semiconductor substrate, forming a second bit line contact that is coupled to the first bit line contact and has a larger width than the first bit line contact, and forming a bit line over the second bit line contact. When using the semiconductor device having a buried gate, although the bit line is formed to have a small width and the bit line pattern is misaligned, the method prevents incorrect coupling between a bit line and a bit line contact, so that it basically deteriorates unique characteristics of the semiconductor device.

Abstract: An overlay mark is used in pattern registration on a semiconductor wafer with an oxide layer. Four sets of two trenches each are formed in the oxide layer. Each trench in a set is parallel to the other trench of the same set. The trenches are configured such that each set forms one side of a box shape.

Abstract: Adapters and methods related to aeration applications. An adapter for use in water treatment applications. The adapter includes a generally circular member for conversion of an aeration diffuser holder from a membrane diffuser element holder to a ceramic diffuser element holder. The generally circular member includes a top adapted to receive a retaining ring, a bottom adapted to receive an aeration diffuser holder, a diameter adapted to receive a ceramic diffuser element, and a height adapted to receive a ceramic diffuser element.

Abstract: A method and apparatus for humidifying residential and commercial buildings in which a flue gas generated by a residential or commercial furnace is provided to one side of a porous liquid water transport membrane and habitable space air is provided to an opposite side of the porous liquid water transport membrane in an amount sufficient to provide a habitable space air to flue gas volume flow rate ratio of at least 8.3:1. At least a portion of the water vapor in the flue gas is condensed, providing condensed liquid water which is passed through the porous liquid water transport membrane to the habitable space air side of the porous liquid water transport membrane. On the habitable space air side of the membrane, the condensed liquid water is evaporated into the habitable space air, producing humidified habitable space air which is provided to the rooms of the residential and commercial buildings. Beneficially, no supplemental water source is required for the humidification process.

Abstract: The invention relates to a method for preparing a fuel based on oxide, carbide, and/or oxycarbide comprising uranium and at least one actinide and/or lanthanide component, comprising the following steps: a step for preparing a load solution consisting in a nitric solution comprising said actinide and/or lanthanide in the form of actinide and/or lanthanide nitrates and uranium as a hydroxylated uranyl nitrate complex; a step for passing said solution over a cation exchange resin comprising carboxylic groups, with which the actinide and/or the lanthanide in cationic form and the uranium as uranyl remain bound to the resin; a heat treatment step of said resin so as to obtain said fuel.

Abstract: The present invention relates to a process for manufacturing an agglomerate in the form of beads made up of microcapsules of a phase change material, the process comprising wet-granulation and fluidized-bed drying.