Abstract: An ionic device includes a layer (220) of an ionic conductor containing first and second species (222, 224) of impurities. The first species (222) of impurity in the layer (220) is mobile in the ionic conductor, and a concentration profile of the first species (222) determines a functional characteristic of the device (200). The second species (224) of impurity in the layer (220) interacts with the first species (222) within the layer (220) to create a structure (226) that limits mobility of the first species (222) in the layer (220).

Abstract: A semiconductor device includes a first horizontal molding pattern, a horizontal electrode pattern disposed on the first horizontal molding pattern, and a second horizontal molding pattern disposed on the horizontal electrode pattern. A vertical structure extends through the horizontal patterns. The vertical structure includes a vertical electrode pattern, a data storage pattern interposed between the vertical electrode pattern and the horizontal patterns, a first buffer pattern interposed between the data storage pattern and the first molding pattern, and a second buffer pattern interposed between the data storage pattern and the second molding pattern and spaced apart from the first buffer pattern.

Abstract: A nonvolatile memory element of the present invention comprises a first electrode (103), a second electrode (108); a resistance variable layer (107) which is interposed between the first electrode (103) and the second electrode (107) and is configured to switch a resistance value reversibly in response to an electric signal applied between the electrodes (103) and (108), and the resistance variable layer (107) has at least a multi-layer structure in which a first hafnium-containing layer having a composition expressed as HfOx (0.9?x?1.6), and a second hafnium-containing layer having a composition expressed as HfOy (1.8?y?2.0) are stacked together.

Abstract: A variable resistance memory according to an embodiment includes: a first wiring; a second wiring intersecting with the first wiring; a first electrode provided in an intersection region between the first wiring and the second wiring, the first electrode being connected to the first wiring; a second electrode connected to the second wiring, the second electrode facing to the first electrode; a variable resistance layer provided between the first electrode and the second electrode; and one of a first insulating layer and a first semiconductor layer formed at side portions of the second electrode. The one of the first insulating layer and the first semiconductor layer, and the second electrode form voids at the side portions of the second electrode.

Abstract: A variable resistance non-volatile storage device includes: a first line which includes a barrier metal layer and a main layer, and fills an inside of a line trench formed in a first interlayer insulating layer; a first electrode covering a top surface of the first line and comprising a precious metal; memory cell holes formed in a second interlayer insulating layer; a variable resistance layer formed in the memory cell holes and connected to the first electrode; and second lines covering the variable resistance layer and the memory cell holes, wherein in an area near the memory cell holes, the main layer is covered with the barrier metal layer and the first electrode in an arbitrary widthwise cross section of the first line.

Abstract: A method of making a device comprises forming a layer comprising quantum dots over a substrate including a first electrode, fixing the layer comprising quantum dots formed over the substrate, and exposing at least a portion of, and preferably all, exposed surfaces of the fixed layer comprising quantum dots to small molecules. Also disclosed is a method of making a device, the method comprising forming a layer comprising quantum dots over a substrate including a first electrode, exposing the layer comprising quantum dots to small molecules and light flux. A method of making a film including a layer comprising quantum dots, and a method of preparing a device component including a layer comprising quantum dots are also disclosed. Devices, device components, and films are also disclosed.

Abstract: A nitride semiconductor light-emitting device includes an n-type nitride semiconductor layer, a V pit generation layer, an intermediate layer, a multiple quantum well light-emitting layer, and a p-type nitride semiconductor layer provided in this order. The multiple quantum well light-emitting layer is a layer formed by alternately stacking a barrier layer and a well layer having a bandgap energy smaller than that of the barrier layer. A V pit is partly formed in the multiple quantum well light-emitting layer, and an average position of starting point of the V pit is located in the intermediate layer.

Abstract: An apparatus including a first layer configured to enable a flow of charge carriers from a source electrode to a drain electrode, a second layer configured to control the density of charge carriers in the first layer using an electric field formed between the first and second layers, and a third layer positioned between the first and second layers to shield the first layer from the electric field, wherein the third layer includes a layer of electrically conducting nanoparticles and is configured such that when stress is applied to the third layer, the strength of the electric field experienced by the first layer is varied resulting in a change in the charge carrier density and a corresponding change in the conductance of the first layer.

Abstract: A field-effect transistor includes a semiconductor layer containing carbon nanomaterials; a first electrode and a second electrode formed in contact with the semiconductor layer; a third electrode for controlling current flowing between the first electrode and the second electrode; and an insulating layer formed between the semiconductor layer and the third electrode. The insulating layer contains an aromatic polyamide comprising a substituent containing 1 to 20 carbon atoms.

Abstract: A heterocyclic compound represented by Formula 1 below and an organic light-emitting diode (OLED) including the same: wherein R1 through R12, Ar1, Ar2, A, B, a, and b are the same as defined above. An OLED including an organic layer including the heterocyclic compound has low driving voltage, high luminous efficiency, and a long lifetime.

Abstract: An organic light-emitting display apparatus is disclosed. In one aspect, the apparatus includes a thin film transistor comprising an active layer, a gate electrode, and source and drain electrodes. The apparatus also includes at least two capacitors each comprising a first electrode having a first region doped with ion impurities and a second region not doped with ion impurities, and formed on the same plane as the active layer. Each capacitor also includes a second electrode formed on the same plane as the gate electrode and disposed corresponding to the second region. The apparatus also includes a pixel electrode formed on the same plane as the gate electrode and connected to one of the source and drain electrodes, a light-emitting layer disposed on the pixel electrode, and an opposite electrode disposed on the light-emitting layer.

Abstract: The thiadiazole represented by formula (2) or (4), when used as a light-emitting material in a light-emitting element, allows the light-emitting element to emit near-infrared light: [In formulae (2) and (4), each R independently represents a hydrogen atom, an alkyl group, or a substituted or unsubstituted aryl group. There may be a ring formed by a carbon linkage between two adjacent R's.

Abstract: A light emitting element including an anode, a cathode, a visible light emitting layer which emits visible light and an infrared light emitting layer which emits infrared light installed between the anode and the cathode is provided. Also, it is preferable that the infrared light emitting layer contain a thiadiazole-based compound as a light emitting material.

Abstract: A nanocomposite including: a matrix including a polyimide; and surface-modified inorganic oxide particles disposed in the matrix, wherein a surface of a particle of the surface-modified inorganic oxide particles is modified with an imide functional group.

Abstract: The invention relates to an organic light-emitting device (OLED) comprising at least: a first electrode (102); a second electrode (105); an organic light emissive layer (104) arranged between said first electrode and said second electrode; and an organic charge transport layer (103) arranged between said first electrode and said emissive layer, wherein i) the charge transport layer is patterned or provided with a periodic surface structure on a surface of the charge transport layer facing the emissive layer, and/or ii) an alignment layer (406) which allows for charge transport to the emissive layer is provided between said charge transport layer and said emissive layer, which alignment layer promotes alignment of the optical dipoles of molecules of said light emissive layer towards a common preferred direction of the molecular axes. The use of the patterned or structured charge transport layer and/or the alignment layer provides improved light out coupling from the OLED layer stack, i.e.

Abstract: An organic light emitting device which includes a m-terphenyl compound having a high T1 energy is provided. In addition, a novel m-terphenyl compound is provided.

Abstract: The present invention provides a novel naphthothiophene compound having a high lowest excited triplet level (T1).

Abstract: A novel stable 10,10-dialkylanthrone compound is provided.

Abstract: An organic light-emitting device that achieves highly efficient emission and low-voltage operation is provided. The organic light-emitting device contains a 9H-xanthen-9-one derivative.

Abstract: An organic light emitting diode (OLED) display is disclosed. In one embodiment, the OLED display includes an organic light emitting element formed over a substrate and an encapsulation portion covering the organic light emitting element. Further, the encapsulation portion may include at least one organic layer and at least one inorganic layer, wherein ends of the inorganic layer and the organic layer directly contact the substrate, and wherein the organic layer is thicker than the inorganic layer.

Abstract: This disclosure provides systems, methods and apparatus for fabricating thin film transistor devices. In one aspect, a substrate having a source area, a drain area, and a channel area is provided. The substrate also includes an oxide semiconductor layer, a first dielectric layer overlying the channel area of the substrate, and a first metal layer on the dielectric layer. Hydrogen ions are implanted with a plasma-immersion ion implantation process in the oxide semiconductor layer overlying the source area and the drain area of the substrate. The hydrogen ion implantation forms a doped n-type oxide semiconductor in the oxide semiconductor layer overlying the source area and the drain area of the substrate.

Abstract: A pixel array substrate including a substrate and a plurality of pixel structures is provided. Each pixel structure includes a patterned metal layer, an insulating layer, a patterned semiconductor layer and a data line layer. The patterned metal layer includes a gate line and a common electrode line. The patterned semiconductor layer includes a channel layer and a photosensitive resistance layer. The channel layer is disposed above and overlaps a part of the gate line. The data line layer includes a patterned first data line, a second data line and a third data line. The first and the second data lines are coupled to the channel layer and combine with the channel layer and the gate line to compose an active component. The second and the third data lines are coupled to the photosensitive resistance layer and combine with the photosensitive resistance layer to compose a light detecting component.

Abstract: An element using a semiconductor layer is formed between wiring layers and, at the same time, a gate electrode is formed using a conductive material other than a material for wirings. A first wiring is embedded in a surface of a first wiring layer. A gate electrode is formed over the first wiring. The gate electrode is coupled to the first wiring. The gate electrode is formed by a process different from a process for the first wiring. Therefore, the gate electrode can be formed using a material other than a material for the first wiring. Further, a gate insulating film and a semiconductor layer are formed over the gate electrode.

Abstract: A light-emitting device includes a first cladding layer, a light-emitting layer, a second cladding layer, an epitaxial structure including an indium-containing oxide, and an electrode unit for supplying external electricity, The electrode unit includes a first electrode disposed to be electrically connected to the first cladding layer, and a second electrode disposed above the epitaxial structure to be electrically connected to the second cladding layer through the epitaxial structure such that the external electricity is permitted to be transmitted to the light-emitting layer through the first and second electrodes. A method for manufacturing the light-emitting device is also disclosed.

Abstract: There is such an issue with a TFT using an oxide semiconductor film that oxygen deficit is generated in a surface region of the oxide semiconductor film after performing plasma etching of a source-drain electrode, and the off-current becomes increased. Disclosed is the TFT which includes: a gate electrode on an insulating substrate as a substrate; a gate insulating film on the gate electrode; an oxide semiconductor film on the gate insulating film; and a source/drain electrode on the oxide semiconductor film. It is the characteristic of the TFT that a surface layer containing at least either fluorine or chlorine exists in a part of the oxide semiconductor film where the source/drain electrode is not superimposed.

Abstract: A thin-film transistor with a fluorinated channel and fluorinated source and drain regions and methods of fabrication are provided. The thin-film transistor includes: a substrate; a semiconductor active layer of fluorine-doped metal-oxide formed on the substrate; fluorine-doped source and drain regions disposed adjacent to the semiconductor active layer; a gate electrode disposed over the semiconductor active layer, configured to induce a continuous conduction channel between the source and drain regions; and a gate dielectric material separating the gate electrode and the channel.

Abstract: An object is to provide a display device which operates stably with use of a transistor having stable electric characteristics. In manufacture of a display device using transistors in which an oxide semiconductor layer is used for a channel formation region, a gate electrode is further provided over at least a transistor which is applied to a driver circuit. In manufacture of a transistor in which an oxide semiconductor layer is used for a channel formation region, the oxide semiconductor layer is subjected to heat treatment so as to be dehydrated or dehydrogenated; thus, impurities such as moisture existing in an interface between the oxide semiconductor layer and the gate insulating layer provided below and in contact with the oxide semiconductor layer and an interface between the oxide semiconductor layer and a protective insulating layer provided on and in contact with the oxide semiconductor layer can be reduced.

Abstract: A semiconductor device includes an oxide semiconductor film in which a channel portion is formed and a gate portion arranged to be opposed to the channel portion. A drain portion in which the oxide semiconductor film has been subjected to resistance reduction process and an intermediate area which is provided between the drain portion and the channel portion and has not been subjected to resistance reduction process are formed in the oxide semiconductor film, and the semiconductor device includes a conductive film to block resistance reduction process to the intermediate area at least at a part.

Abstract: A light emitting diode (LED) chip including: a substrate; and a light emitting structure including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer, sequentially deposited on the substrate, in which when a length of the substrate is L and a width of the substrate is W, L/W>10.

Abstract: Methods of fabricating multi-die assemblies including a base semiconductor die bearing a peripherally encapsulated stack of semiconductor dice of lesser lateral dimensions, the dice vertically connected by conductive elements between the dice, resulting assemblies, and semiconductor devices comprising such assemblies.

Abstract: A method of manufacturing a semiconductor device and a semiconductor device package are disclosed. A method of manufacturing a semiconductor device comprises the steps of testing the semiconductor device using at least a first monitoring pad connected to an internal circuit of the semiconductor device via at least a first fuse circuit; after testing the semiconductor device, electrically disconnecting the first monitoring pad from the internal circuit by opening the first fuse circuit; and after testing of the semiconductor device, electrically connecting at least a first auxiliary pad to the first monitoring pad with at least a first connecting terminal, wherein the first auxiliary pad is connected, through at least a first conductive line, to at least a first power pad of the semiconductor device.

Abstract: A display device includes: a base film including plastic; an active layer on the base film, the active layer including a polysilicon layer formed by crystallizing an amorphous silicon layer using a laser; a barrier layer between the active layer and the base film; and a laser absorption layer between the barrier layer and the active layer.

Abstract: A technology for a vertical semiconductor device having a RESURF structure, which is capable of preventing the drop of the withstand voltage when the adhesion of external electric charges occurs is provided. The vertical semiconductor device disclosed in the present specification has a cell region and a non-cell region disposed outside the cell region. This vertical semiconductor device has a diffusion layer disposed in at least part of the non-cell region. When the vertical semiconductor device is viewed in a plane, the diffusion layer has an impurity surface density higher than that satisfying a RESURF condition at an end part close to the cell region, and an impurity surface density lower than that satisfying the RESURF condition at an end part far from the cell region.

Abstract: A thin-film semiconductor device according to the present disclosure includes: a substrate; a gate electrode formed above the substrate; a gate insulating film formed on the gate electrode; a channel layer that is formed of a polycrystalline semiconductor layer on the gate insulating film; an amorphous semiconductor layer formed on the channel layer and having a projecting shape in a surface; and a source electrode and a drain electrode that are formed above the amorphous semiconductor layer, and a first portion included in the amorphous semiconductor layer and located closer to the channel layer has a resistivity lower than a resistivity of a second portion included in the amorphous semiconductor layer and located closer to the source and drain electrodes.

Abstract: A semiconductor device (100) according to the present invention includes: a substrate (1); a gate electrode (11) which is arranged on the substrate; a gate insulating layer (12) which has been formed on the gate electrode; an oxide semiconductor layer (13) which has been formed on the gate insulating layer and which includes a channel region (13c) and source and drain regions (13s, 13d) that interpose the channel region between them; a source electrode (14) which is electrically connected to the source region; a drain electrode (15) which is electrically connected to the drain region; and a metallic compound layer (16) which is arranged between the source and drain electrodes so as to be located on, and contact with, the oxide semiconductor layer. The metallic compound layer is an insulating layer or semiconductor layer which is made of a compound of the same metallic element as at least one of metallic elements that are included in the source and drain electrodes.

Abstract: A thin-film transistor device which is a bottom-gate thin-film transistor device, includes: a gate electrode formed above a substrate; a gate insulating film formed above the gate electrode; a crystalline silicon thin film formed above the gate insulating film and having a channel region; an amorphous silicon thin film formed above the crystalline silicon thin film including the channel region; and a source electrode and a drain electrode formed above the amorphous silicon thin film, in which an optical bandgap of the amorphous silicon thin film and an off-state current of the thin-film transistor device have a positive correlation.

Abstract: An organic thin film transistor including at least a gate electrode, a source electrode, a drain electrode, an insulator layer and an organic semiconductor layer, at least one of the source electrode and the drain electrode including a conductive polyaniline composition containing (a) a substituted or unsubstituted polyaniline composite which is protonated by an organic protonic acid or its salts represented by M(XCR4(CR52COOR6)COOR7)p and (b) compound having a phenolic hydroxyl group.

Abstract: The present invention relates to a thin film transistor substrate and method for fabricating the same which can secure an alignment margin and reduce the number of mask steps. A thin transistor substrate according to the present invention includes a gate line and a data line crossing each other to define a pixel, a gate metal pattern under the data line, a thin film transistor having a gate electrode, a source electrode and a drain electrode in the pixel, and a pixel electrode connected to the drain electrode of the thin film transistor by a connection electrode, wherein the data line has a plurality of first slits to disconnect the gate metal pattern from the gate line.

Abstract: An array substrate for a transflective liquid crystal display device includes: a substrate; a gate line and a data line on the substrate, the gate line and the data line crossing each other to define a pixel region including a transmissive area and a reflective area surrounding the transmissive area; a thin film transistor having a gate insulating layer, the thin film transistor electrically connected to the gate line and the data line; a first passivation layer having a drain contact hole exposing a drain electrode of the thin film transistor and a through hole exposing the substrate in the transmissive area; a pixel electrode on the first passivation layer, the pixel electrode contacting the substrate in the transmissive area through the through hole; and a reflective plate on the pixel electrode, the reflective plate being electrically connected to the drain electrode through the drain contact hole and to the pixel electrode.

Abstract: A thin-film transistor array substrate is disclosed. In one embodiment, the transistor includes a capacitor including a lower electrode disposed on the same layer as an active layer and an upper electrode disposed on the same layer as a gate electrode. The transistor may also include a first insulating layer disposed between the active layer and the gate electrode and between the lower and upper electrodes, the first insulating layer not being disposed on a perimeter of the lower electrode. The transistor may further include a second insulating layer between the first insulating layer and the source and drain electrodes, the second insulating layer not being disposed on perimeters of the upper and lower electrodes.

Abstract: Exemplary embodiments of the invention disclose a method of manufacturing a thin film transistor array panel having reduced overall processing time and providing a uniform crystallization. Exemplary embodiments of the invention also disclose a crystallization method of a thin film transistor, including forming on a substrate a semiconductor layer including a first pixel area, a second pixel area, and a third pixel area. The crystallization method includes crystallizing a portion of the semiconductor layer corresponding to a channel region of a thin film transistor using a micro lens array.

Abstract: A thin-film transistor array substrate and a fabrication method thereof according to an embodiment of the present invention are disclosed to form an interlayer insulating layer, thereby reducing a failure occurred during the process subsequent to a gate electrode. The thin-film transistor disclosed according to the present invention may include a substrate, a gate electrode formed on the substrate, a planarized insulating layer formed at a lateral surface portion of the gate electrode and at an upper portion of the substrate, a gate insulating layer formed on the planarized insulating layer containing an upper portion of the gate electrode, an active layer formed at an upper portion of the planarized insulating layer located at an upper side of the gate electrode, and a source electrode and a drain electrode formed on the active layer and separated from each other based on a channel region.

Abstract: A semiconductor device (100) includes: a first thin film transistor (105) of a first conductivity type formed on a substrate for each pixel; and a plurality of photosensor sections (200). Each photosensor section (200) includes a photodetecting portion including a thin film diode (202), a capacitor (206) for storing a photocurrent occurring in the thin film diode (202), and a second thin film transistor (204) of the first conductivity type, the photodetecting portion being connected to the capacitor (206) via the second thin film transistor (204); the first and second thin film transistors (105, 204) and the thin film diode (202) have semiconductor layers made of the same semiconductor film; and a characteristic of the first thin film transistor (105) and a characteristic of the second thin film transistor (204) are different.

Abstract: A semiconductor device (130) includes: a bonding substrate (100); a thin film element (80) formed on the bonding substrate (100); and a semiconductor element (90) bonded to the bonding substrate (100), the semiconductor element (90) including semiconductor element main body (50) and a plurality of underlying layers (51-54) stacked on a side of the semiconductor element main body (50) facing the bonding substrate (100), and each of the underlying layers (51-54) including an insulating layer and a circuit pattern in the insulating layer, wherein an end of the semiconductor element (90) facing the thin film element (80) is provided in a stepped form so that the closer to the bonding substrate the underlying layers arc, the farther ends of the underlying layers facing the thin film element protrude, the end of the semiconductor element (90) is covered with a resin layer (120), and the thin film element (80) is connected to the semiconductor element main body (50) via a connection line (121a) provided on the resin

Abstract: An organic light-emitting display device includes a plurality of sub-pixels each comprising a light-emitting portion, a thin film transistor (TFT), and a capacitor, each of the sub-pixels emitting a different color, wherein the capacitor of at least one of the plurality of sub-pixels extends into at least one adjacent one of the sub-pixels.

Abstract: An organic light-emitting display device includes a thin film transistor including an active layer, a gate electrode, source/drain electrodes, a first insulating layer between the active layer and the gate electrode, and a second insulating layer over the gate electrode; a pixel electrode on the first insulating layer and the second insulating layer and connected to the source or drain electrode; a first wire on the first insulating layer, of the same material as the gate electrode; a second wire on the second insulating layer to at least partially overlap the first wire and including a lower wiring layer of the same material as the pixel electrode and an upper wiring layer on the lower wiring layer, of the same material as the source/drain electrodes; and third insulating layers between the second insulating layer and the pixel electrode and between the second insulating layer and the second wire.

Abstract: Disclosed are a light emitting device, a method of manufacturing the light emitting device, a light emitting device package and a lighting system. The light emitting device includes a silicon substrate; a nitride buffer layer on the silicon substrate; and a gallium nitride epitaxial layer on the nitride buffer layer, wherein the nitride buffer layer includes a first nitride buffer layer having a first aluminum nitride layer on the silicon substrate and a first gallium nitride layer on the first aluminum nitride layer.

Abstract: A nitrogen compound semiconductor light emitting element having an n-type layer, an active layer comprising AlGaInN and a p-type layer, emitting ultraviolet radiation with an emission peak wavelength of at most 400 nm and having a high emission intensity as well as a manufacturing method thereof are provided. In the nitrogen compound semiconductor light emitting element of the present invention having an n-type layer, an active layer and a p-type layer, the active layer consists of a nitrogen compound semiconductor layer with an emission peak wavelength of at most 400 nm comprising AlGaN, and the n-type layer has an n-type AlGaN layer comprising AlGaN and a GaN protective layer which does not contain Al and has a thickness of at least 5 nm. The active layer is formed on the protective layer. The manufacturing method comprises processes of growing the n-type AlGaN layer at a high substrate temperature of at least 1000° C.

Abstract: The present invention provides a semiconductor device, comprising: a substrate; shallow trench isolations embedded into the substrate and forming at least one opening area; a channel region located in the opening area; a gate stack comprising a gate dielectric layer and a gate electrode layer and located above the channel region; source/drain regions located at both sides of the channel region and comprising a stress layer that provides a strain to the channel region; wherein, there is a liner layer between the shallow trench isolation and the stress layer, which serves as the seed layer of the stress layer. A liner layer that is of the same or similar material as the stress layer in the source/drain region is inserted between the STI and the stress layer of the source/drain region as a seed layer or nucleation layer for the epitaxial growth, thereby eliminating the STI edge effect during the source/drain strain engineering, i.e.

Abstract: A semiconductor device and its manufacturing method are provided. The semiconductor device comprises: a semiconductor substrate of a first semiconductor material, a gate structure on the semiconductor substrate, a crystal lattice dislocation line in a channel under the gate structure for generating channel stress, wherein the crystal lattice dislocation line being at an angle to the channel.