Patents Issued in February 14, 2013
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Publication number: 20130037873Abstract: Provided is a semiconductor device capable of preventing destruction of an electrode having a pillar shape and densely arranged. The semiconductor device having a field-effect transistor and a capacitor having a pillar shape, the semiconductor device includes: a first electrode having a pillar shape and electrically connected to an impurity diffusion region of the field-effect transistor; a dielectric film formed at least on a side of the first electrode; a second electrode formed on the dielectric film; and a support film extending in a direction crossing a length direction of the first electrode having the pillar shape, and formed by a boron-added silicon nitride film connected to the first electrode by penetrating through at least a part of the second electrode.Type: ApplicationFiled: August 10, 2012Publication date: February 14, 2013Applicant: TOKYO ELECTRON LIMITEDInventors: Keisuke SUZUKI, Kentaro KADONAGA, Yuichiro MOROZUMI
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Publication number: 20130037874Abstract: A nonvolatile memory cell is able to reduce the size per the unit area by employing a dual gate structure where the chalcogenide compound is used for a channel. The nonvolatile memory cell includes a phase-change layer, a first and a second gate that are in contact with sides of the phase-change layer to face each other across the phase-in change layer and control a current flowing through the phase-change layer by each gate being arranged to induce the phase transition of the phase-change layer independently of the other.Type: ApplicationFiled: September 14, 2012Publication date: February 14, 2013Inventors: Hae-Chan PARK, Gap-Sok Do, Jang-Uk Lee
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Publication number: 20130037875Abstract: A semiconductor memory device includes a first select transistor, first stepped portion, and a first contact plug. The first select transistor is formed on a side of an upper surface of a substrate and has a first multi-layer gate. The first stepped portion is formed by etching the substrate adjacent to the first multi-layer gate of the first select transistor such that the first stepped portion forms a cavity in the upper surface of the substrate. The first contact plug is formed in the first stepped portion.Type: ApplicationFiled: October 16, 2012Publication date: February 14, 2013Inventor: Toshitake YAEGASHI
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Publication number: 20130037876Abstract: According to one embodiment, a semiconductor device includes a polysilicon film formed above a semiconductor substrate, and a silicide film of a metal formed on the polysilicon film. The semiconductor device of the embodiment includes an oxide film of the metal formed above the silicide film, and a film containing tungsten or molybdenum formed on the oxide film.Type: ApplicationFiled: March 9, 2012Publication date: February 14, 2013Applicant: Kabushiki Kaisha ToshibaInventor: Seiichi OMOTO
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Publication number: 20130037877Abstract: A split gate memory cell is fabricated with a fin structure between a memory gate stack and a select gate. Embodiments include a first channel region under the memory gate stack and a second channel region under the select gate.Type: ApplicationFiled: August 10, 2011Publication date: February 14, 2013Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Shyue Seng (Jason) Tan, Eng Huat Toh, Elgin Quek
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Publication number: 20130037878Abstract: A method for fabricating VDMOS devices includes providing a semiconductor substrate; forming a first N-type epitaxial layer on the semiconductor substrate; forming a hard mask layer with an opening on the first N-type epitaxial layer; etching the first N-type epitaxial layer along the opening until the semiconductor substrate is exposed, to form P-type barrier figures; forming a P-type barrier layer in the P-type barrier figures, the P-type barrier layer having a same thickness as that of the first N-type epitaxial layer; removing the hard mask layer; forming a second N-type epitaxial layer on the first N-type epitaxial layer and the P-type barrier layer; forming a gate on the second N-type epitaxial layer; forming a source in the second N-type epitaxial layer on both side of the gate; and forming a drain on the back of the semiconductor substrate relative to the gate and the source.Type: ApplicationFiled: June 23, 2011Publication date: February 14, 2013Applicants: CSMC TECHNOLOGIES FAB2 CO., LTD., CSMC TECHNOLOGIES FAB1 CO., LTD.Inventor: Le Wang
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Publication number: 20130037879Abstract: Vertical devices and methods of forming the same are provided. One example method of forming a vertical device can include forming a trench in a semiconductor structure, and partially filling the trench with an insulator material. A dielectric material is formed over the insulator material. The dielectric material is modified into a modified dielectric material having an etch rate greater than an etch rate of the insulator material. The modified dielectric material is removed from the trench via a wet etch.Type: ApplicationFiled: August 8, 2011Publication date: February 14, 2013Applicant: Micron Technology, Inc.Inventors: Andrea Filippini, Luca Ferrario, Marcello Mariani
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Publication number: 20130037880Abstract: A trench-gate metal oxide semiconductor device includes a substrate, a first gate dielectric layer, a first gate electrode and a first source/drain structure. The substrate has a first doping region, a second doping region and at least one trench. A P/N junction is formed between the first doping region and the second doping region. The trench extends from a surface of the substrate to the first doping region through the second doping region and the P/N junction. The first gate dielectric layer is formed on a sidewall of the second trench. The first gate electrode is disposed within the trench. A height difference between the top surface of the first gate electrode and the surface of the substrate is substantially smaller than 1500 ?. The first source/drain structure is formed in the substrate and adjacent to the first gate dielectric layer.Type: ApplicationFiled: August 9, 2011Publication date: February 14, 2013Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: Kuan-Ling LIU, Shih-Yuan UENG
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Publication number: 20130037881Abstract: A gate electrode is formed in a trench reaching a drain region so as to leave a concave portion on the top of the trench. A first insulating film is formed, which fills the concave portion and of which the thickness increases as the distance from an end of the trench increases on the substrate surface on both sides of the trench. First and second source regions are formed in a self-alignment manner by introduction of impurities through the first insulating film.Type: ApplicationFiled: October 17, 2012Publication date: February 14, 2013Applicant: PANASONIC CORPORATIONInventor: Panasonic Corporation
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Publication number: 20130037882Abstract: A semiconductor device includes a semiconductor substrate including an active region defined by a device isolation layer, a trench extending across the active region, a buried gate filling a part of the trench and including a base portion, a first extension portion, and a second extension portion extending along an inner wall of the trench, and having different heights at sides of the base portion, and a capping layer formed on the buried gate and filling the trench.Type: ApplicationFiled: August 10, 2012Publication date: February 14, 2013Inventors: Ji-young Kim, Gyo-young Jin, Hyeong-sun Hong, Yoo-sang Hwang, Sung-kwan Choi, Hyun-woo Chung
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Publication number: 20130037883Abstract: An LDPMOS structure having enhanced breakdown voltage and specific on-resistance is described, as is a method for fabricating the structure. A P-field implanted layer formed in a drift region of the structure and surrounding a tightly doped drain region effectively increases breakdown voltage while maintaining a relatively low specific on-resistance.Type: ApplicationFiled: October 10, 2012Publication date: February 14, 2013Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yin-Fu Huang, Miao-Chun Chung, Shih-Chin Lien
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Publication number: 20130037884Abstract: An active region, a source region, and a drain region are formed on a single crystal semiconductor substrate or a single crystal semiconductor thin film. Impurity regions called pinning regions are formed in striped form in the active region so as to reach both of the source region and the drain region. Regions interposed between the pinning regions serve as channel forming regions. A tunnel oxide film, a floating gate, a control gate, etc. are formed on the above structure. The impurity regions prevent a depletion layer from expanding from the source region toward the drain region.Type: ApplicationFiled: July 16, 2012Publication date: February 14, 2013Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei YAMAZAKI, Hisashi OHTANI, Jun KOYAMA, Takeshi FUKUNAGA
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Publication number: 20130037885Abstract: A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer.Type: ApplicationFiled: October 15, 2012Publication date: February 14, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: INTERNATIONAL BUSINESS MACHINES CORP
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Publication number: 20130037886Abstract: A semiconductor device includes a semiconductor substrate, at least a first fin structure, at least a second fin structure, a first gate, a second gate, a first source/drain region and a second source/drain region. The semiconductor substrate has at least a first active region to dispose the first fin structure and at least a second active region to dispose the second fin structure. The first/second fin structure partially overlapped by the first/second gate has a first/second stress, and the first stress and the second stress are different from each other. The first/second source/drain region is disposed in the first/second fin structure at two sides of the first/second gate.Type: ApplicationFiled: August 10, 2011Publication date: February 14, 2013Inventors: Teng-Chun Tsai, Chun-Yuan Wu, Chih-Chien Liu, Chin-Cheng Chien, Chin-Fu Lin
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Publication number: 20130037887Abstract: According to one embodiment, a semiconductor device includes a source region having p-type conductivity, a drain region having p-type conductivity, a channel region provided between the source region and the drain region and having n-type conductivity, a lower gate insulating film provided on the channel region, a lower gate electrode provided on the lower gate insulating film, an upper gate insulating film provided on the lower gate electrode, an upper gate electrode provided on the upper gate insulating film, and a switching element connected between the lower gate electrode and the source region.Type: ApplicationFiled: March 8, 2012Publication date: February 14, 2013Applicant: Kabushiki Kaisha ToshibaInventor: Osamu Takata
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Publication number: 20130037888Abstract: A semiconductor device includes an active region defined by a device isolation layer and including first and second sections or regions, a gate electrode extending in a first direction across the active region over a channel between the first region and the second region and including at least one first gate tab protruding in a second direction toward the first region, and first and second contact plugs. The first gate tab covers and extends along a boundary between the active region and the device isolation layer. The first contact plug is disposed over the first region, the second contact plug is disposed over the second region, and the second contact plug has an effective width, as measured in the first direction, greater than that of the first contact plug.Type: ApplicationFiled: August 9, 2012Publication date: February 14, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: SEUNG-UK HAN, NAM-HO JEON
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Publication number: 20130037889Abstract: A fabricating method of semiconductor structure is provided. First, a substrate with a dielectric layer formed thereon is provided. The dielectric layer has a first opening and a second opening exposing a portion of the substrate. Further, a gate dielectric layer including a high-k dielectric layer and a barrier layer stacked thereon had been formed on the bottoms of the first opening and the second opening. Next, a sacrificial layer is formed on the portion of the gate dielectric layer within the second opening. Next, a first work function metal layer is formed to cover the portion of the gate dielectric layer within the first opening and the sacrificial layer. Then, the portion of the first work function metal layer and the sacrificial layer within the second opening are removed.Type: ApplicationFiled: August 8, 2011Publication date: February 14, 2013Applicant: UNITED MICROELECTRONICS CORP.Inventors: Duan-Quan LIAO, Yi-Kun Chen, Xiao-Zhong Zhu
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Publication number: 20130037890Abstract: The present disclosure provides for multiple gate dielectric semiconductor structures and methods of forming such structures. In one embodiment, a method of forming a semiconductor structure includes providing a substrate including a pixel array region, an input/output (I/O) region, and a core region. The method further includes forming a first gate dielectric layer over the pixel array region, forming a second gate dielectric layer over the I/O region, and forming a third gate dielectric layer over the core region, wherein the first gate dielectric layer, the second gate dielectric layer, and the third gate dielectric layer are each formed to be comprised of a different material and to have a different thickness.Type: ApplicationFiled: August 11, 2011Publication date: February 14, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsiao-Hui Tseng, Dun-Nian Yaung, Jen-Cheng Liu, Wen-I Hsu, Min-Feng Kao
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Publication number: 20130037891Abstract: The present disclosure provides a method including providing a first substrate; and forming a microelectromechanical system (MEMS) device on a first surface of the first substrate. A bond pad is formed on at least one bonding site on the first surface of the first substrate. The bonding site is recessed from the first surface. Thus, a top surface of the bond pad may lie below the plane of the top surface of the substrate. A device with recessed connective element(s) (e.g., bond pad) is also described. In further embodiments, a protective layer is formed on the recessed connective element during dicing of a substrate.Type: ApplicationFiled: August 9, 2011Publication date: February 14, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd., ("TSMC")Inventors: Hsin-Ting Huang, Jung-Huei Peng, Shang-Ying Tsai, Yao-Te Huang, Ming-Tung Wu, Ping-Yin Liu, Xin-Hua Huang, Yuan-Chih Hsieh
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Publication number: 20130037892Abstract: A semiconductor device includes a pinned layer having a magnetic direction permanently set to a first direction, a tunnel insulating layer arranged on the pinned layer, a free layer arranged on the tunnel insulating layer and having a changeable magnetic direction, and a magnetic induction layer formed to surround the pinned layer and have a magnetic direction permanently set to a second direction different from the first direction.Type: ApplicationFiled: December 20, 2011Publication date: February 14, 2013Inventor: Ji Ho PARK
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Publication number: 20130037893Abstract: A semiconductor device includes a first free layer having a magnetic direction that changes according to a direction and an amount of a first current, a first tunnel insulating layer arranged on the first free layer, a pinned layer, arranged on the first tunnel insulating layer, having a magnetic direction set to a first direction, a second tunnel insulating layer arranged on the pinned layer, and a second free layer, arranged on the second tunnel insulating layer, having a magnetic direction that changes according to a direction and an amount of a second current.Type: ApplicationFiled: December 23, 2011Publication date: February 14, 2013Inventor: Seung Hyun LEE
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Publication number: 20130037894Abstract: In a method for fabricating a magnetic tunnel junction, a fixed layer, a tunnel insulating layer, a free layer, and an anti-etch layer are formed on a substrate. A sacrificial layer having a hole is formed on the anti-etch layer. An upper electrode is buried in the hole. The sacrificial layer is removed. The anti-etch layer, the free layer, the tunnel insulating layer, and the fixed layer are etched using the upper electrode as a mask.Type: ApplicationFiled: December 23, 2011Publication date: February 14, 2013Inventor: Su Ock CHUNG
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Publication number: 20130037895Abstract: In a method for fabricating a semiconductor device, a conductive layer is formed on a substrate, where the substrate has a bottom layer formed thereon. A magnetic tunnel junction layer is formed on the conductive layer. The magnetic tunnel junction layer is patterned using an etching gas containing oxygen. An insulating layer is formed by oxidizing the conductive layer exposed outside the patterned magnetic tunnel junction layer using the etching gas.Type: ApplicationFiled: December 23, 2011Publication date: February 14, 2013Inventors: Min Suk LEE, Bo Kyoung Jung
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Publication number: 20130037896Abstract: A method for fabricating a semiconductor device includes forming a magnetic tunnel junction (MTJ) element on a substrate, forming a first capping layer along the shape of the MTJ element, forming an insulating layer on the first capping layer, forming a trench exposing a portion of the first capping layer above the MTJ element by selectively etching the insulating layer, forming a second capping layer on sidewalls of the trench, removing the exposed portion of the first capping layer using the second capping layer as an etching mask to expose an upper surface of the MTJ element, and forming a conductive layer in the trench, wherein the conductive layer contacts the upper surface of the MTJ element.Type: ApplicationFiled: June 21, 2012Publication date: February 14, 2013Inventors: Jung Woo Park, Gil Jae Park, Ki Seon Park
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Publication number: 20130037897Abstract: Disclosed is a novel non-volatile, ferroelectric random access memory (F-RAM) device and a method for fabricating a damascene self-aligned F-RAM device structure on a planar surface using a reduced number of masks and etching steps.Type: ApplicationFiled: August 8, 2012Publication date: February 14, 2013Applicant: RAMTRON INTERNATIONAL CORPORATIONInventors: Shan Sun, Thomas E. Davenport, John Cronin
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Publication number: 20130037898Abstract: A memory device includes a first plurality of magnetic random access memory (MRAM) cells positioned along a first direction, and a first bit line electrically connected to the first plurality of MRAM cells, the bit line oriented in the first direction. The device includes a first plurality of field lines oriented in a second direction different from the first direction, the first plurality of field lines being spaced such that only a corresponding first one of the first plurality of MRAM cells is configurable by each of the first plurality of field lines. The device includes a second plurality of field lines oriented in a third direction different from the first direction and the second direction, the second plurality of field lines being spaced such that only a corresponding second one of the first plurality of MRAM cells is configurable by each of the second plurality of field lines.Type: ApplicationFiled: August 10, 2012Publication date: February 14, 2013Applicant: CROCUS TECHNOLOGY, INC.Inventors: Bertrand F. Cambou, Douglas J. Lee, Anthony J. Tether, Barry Hoberman
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Publication number: 20130037899Abstract: A semiconductor structure for photon detection, comprising a substrate composed of a semiconductor material having a first doping, a contact region fitted at the frontside of the substrate, a bias layer composed of a semiconductor material having a second doping, which is arranged on the backside of the substrate at a distance from the contact region, wherein the contact region at least partly lies opposite the bias layer, such that an overlap region is present in a lateral direction, a guard ring, which is arranged at the frontside of the substrate and surrounds the contact region, wherein a reverse voltage can be applied between the contact region and the guard ring. In order to enable more cost-effective production, the overlap region has a lateral extent amounting to at least one quarter of the distance between contact region and bias layer.Type: ApplicationFiled: July 18, 2012Publication date: February 14, 2013Applicant: ESPROS Photonics AGInventors: Martin POPP, Beat DE COI, Marco ANNESE
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Publication number: 20130037900Abstract: A solid-state imaging element includes a pixel having a photoelectric conversion section and a side pinning layer. The photoelectric conversion section is formed in a semiconductor substrate. The side pinning layer is formed on a side of the photoelectric conversion section. The side pinning layer is formed by performing ion implantation in a state of a trench being open, the trench being formed in a part on a side of a region in which the photoelectric conversion section is formed.Type: ApplicationFiled: August 1, 2012Publication date: February 14, 2013Applicant: SONY CORPORATIONInventor: Takashi Abe
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Publication number: 20130037901Abstract: It is an object to provide a photoelectric conversion device with high photoelectric conversion efficiency that improves reliability by increasing contact force between a light absorbing layer and an electrode layer. The photoelectric conversion device includes an electrode layer, and a light absorbing layer located on the electrode layer. The light absorbing layer contains a compound semiconductor. The light absorbing layer comprises a first layer close to the electrode layer and a second layer located on the first layer. The first layer has a void ratio lower than that of the second layer.Type: ApplicationFiled: April 22, 2011Publication date: February 14, 2013Applicant: KYOCERA CORPORATIONInventors: Shintaro Kubo, Shuji Nakazawa, Rui Kamada, Seiji Oguri, Shinnosuke Ushio, Shuichi Kasai, Seiichiro Inai
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Publication number: 20130037902Abstract: An image sensing device includes a light-shielding film having transit portions, a first film and a second film. The second film comprises a first layer having a different refractive index from the first film. The first layer lies within at least the transit portions, and forms interfaces with the first film. The distance between the interface and the corresponding photoelectric conversion portion is greater than the distance between the photoelectric conversion portion and the lower end of the corresponding transit portion.Type: ApplicationFiled: August 3, 2012Publication date: February 14, 2013Applicant: CANON KABUSHIKI KAISHAInventors: Toru Nakazawa, Hiroaki Kobayashi
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Publication number: 20130037903Abstract: Disclosed is a display device that is configured such that light that is emitted from a backlight or the like and that illuminates a display panel is prevented from being transmitted through a light-shielding layer that is provided between a light sensor element and a substrate. A liquid crystal display device 1 is provided with: a photodiode 10, which is formed on a substrate 30 that constitutes a part of the display panel; and a light-shielding film 20, which is formed between the substrate 30 and the photodiode 10. The thickness of the light-shielding film 20 is 100 nm or more.Type: ApplicationFiled: April 5, 2011Publication date: February 14, 2013Applicant: SHARP KABUSHIKI KAISHAInventors: Hiroyuki Kaigawa, Isao Nakanishi
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Publication number: 20130037904Abstract: An object is to provide a PTC element that can be made thinner, using a Pb-free semiconductor ceramic composition. The object is achieved with a PTC element including at least two metal electrodes and a BaTiO3 system semiconductor ceramic composition arranged between the electrodes, in which, in the semiconductor ceramic composition, a portion of Ba in the BaTiO3 system is substituted by Bi—Na and a semiconductorizing element, vacancies are formed on Bi sites by depleting at least a portion of Bi, and oxygen defects are formed on a crystal thereof. Since the PTCR characteristic at the inside of the semiconductor ceramic composition is negligibly weak in comparison with the PTCR characteristic at the interface between the semiconductor ceramic composition and the electrodes, the PTC element can be made thinner.Type: ApplicationFiled: April 6, 2011Publication date: February 14, 2013Applicant: HITACHI METALS, LTD.Inventors: Takesha Shimada, Kentaro Ino, Toshiki Kida
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Publication number: 20130037905Abstract: In a hybrid integrated module, a semiconductor die is mechanically coupled face-to-face to an integrated device in which the substrate has been removed. For example, the integrated circuit may include an optical device fabricated on a silicon-on-insulator (SOI) wafer in which the backside silicon handler has been completely removed, thereby facilitating improved device performance and highly efficient thermal tuning of the operating wavelength of the optical device. Moreover, the semiconductor die may be a VLSI chip that provides power, and serves as a mechanical handler and/or an electrical driver. The thermal tuning efficiency of the substrateless optical device may be enhanced by over 100× relative to an optical device with an intact substrate, and by 5× relative to an optical device in which the substrate has only been removed in proximity to the optical device.Type: ApplicationFiled: August 9, 2011Publication date: February 14, 2013Applicant: ORACLE INTERNATIONAL CORPORATIONInventors: Ivan Shubin, Ashok V. Krishnamoorthy, John E. Cunningham
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Publication number: 20130037906Abstract: A semiconductor device having a semiconductor die is provided. The semiconductor die includes a main horizontal surface, an outer edge, an active area, and a peripheral area. The peripheral area includes a dielectric structure surrounding the active area and extending from the main horizontal surface into the semiconductor die. The dielectric structure includes, in a horizontal cross-section, at least one substantially L-shaped portion that is inclined against the outer edge. Further, a method for forming a semiconductor device is provided.Type: ApplicationFiled: August 9, 2011Publication date: February 14, 2013Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Franz Hirler, Anton Mauder, Hans-Joachim Schulze
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Publication number: 20130037907Abstract: An optoelectronic integrated circuit substrate may include a first region and a second region. The first region and the second region each include at least two buried insulation layers having different thicknesses. The at least two buried insulation layers of the first region are formed at a greater depth and have a greater thickness as compared to the at least two buried insulation layers of the second region. A micro-electromechanical systems (MEMS) structure may be formed in a third region that does not include a buried insulation layer.Type: ApplicationFiled: January 31, 2012Publication date: February 14, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: Seong-ho Cho
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Publication number: 20130037908Abstract: The spikes in current and voltage that result from the failure of a galvanic dielectric layer are safely contained by a galvanic isolation fuse that pops and forms and open circuit between a high-voltage die and a low-voltage die in response to the failure of the galvanic dielectric layer.Type: ApplicationFiled: August 12, 2011Publication date: February 14, 2013Inventors: Peter J. Hopper, William French, Ann Gabrys, Martin Fallon
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Publication number: 20130037909Abstract: Galvanic isolation between a high-voltage die and a low-voltage die in a multi-die chip is provided by a galvanic isolation die that physically supports the high-voltage die and the low-voltage die, and provides capacitive structures with high breakdown voltages that allow the high-voltage die to capacitively communicate with the low-voltage die.Type: ApplicationFiled: August 9, 2011Publication date: February 14, 2013Inventors: William French, Peter J. Hopper, Ann Gabrys
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Publication number: 20130037910Abstract: Decoupling metal-insulator-metal (MIM) capacitor designs for interposers and methods of manufacture thereof are disclosed. In one embodiment, a method of forming a decoupling capacitor includes providing a packaging device, and forming a decoupling MIM capacitor in at least two metallization layers of the packaging device.Type: ApplicationFiled: August 12, 2011Publication date: February 14, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Chyuan Tzeng, Kuo-Chi Tu, Chen-Jong Wang, Hsiang-Fan Lee
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Publication number: 20130037911Abstract: In a chip-component structure, a monolithic ceramic capacitor is a structure including a predetermined number of substantially flat internal electrodes stacked on each other. An interposer includes a substrate larger than the outer shape of the monolithic ceramic capacitor. The substrate includes a first major surface on which first front electrodes for use in mounting the monolithic ceramic capacitor are disposed and a second major surface on which first back electrodes for use in connecting to an external circuit board are disposed. The interposer includes a depression in its side surface. The depression includes a wall surface on which a connection conductor is disposed. The front surface of the substrate is overlaid with resist films extending along its edges.Type: ApplicationFiled: August 8, 2012Publication date: February 14, 2013Applicant: MURATA MANUFACTURING CO., LTD.Inventors: Kazuo HATTORI, Isamu FUJIMOTO
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Publication number: 20130037912Abstract: Disclosed is a non-volatile, ferroelectric random access memory (F-RAM) device and a method for fabricating the same in the form of a damascene self-aligned F-RAM device comprising a PZT capacitor built on the sidewalls of an oxide trench, while allowing for the simultaneous formation of two ferroelectric sidewall capacitors.Type: ApplicationFiled: August 8, 2012Publication date: February 14, 2013Applicant: Ramtron International CorporationInventors: Shan Sun, Thomas E. Davenport, John Cronin
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Publication number: 20130037913Abstract: This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor and DRAM cell. In particular, a bottom electrode has a material selected for lattice matching characteristics. This material may be created from a relatively inexpensive metal oxide which is processed to adopt a conductive, but difficult-to-produce oxide state, with specific crystalline form; to provide one example, specific materials are disclosed that are compatible with the growth of rutile phase titanium dioxide (TiO2) for use as a dielectric, thereby leading to predictable and reproducible higher dielectric constant and lower effective oxide thickness and, thus, greater part density at lower cost.Type: ApplicationFiled: October 19, 2012Publication date: February 14, 2013Applicant: INTERMOLECULAR INC.Inventor: INTERMOLECULAR INC.
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Publication number: 20130037914Abstract: A bipolar junction transistor and a manufacturing method for the same are provided. The bipolar junction transistor includes a well region, an emitter electrode, a base electrode, a collector electrode, and a conductive layer. The emitter electrode, the base electrode and the collector electrode are separated from each other by the well region. The conductive layer is on the well region between the base electrode and the collector electrode.Type: ApplicationFiled: August 8, 2011Publication date: February 14, 2013Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chin-Wei Chang, Ching-Lin Chan, Chin-Shien Lu, Ming-Tung Lee, Shuo-Lun Tu
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Publication number: 20130037915Abstract: A method provides a layout defining a structure to be patterned onto a substrate. The structure is registered with a predefined grid of the layout. The method includes locally stretching the grid in a first portion of a layout causing a problematic spot on the substrate.Type: ApplicationFiled: August 11, 2011Publication date: February 14, 2013Applicant: Infineon Technologies AGInventor: Hanno Melzner
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Publication number: 20130037916Abstract: A break pattern of a silicon wafer includes a line to be cut which is set in the silicon wafer assuming a surface as a (110) face in a surface direction of a first (111) face perpendicular to the (110) face; and through holes which are provided in a plurality of rows on the line to be cut, wherein each of the through holes has a first (111) face, a second (111) face which intersects the first (111) face, and a third (111) face which intersects the second (111) face and the first (111) face, an intersecting point with end edges of the second (111) face and the third (111) face is assumed as a point closest to the adjacent through holes.Type: ApplicationFiled: August 9, 2012Publication date: February 14, 2013Applicant: SEIKO EPSON CORPORATIONInventor: Isamu TOGASHI
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Publication number: 20130037917Abstract: A method for forming a wafer level chip scale (WLCS) package device with a thick bottom metal comprising the step of attaching a lead frame comprising a plurality of thick bottom metals onto a back metal layer of a semiconductor wafer including a plurality of semiconductor chips having a plurality of bonding pads formed on a front surface of each chip, each thick bottom metal is aligned to a central portion of each chip; a plurality of back side cutting grooves are formed along the scribe lines and filled with a package material, the package material are cut through thus forming a plurality of singulated WLCS package devices.Type: ApplicationFiled: September 1, 2012Publication date: February 14, 2013Inventor: Yan Xun Xue
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Publication number: 20130037918Abstract: A semiconductor structure is provided in the present invention. The semiconductor structure includes a substrate, a first material layer and a second material layer. A trench region is defined on the substrate. The trench region includes two separated first regions and a second region, wherein the second region is adjacent to and between the two first regions. The first material layer is disposed on the substrate outside the trench region. The second material layer is disposed in the second region and is level with the first material layer.Type: ApplicationFiled: August 10, 2011Publication date: February 14, 2013Inventor: Tong-Yu Chen
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Publication number: 20130037919Abstract: A method of creating a trench having a portion of a bulb-shaped cross-section in silicon is disclosed. The method comprises forming at least one trench in silicon and forming a liner in the at least one trench. The liner is removed from a bottom surface of the at least one trench to expose the underlying silicon. A portion of the underlying exposed silicon is removed to form a cavity in the silicon. At least one removal cycle is conducted to remove exposed silicon in the cavity to form a bulb-shaped cross-sectional profile, with each removal cycle comprising subjecting the silicon in the cavity to ozonated water to oxidize the silicon and subjecting the oxidized silicon to a hydrogen fluoride solution to remove the oxidized silicon. A semiconductor device structure comprising the at least one trench comprising a cavity with a bulb-shaped cross-sectional profile is also disclosed.Type: ApplicationFiled: August 10, 2011Publication date: February 14, 2013Applicant: MICRON TECHNOLOGY, INC.Inventors: Sanjeev Sapra, Cheng-Shun Chen, Hung-Ming Tsai, Sheng-Wei Yang
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Publication number: 20130037920Abstract: The present invention includes a method for manufacturing a silicon epitaxial wafer having a silicon homoepitaxial layer formed on a surface of a silicon single crystal wafer, including the steps of: preparing the silicon single crystal wafer such that a plane orientation of the silicon single crystal wafer is tilted at an angle in the range from 0.1° to 8° in a <112> direction from a {110} plane; and growing the silicon homoepitaxial layer on the prepared silicon single crystal wafer. According to the present invention, a silicon epitaxial wafer using the {110} substrate with improved surface quality, such as Haze and surface roughness and a method for manufacturing the silicon epitaxial wafer are provided.Type: ApplicationFiled: April 28, 2011Publication date: February 14, 2013Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Yutaka Shiga, Hiroshi Takeno
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Publication number: 20130037921Abstract: A resist underlayer composition, including a solvent, and an organosilane condensation polymerization product of hydrolyzed products produced from a compound represented by Chemical Formula 1, a compound represented by Chemical Formula 2, and a compound represented by Chemical Formula 3.Type: ApplicationFiled: August 10, 2012Publication date: February 14, 2013Inventors: Kwen-Woo HAN, Mi-Young KIM, Woo-Jin LEE, Han-Song LEE, Seung-Hee HONG, Sang-Kyun KIM, Jin-Wook LEE
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Publication number: 20130037922Abstract: An integrated circuit chip is formed with a circuit layer, a trap rich layer and through-semiconductor-vias. The trap rich layer is formed above the circuit layer. The through-semiconductor-vias are also formed above the circuit layer. In some embodiments, the circuit layer is included in a wafer, and the trap rich layer and through-semiconductor-vias are included in another wafer. The two wafers are bonded together after formation of the trap rich layer and through-semiconductor-vias. Additionally, in some embodiments, yet another wafer may also be bonded to the wafer that includes the trap rich layer and through-semiconductor-vias. Furthermore, in some embodiments, another circuit layer may be formed in the wafer that includes the trap rich layer and through-semiconductor-vias.Type: ApplicationFiled: October 15, 2012Publication date: February 14, 2013Applicant: IO SEMICONDUCTOR, INC.Inventor: IO SEMICONDUCTOR, INC.
