Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate, a gate electrode provided on the semiconductor substrate via an insulating layer, and a gate insulator provided on a side surface of the gate electrode. The device includes a stacked layer including a lower main terminal layer of a first conductivity type, an intermediate layer, and an upper main terminal layer of a second conductivity type which are successively stacked on the semiconductor substrate, the stacked layer being provided on the side surface of the gate electrode via the gate insulator. The upper or lower main terminal layer is provided on the side surface of the gate electrode via the gate insulator and the semiconductor layer.

Abstract: Cell electrodes are provided respectively for cell structures on a semiconductor substrate. The cell electrodes are divided into groups each including two or more cell electrodes. Conductive members are respectively electrically connected to the groups. The conductive members have a used portion and an unused portion. The used portion has two or more conductive members electrically connected to each other. The unused portion has at least one of the conductive members and is electrically insulated from the used portion.

Abstract: Disclosed is a semiconductor light emitting chip (20) that is composed of: a substrate (10), which has the C plane of a sapphire single crystal as the front surface, and the side surfaces (25, 26) configured of planes that intersect all the planes equivalent to the M plane of the sapphire single crystal, and which includes modified regions (23, 24) in the side surfaces (25, 26), the modified regions being formed by laser radiation; and a light emitting element (12), which is provided on the substrate front surface (10a) of the substrate (10). In the semiconductor light emitting chip, a tilt of the substrate side surfaces with respect to the substrate front surface is suppressed. Also disclosed is a method for processing the substrate.

Abstract: A light emitting diode (LED) package module and the manufacturing method thereof are presented. A plurality of LEDs and a plurality of semiconductor elements are disposed on a silicon substrate, and then a plurality of lenses is formed above the positions of the plurality of the LEDs, and the plurality of the lenses is corresponding to the plurality of the LEDs. Then, a plurality of package units is defined on the silicon substrate, and each package unit has a semiconductor element and at least one LED. After that, the silicon substrate is cut to form a plurality of LED package modules, and each LED package module has at least one package unit.

Abstract: Embodiments may provide a light source with a controlled brightness variation. A first device is provided that includes a substrate and a plurality of OLEDs disposed on the substrate. Each of the OLEDs includes a first electrode, a second electrode, and an organic electroluminescent (EL) material disposed between the first and the second electrodes. The plurality of OLEDs comprise a first group and a second group where a first current density is supplied to the first group of the plurality of OLEDs and a second current density that is different from the first current density is supplied to the second group of the plurality of OLEDs. Each of the plurality of OLEDs is commonly addressable and at least one of the OLEDs in the first group of OLEDs has substantially the same device structure as at least one of the OLEDs in the second group of OLEDs.

Abstract: An organic light-emitting display and a method of manufacturing the organic light-emitting display are disclosed. In one embodiment, the organic light-emitting display includes: i) a pixel electrode disposed on a substrate, ii) an opposite electrode disposed opposite to the pixel electrode, iii) an organic emission layer disposed between the pixel electrode and the opposite electrode; a light-scattering portion disposed between the substrate and the organic emission layer, including a plurality of scattering patterns for scattering light emitted from the organic emission layer in insulating layers having different refractive indexes. The display may further include a plurality of light absorption portions disposed between the light-scattering portion and the organic emission layer to correspond to the scattering patterns.

Abstract: A display substrate includes a base substrate; a first metal pattern disposed on the base substrate and comprising a first signal line and a first electrode electrically connected to the first signal line; and a buffer pattern disposed at a corner between a sidewall surface of the first metal pattern and the base substrate.

Abstract: A light emitting diode package includes a heat-dissipating substrate including a reflective groove having a lower bottom surface, an upper opening having a width greater than the lower bottom surface, and an inclined surface formed between the upper opening and the lower bottom surface and mounting grooves, each formed in the reflective groove and having a lower bottom surface, an upper opening having a width greater than the lower bottom surface, and an inclined surface formed between the upper opening and the lower bottom surface; an insulating layer selectively formed on the heat-dissipating substrate; wiring pattern layers formed on the insulating layer and extending to bottom surfaces of the mounting grooves to be selectively formed thereon; a light emitting diode chip mounted in each of the mounting grooves; and a molding layer formed around the light emitting diode chip.

Abstract: A method for manufacturing a device that includes an opto-electronic module includes creating a wafer stack including multiple active optical components mounted on a substrate wafer, and an optics wafer including multiple passive optical components. The optics wafer can include a blocking portion, which is substantially non-transparent for at least a specific wavelength range, and a transparent portion, which is substantially non-transparent for the specific wavelength range. Each opto-electronic module includes a substrate member, an optics member, an active optical component mounted on the substrate member, and a passive optical component. The optics member is directly or indirectly fixed to the substrate member. The opto-electronic modules can have excellent manufacturability, small dimensions and high alignment accuracy.

Abstract: One embodiment provides a structure, comprising: a display; at least one structural component disposed over a portion of the display, wherein the at least on structural component comprises at least one amorphous alloy; and wherein a portion of the display is foldable.

Abstract: The present invention relates to an optical device and a method for manufacturing the same. The technical object of the invention is to realize a surface emitting body which allows heat generated from a light-emitting chip to be easily dissipated, eliminates the need for an additional wiring layer, and allows a singular light emitting chips or a plurality of light emitting chips to be arranged in series, in parallel, or in series-parallel. The present invention discloses an optical device comprising: a substrate; a plurality of light emitting chips disposed on the substrate; a plurality of conductive wires which electrically connect the substrate with the light emitting chips such that the plurality of light emitting chips are connected to each other in series, in parallel or in series-parallel; and a protective layer which covers the plurality of light emitting chips and the plurality of conductive wires on the substrate.

Abstract: According to an aspect of the invention, there is provided a light emitting element module substrate including: a laminated plate; and a metal layer. The laminated plate includes a base metal plate and an insulating layer provided on the base metal plate. The metal layer is provided on the insulating layer. The metal layer includes a mounting section on which a light emitting element is to be mounted, and a bonding section to which a wiring electrically connected to the light emitting element is to be bonded. The metal layer includes a silver layer which is an uppermost layer of at least one of the mounting section and the bonding section and is formed by electrolytic plating. The mounting section and the bonding section are electrically isolated from a periphery of the laminated plate.

Abstract: A display device is provided with a reinforced power line. The display device includes a common power line. A light emission layer is interposed between a first and a second electrode. A passivation layer is formed over the second electrode and has a stepped shape. An auxiliary metal layer is coupled to a common power line. At least a portion of the auxiliary metal layer is formed over the passivation layer and has a shape that follows the stepped shape of the passivation layer.

Abstract: A light emitting device that includes a conductive substrate, an insulating layer on the conductive substrate, a plurality of light emitting device cells on the insulating layer, a connection layer electrically interconnecting the light emitting device cells, a first contact section electrically connecting the conductive substrate with at least one light emitting device cell, and a second contact section on the at least one light emitting device cell.

Abstract: A package for a light source is disclosed. In particular, a Plastic Leaded Chip Carrier (PLCC) is described which provides many features offered by traditional surface mount technology lamps, but also has a decreased height, increased light output, and enables a smaller viewing angle as compared to traditional surface mount technology lamps.

Abstract: Light-emitting elements such as LEDs are associated with light-converting material such as phosphor and/or other material. A donor substrate comprising the light-converting and/or other material is suitably placed relative to a target substrate associated with the light-emitting elements. A laser or other energy source is then used to transfer the light-converting and/or other material in a pattern via writing or masking from the donor substrate to the target substrate in accordance with the pattern. Addressability and targetability of the transfer process facilitates precise patterning of the target substrate.

Abstract: A semiconductor light emitting element of the present invention includes a support substrate, a semiconductor film including a light emitting layer, a surface electrode provided on the surface on a light-extraction-surface side of the semiconductor film, and a light reflecting layer. The surface electrode includes first electrode pieces that form ohmic contact with the semiconductor film and a second electrode piece electrically connected to the first electrode pieces. The light reflecting layer includes a reflecting electrode, and the reflecting electrode includes third electrode pieces that form ohmic contact with the semiconductor film and a fourth electrode piece electrically connected to the third electrode pieces and placed opposite to the second electrode piece. Both the second electrode piece and the fourth electrode piece form Schottky contact with the semiconductor film so as to form barriers to prevent forward current in the semiconductor film.

Abstract: The present invention relates to an epoxy resin composition for an optical semiconductor device having an optical semiconductor element mounting region and having a reflector that surrounds at least a part of the region, the epoxy resin composition being an epoxy resin composition for forming the reflector, the epoxy resin composition including the following ingredients (A) to (E): (A) an epoxy resin; (B) a curing agent; (C) a white pigment; (D) an inorganic filler; and (E) a specific release agent.

Abstract: Disclosed is a semiconductor light emitting device. The semiconductor light emitting device comprises a substrate; a light emitting structure comprising a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer on the substrate; an electrode layer on the second conductive semiconductor layer; and an electrode on the electrode layer, wherein the substrate comprises a plurality of convex portions, wherein the electrode layer comprises a plurality of holes corresponding to a region of at least one of the plurality of convex portions of the substrate, wherein an insulating material is disposed in the plurality of holes on the light emitting structure.

Abstract: A light emitting device (100) includes a base member (101), electrically conductive members (102a, 102b) disposed on the base member (101), a light emitting element (104) mounted on the electrically conductive members (102a, 102b), an insulating filler (114) covering at least a portion of surfaces of the electrically conductive members (102a, 102b) where the light emitting element (104) is not mounted, and a light transmissive member (108) covering the light emitting element (104).

Abstract: A light emitting transistor of the present invention has a light emitting layer, both a source electrode and a drain electrode both of which are connected with the light emitting layer electrically, an insulation layer arranged on the light emitting layer, a gate electrode arranged on the insulation layer. The light emitting layer is made from an organic semiconductor material. The light emitting transistor has also a periodic structure and the gate electrode to which an AC voltage is applied. And the emission intensity can be high, and width of the emission spectrum can be reduced. In addition, it is easy to control the amplitude of the emitting light and the width of emission spectrum reproducibly.

Abstract: A light-emitting device (100) is provided with a metal part (2) atop a planar LED substrate (1), and an LED element (3) is disposed atop the metal part (2). A glass substrate (5) is provided to an upper surface of the LED element (3), and a wavelength conversion part (6) is formed on an upper surface of the glass substrate (5). The wavelength conversion part (6) comprises a light-transmissive ceramic layer formed by heating a mixture containing a phosphor, an organometallic compound, a layered silicate mineral, an inorganic particulate, an organic solvent, and water.

Abstract: A light emitting diode (LED) module includes a lead frame having a number (N) of conducting arms spaced apart from each other, where N?3, and at least one LED die mounted on one of any two neighbor conducting arms. Any two neighbor conducting arms are electrically coupled each other.

Abstract: The present invention relates to a divalent europium-activated nitride red light emitting phosphor substantially represented by a general formula: (MI1-xEux)MIISiN3 (1) (in the formula (1), MI is an alkaline-earth metal element and represents at least one element selected from the group consisting of Mg, Ca, Sr, and Ba; MII is a trivalent metal element and represents at least one element selected from the group consisting of Al, Ga, In, Sc, Y, La, Gd, and Lu; and x is the number satisfying 0.001?x?0.10), in which the electrical conductivity of a supernatant liquid of the solution containing 10 parts by mass of pure water with respect to 1 part by mass of the red light emitting phosphor is not more than 10 mS/cm.

Abstract: A layered substrate includes a first substrate including an upper surface, a lower surface, a peripheral surface between peripheral edges of the upper surface and the lower surface, and a cut portion cut into the peripheral surface and passing through the upper surface and the lower surface, and a second substrate including an upper surface, a lower surface, and a peripheral surface between peripheral edges of the upper surface and the lower surface, and the lower surface of the second substrate layered on the upper surface of the first substrate and closing the cut portion of the first substrate from above. The second substrate includes a heat conductor that is thermally connected to an element to be mounted on the upper surface of the second substrate, the heat conductor configured to thermally extend to the cut portion of the first substrate.

Abstract: Disclosed are a light emitting device and a light emitting device package having the same. The light emitting device includes a light emitting structure including a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer, a first electrode disposed in an opening portion of the light emitting structure and contacted with a portion of the first conductive type semiconductor layer, an insulating layer covering the first electrode, a second electrode disposed on the insulating layer and connected to the second conductive type semiconductor layer, a first electrode layer under the second electrode.

Abstract: A method of manufacturing a vertical structure light emitting diode device, the method including: sequentially forming a first conductivity type III-V group compound semiconductor layer, an active layer, and a second conductivity type III-V group compound semiconductor layer on a substrate for growth; bonding a conductive substrate to the second conductivity type III-V group compound semiconductor layer; removing the substrate for growth from the first conductivity type III-V group compound semiconductor layer; and forming an electrode on an exposed portion of the first conductive III-V group compound semiconductor layer due to the removing the substrate for growth, wherein the bonding a conductive substrate comprises partially heating a metal bonding layer by applying microwaves to a bonding interface while bringing the metal bonding layer into contact with the bonding interface.

Abstract: Disclosed are: a semiconductor light-emitting element that fulfills all of having high migration prevention, high transmittance, and low film-production cost; the protective film of the semiconductor light-emitting element; and a method for fabricating same. To this end, in the semiconductor light-emitting element-which has: a plurality of semiconductor layers (12-14) formed on a substrate (11); and electrode sections (15, 16) and other electrode sections (17, 18) that are the electrodes of the plurality of semiconductor layers (12-14)—as the protective film thereof, the surroundings of the plurality of semiconductor layers (12-14), the electrode sections (15, 16), and the other electrode sections (17, 18) are covered by a SiN film (21) comprising silicon nitride of which the quantity of Si—H bonds in the film is less than 1.0×1021 bonds/cm3.

Abstract: A semiconductor device including a base semiconductor layer of a first conductivity type, a cell portion including a diffusion region of a second conductivity type formed on a surface of the base semiconductor layer, a plurality of guard ring semiconductor layers of the second conductivity type formed on the surface of the base semiconductor layer, each guard ring semiconductor layer being formed to surround the cell portion, a plurality of first RESURF semiconductor layers of the first conductivity type provided on the surface of the base semiconductor layer inside the plurality of guard ring semiconductor layers and having a higher concentration than the base semiconductor layer and a second RESURF semiconductor layer of the first conductivity type provided on the surface of the base semiconductor layer between the outermost guard ring semiconductor layer and the EQPR semiconductor layer.

Abstract: Super-junction MOSFETs by trench fill system requires void-free filling epitaxial growth. This may require alignment of plane orientations of trenches in a given direction. Particularly, when column layout at chip corner part is bilaterally asymmetrical with a diagonal line between chip corners, equipotential lines in a blocking state are curved at corner parts due to column asymmetry at chip corner. This tends to cause points where equipotential lines become dense, which may cause breakdown voltage reduction. In the present invention, in power type semiconductor active elements such as power MOSFETs, a ring-shaped field plate is disposed in chip peripheral regions around an active cell region, etc., assuming a nearly rectangular shape. The field plate has an ohmic-contact part in at least a part of the portion along the side of the rectangle. However, in the portion corresponding to the corner part of the rectangle, an ohmic-contact part is not disposed.

Abstract: A semiconductor device includes a stripe-shaped gate trench formed in one major surface of n-type drift layer, a gate trench including gate polysilicon formed therein, and a gate polysilicon connected to a gate electrode. A p-type base layer is formed selectively in mesa region between adjacent gate trenches and a p-type base layer including an n-type emitter layer and connected to emitter electrode. One or more dummy trenches are formed between p-type base layers adjoining to each other in the extending direction of gate trenches. An electrically conductive dummy polysilicon is formed on an inner side wall of dummy trench with a gate oxide film interposed between the dummy polysilicon and dummy trench. The dummy polysilicon is spaced apart from the gate polysilicon and may be connected to the emitter electrode.

Abstract: A photodetector is provided, comprising: a radiation-absorbing semiconductor region and a collection semiconductor region separated by and each in contact with a barrier semiconductor region; wherein, at least in the absence of an applied bias voltage, the band gap between the valence band energy and the conduction band energy of the barrier semiconductor region is offset from the band gap between the valence band energy and the conduction band energy of the radiation-absorbing semiconductor region so as to form an energy barrier between the radiation-absorbing semiconductor region and the collection semiconductor region which resists the flow of minority carriers from the radiation-absorbing semiconductor region to the collection semiconductor region. Also provided is a method of manufacturing a photodetector.

Abstract: Provided is a Si—Ge laminated thin film including at least one Si layer and at least one Ge layer, which are alternately laminated on a substrate (1). A Si layer (31) and a Ge layer (22) each have a thickness in a range of 5 to 500 nm. The Si layer (31) is amorphous and only the Ge layer (22) is crystallized. An average crystallite size of Ge in the Ge layer (22) is 20 nm or less.

Abstract: This invention relates to a semiconductor device and a manufacturing method therefor for reducing stacking faults caused by high content of Ge in an embedded SiGe structure. The semiconductor device comprises a Si substrate with a recess formed therein. A SiGe seed layer is formed on sidewalls of the recess, and a first SiGe layer having a Ge content gradually increased from bottom to top is formed on the recess bottom. A second SiGe layer having a constant content of Ge is formed on the first SiGe layer. The thickness of the first SiGe layer is less than the depth of the recess. The Ge content in the SiGe seed layer is less than the Ge content in the second SiGe layer, and the Ge content at the upper surface of the first SiGe layer is less than or equal to the Ge content in the second SiGe layer.

Abstract: Structures and methods for producing active layer stacks of lattice matched, lattice mismatched and thermally mismatched semiconductor materials, with low threading dislocation densities, no layer cracking and minimized wafer bowing, by using epitaxial growth onto elevated substrate regions in a mask-less process.

Abstract: This invention relates to a semiconductor device and a manufacturing method thereof for reducing stacking faults caused by high content of Ge in an embedded SiGe structure. The semiconductor device comprises a Si substrate with a recess formed therein. A first SiGe layer having a Ge content gradually increased from bottom to top is formed on the recess bottom, a SiGe seed layer is formed on sidewalls of the recess and a second SiGe layer having a constant content of Ge is formed on the first SiGe layer. The thickness of the first SiGe layer is less than the depth of the recess. The Ge content in the SiGe seed layer is less than the Ge content in the second SiGe layer and the Ge content at the upper surface of the first SiGe layer is less than or equal to the Ge content in the second SiGe layer.

Abstract: A semiconductor device and a method for programming the same are provided. The semiconductor device comprises: a semiconductor substrate with an interconnect formed therein; a Through-Silicon Via (TSV) penetrating through the semiconductor substrate; and a programmable device which can be switched between on and off states, the TSV being connected to the interconnect by the programmable device. The present invention is beneficial in improving flexibility of TSV application.

Abstract: A 3-D memory is provided. Each word line layer has word lines and gaps alternately arranged along a first direction. Gaps include first group and second group of gaps alternately arranged. A first bit line layer is on word line layers and has first bit lines along a second direction. A first conductive pillar array through word line layers connects the first bit line layer and includes first conductive pillars in first group of gaps. A first memory element is between a first conductive pillar and an adjacent word line. A second bit line layer is below word line layers and has second bit lines along the second direction. A second conductive pillar array through word line layers connects the second bit line layer and includes second conductive pillars in second group of gaps. A second memory element is between a second conductive pillar and an adjacent word line.

Abstract: An image sensor for a semiconductor light-sensitive device including a semiconductor substrate and a light receiving device configured to receive light and generate a signal from the light. The image sensor may include an electron collecting device formed in the semiconductor substrate to receive at least a portion of the electrons generated by the light in the light receiving device. The image sensor may include a first type device isolation film configured to isolate the light receiving device from the electron collecting device. The image sensor may include a shielding film formed over the semiconductor substrate and configured to shield the first electron collecting device from the light.

Abstract: According to one embodiment, a magnetic random access memory includes a plurality of magnetoresistance elements. The plurality of magnetoresistance elements each include a recording layer having magnetic anisotropy perpendicular to a film surface, and a variable magnetization direction, a reference layer having magnetic anisotropy perpendicular to a film surface, and an invariable magnetization direction, and a first nonmagnetic layer formed between the recording layer and the reference layer. The recording layer is physically separated for each of the plurality of magnetoresistance elements. The reference layer and the first nonmagnetic layer continuously extend over the plurality of magnetoresistance elements.

Abstract: The embodiments of methods and structures are for doping fin structures by plasma doping processes to enable formation of shallow lightly doped source and drain (LDD) regions. The methods involve a two-step plasma doping process. The first step plasma process uses a heavy carrier gas, such as a carrier gas with an atomic weight equal to or greater than about 20 amu, to make the surfaces of fin structures amorphous and to reduce the dependence of doping rate on crystalline orientation. The second step plasma process uses a lighter carrier gas, which is lighter than the carrier gas for the first step plasma process, to drive the dopants deeper into the fin structures. The two-step plasma doping process produces uniform dopant profile beneath the outer surfaces of the fin structures.

Abstract: Cross-coupling between a gate conductor and an active region of a semiconductor substrate is provided by forming a gate dielectric layer on the semiconductor substrate and lithographically patterning the gate dielectric layer to form opening therein over a portion of the active region at which electrical contact with the gate conductor is desired. After implanting electrical dopants, a gate conductor layer is deposited and patterned. A remaining portion of the gate conductor layer includes an integral conductor structure, which includes a first portion overlying a gate dielectric over an active region and a second portion contacting the semiconductor material of the same active region or a different active region. The gate dielectric layer can be deposited within gate cavities in planarization dielectric material layer in a replacement gate scheme, or can be deposited on planar surfaces of active regions and/or shallow trench isolation structures in a gate first processing scheme.

Abstract: A semiconductor structure which includes a semiconductor substrate and a metal gate structure formed in a trench or via on the semiconductor substrate. The metal gate structure includes a gate dielectric; a wetting layer selected from the group consisting of cobalt and nickel on the gate dielectric lining the trench or via and having an oxygen content of no more than about 200 ppm (parts per million) oxygen; and an aluminum layer to fill the remainder of the trench or via. There is also disclosed a method of forming a semiconductor structure in which a wetting layer is formed from cobalt amidinate or nickel amidinate deposited by a chemical vapor deposition process.

Abstract: A method for forming a semiconductor device includes providing a substrate and depositing a gate stack having a side periphery on the substrate. A first liner dielectric layer is deposited on the substrate and the gate stack. A first spacer dielectric layer is deposited on the first liner dielectric layer. The first spacer dielectric layer is selectively etched such that the first spacer dielectric layer remains adjacent at least a portion of the side periphery of the gate stack. A first resist mask is disposed on a first portion of the first spacer dielectric layer such that the first portion of the first spacer dielectric layer is protected by the resist mask and a second portion of the first spacer dielectric layer is not protected by the resist mask. The first spacer dielectric layer is etched such that the second portion is removed and the first portion remains.

Abstract: According to one embodiment, a semiconductor device includes a substrate, a gate electrode, a channel region, a source region and a drain region. The source region forms a first boundary with the channel region, and the drain region forms a second boundary with the channel region. A side of the gate electrode at the side of the source region has a plurality of convex portions extending along a gate length direction, a side of the gate electrode at the side of the drain region is parallel to a gate width direction, the first boundary and the second boundary have shapes corresponding to the side of the gate electrode at the side of the source region and the side of the gate electrode at the side of the drain region, and the length of the first boundary is more than the length of the second boundary.

Abstract: A semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer formed over the first nitride semiconductor layer; and a gate electrode facing the second nitride semiconductor layer via a gate insulating film. Because the second nitride semiconductor layer is formed by stacking plural semiconductor layers with their Al composition ratios different from each other, the Al composition ratio of the second nitride semiconductor layer changes stepwise. The semiconductor layers forming the second nitride semiconductor layer are polarized in the same direction so that, among the semiconductor layers, a semiconductor layer nearer to the gate electrode has higher (or lower) intensity of polarization.

Abstract: According to one embodiment, a manufacturing method of a semiconductor device includes a step of forming a dummy-fin semiconductor on a semiconductor substrate; a step of forming an insulating layer, into which a lower part of the dummy-fin semiconductor is buried, on the semiconductor substrate; a step of forming a fin semiconductor, which is bonded to a side face at an upper part of the dummy-fin semiconductor, on the insulating layer; and a step of removing the dummy-fin semiconductor on the insulating layer with the fin semiconductor being left on the insulating layer.

Abstract: Disclosed is a manufacturing method for a semiconductor device that prevents excessive etching of a conductive layer, even if the section where a conductive layer contact hole is formed is etched a plurality of times. A light-shielding film 20 is formed on a substrate 30. A buffer film 21, a gate insulating film 22, and a silicon film 11 are formed on the substrate 30 and the light-shielding film 20. A cleared section 40 is formed by etching to remove a section of the buffer film 21 and the gate insulating film 22, the section being on the light-shielding film 20 and disposed outside the area in which the silicon film 11 is formed. A gate electrode film 33 is formed in the cleared section 40. An inter-layer insulating film 23 is formed above the substrate 30. Etching is used to simultaneously form contact holes 45 and 46 extending to the silicon film 11 and a contact hole 44 extending to the light-shielding film 20 in the cleared section 40.

Abstract: An integrated circuit device includes a plurality of fins on an upper surface of a semiconductor substrate and extending in a first direction, a device isolation insulating film placed between the fins, a gate electrode extending in a second direction crossing the first direction on the insulating film; and an insulating film insulating the fin from the gate electrode. In a first region where a plurality of the fins are consecutively arranged, an upper surface of the device isolation insulating film is located at a first position below an upper end of the fin. In a second region located in the second direction as viewed from the first region, the upper surface of the device isolation insulating film is located at a second position above the upper end of the fin. In the second region, the device isolation insulating film covers entirely a side surface of the fin.

Abstract: Disclosed is a non-volatile, ferroelectric random access memory (F-RAM) device and a method for fabricating a damascene self-aligned F-RAM that allows for the formation of a ferroelectric capacitor with separated PZT layers aligned with a preexisting, three dimensional (3-D) transistor structure.