Abstract: In a semiconductor device, at least one of the ratio (collector contact area/collector active area) in the High Side IGBT and the ratio (contact area on p+ region/p30 region area) is higher than the ratio in the Low Side IGBT. Thus, it is possible to develop without substantial changes and reduce the development burden.

Abstract: A dichromatic photodiode and method for dichromatic photodetection are disclosed. A wide bandgap junction comprises a lattice matched junction operable to detect a first light spectrum. A narrow bandgap junction is coupled to the wide bandgap junction, and comprises a photodiode structure. The narrow bandgap junction is operable to detect a second light spectrum.

Abstract: A semiconductor device includes: a channel layer made of a compound semiconductor; a barrier layer provided above the channel layer and made of a compound semiconductor in which an energy band on a carrier travel side in a junction with respect to the channel layer is farther from an intrinsic Fermi level in the channel layer than in the channel layer; a low-resistance region provided in a surface layer of the barrier layer, in which resistance is kept lower than portions around by containing impurity; a source electrode and a drain electrode connected to the barrier layer at positions sandwiching the low-resistance region; a gate insulating layer provided on the low-resistance region; and a gate electrode provided above the low-resistance region through the gate insulating layer.

Abstract: A method for producing a monolithic template comprises a Si wafer with a layer of a III/V semiconductor epitaxially applied to its surface. The III/V semiconductor has a lattice constant differing by less than 10% from that of Si. The method includes epitaxially growing a layer of a III/V semiconductor on the surface of the Si wafer at a wafer temperature from 350 to 650° C., a growth rate from 0.1 to 2 ?m/h, and a layer thickness from 1 to 100 nm. A layer of another III/V semiconductor, identical to or different from the previously applied III/V semiconductor, is epitaxially grown on the III/V semiconductor layer at a wafer temperature from 500 to 800° C., a growth rate from 0.1 to 10 ?m/h, and a layer thickness from 10 to 150 nm.

Abstract: A compound semiconductor device includes a substrate; and a compound semiconductor layer disposed over the substrate, wherein the compound semiconductor layer includes a first region having first conductivity-type carriers generated by activating a first impurity and also includes a second region having carriers at lower concentration as compared to the first region, the carriers being generated by activating a second impurity which is the same type as the first impurity.

Abstract: An embodiment of the present invention concerns a layered epitaxial structure for enhancement/depletion PHEMT devices, an enhancement/depletion PHEMT device and a method for manufacturing an enhancement/depletion PHEMT device that finds advantageous, but not exclusive, application in the manufacturing of integrated circuits operating at millimetre-wave and microwave frequencies.

Abstract: Heterojunction bipolar transistors with reduced base resistance, as well as fabrication methods for heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The heterojunction bipolar transistor includes a conductive layer between the intrinsic base and the extrinsic base. The conductive layer is comprised of a conductive material, such as a silicide, having a lower resistivity than the materials forming the intrinsic base and the extrinsic base.

Abstract: Improved silicide formation and associated devices are disclosed. An exemplary method includes providing a semiconductor material having spaced source and drain regions therein, forming a gate structure interposed between the source and drain regions, performing a gate replacement process on the gate structure to form a metal gate electrode therein, forming a hard mask layer over the metal gate electrode, forming silicide layers on the respective source and drain regions in the semiconductor material, removing the hard mask layer to expose the metal gate electrode, and forming source and drain contacts, each source and drain contact being conductively coupled to a respective one of the silicide layers.

Abstract: An engineered epitaxial region compensates for short channel effects of a MOS device by providing a blocking layer to reduce or prevent dopant diffusion while at the same time reducing or eliminating the side effects of the blocking layer such as increased leakage current of a BJT device and/or decreased breakdown voltage of a rectifier. These side effects are reduced or eliminated by a non-conformal dopant-rich layer between the blocking layer and the substrate, which lessens the abruptness of the junction, thus lower the electric field at the junction region. Such a scheme is particularly advantageous for system on chip applications where it is desirable to manufacture MOS, BJT, and rectifier devices simultaneously with common process steps.

Abstract: A nitride semiconductor device includes a first semiconductor layer, a second semiconductor layer, a conductive substrate, a first electrode, a second electrode, and a control electrode. The second semiconductor layer is directly bonded to the first semiconductor layer. The conductive substrate is provided on and electrically connected to the first semiconductor layer. The first electrode and the second electrode are provided on and electrically connected to a surface of the second semiconductor layer on a side opposite to the first semiconductor layer. The control electrode is provided on the surface of the second semiconductor layer between the first electrode and the second electrode. The first electrode is electrically connected to a drain electrode of a MOSFET formed of Si. The control electrode is electrically connected to a source electrode of the MOSFET. The conductive substrate is electrically connected to a gate electrode of the MOSFET.

Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: a semiconductor layer comprising a plurality of semiconductor sub-layers; and a plurality of fins formed in the semiconductor layer and adjoining the semiconductor layer, wherein at least two of the plurality of fins comprise different numbers of the semiconductor sub-layers and have different heights. According to the present disclosure, a plurality of semiconductor devices with different dimensions and different driving abilities can be integrated on a single wafer.

Abstract: In a solid-state imaging device, a pixel has a first island-shaped semiconductor (P11) formed on a substrate (1) and a drive output circuit has second island-shaped semiconductors (4a to 4c) formed on the substrate at the same height as that of the first island-shaped semiconductor (P11). The first island-shaped semiconductor (P11) has a first gate insulating layer (6b) formed on an outer periphery thereof and a first gate conductor layer (105a) surrounding the first gate insulating layer (6b). The second island-shaped semiconductors (4a to 4c) have a second gate insulating layer (6a) formed on an outer periphery thereof and a second gate conductor layer (7a) surrounding the second gate insulating layer (6a). The first gate conductor layer (105a) and the second gate conductor layer (7a) have bottom portions located on the same plane.

Abstract: A spin transfer torque random access memory includes a substance unit, a source line unit, an insulation unit, a transistor unit, a MTJ unit, and a bit line unit. The substance unit includes a substance layer. The source line unit includes a plurality of source lines formed inside the substance layer. The transistor unit includes a plurality of transistors respectively disposed on the source lines. Each transistor includes a source region formed on each corresponding source line, a drain region formed above the source region, a channel region formed between the source region and the drain region, and a surrounding gate region surrounding the source region, the drain region, and the channel region. The MTJ unit includes a plurality of MTJ structures respectively disposed on the transistors. The bit line unit includes at least one bit line disposed on the MTJ unit.

Abstract: In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In a preferred embodiment, an oxide layer and a nitride layer are used as masks to define trenches, pillars, and active areas in a substrate. Preferably, two substrate etch processes use the masks to form three levels of bulk silicon.

Abstract: A flash memory structure includes a semiconductor substrate, a gate dielectric layer on the semiconductor substrate, a floating gate on the gate dielectric layer, a capacitor dielectric layer conformally covering the floating gate, wherein the capacitor dielectric layer forms a top surface and four sidewall surfaces; and an isolated conductive cap layer covering the top surface and the four sidewall surfaces.

Abstract: A memory device, and a method of forming a memory device, is provided that includes a capacitor with a lower electrode of a metal semiconductor alloy. In one embodiment, the memory device includes a trench present in a semiconductor substrate including a semiconductor on insulating (SOI) layer on top of a buried dielectric layer, wherein the buried dielectric layer is on top of a base semiconductor layer. A capacitor is present in the trench, wherein the capacitor includes a lower electrode of a metal semiconductor alloy having an upper edge that is self-aligned to the upper surface of the base semiconductor layer, a high-k dielectric node layer, and an upper electrode of a metal. The memory device further includes a pass transistor in electrical communication with the capacitor.

Abstract: Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess may be extended to a second depth that is greater that the first depth to form an extended portion of the device recess. A field oxide layer may be provided within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate. Active regions may be formed in the substrate that abut the field oxide layer, and a gate material may be deposited into the device recess.

Abstract: A device includes a semiconductor region surrounded with the isolation region and includes a first active region, a channel region and a second active region arranged in that order in a first direction. A first side portion of the first active region and a second side portion of the second active region faces each other across a top surface of the channel region in the first direction. A gate electrode covers the top surface and the first and second side portions and extends in a second direction that intersects the first direction. A first diffusion layer is formed in the first active region. A second diffusion layer is formed in the second active region. An embedded contact plug is formed in the first active region and extends downwardly from the upper surface of the semiconductor region and contacts with the first diffusion layer.

Abstract: According to one embodiment, a semiconductor memory includes a memory cell in a memory cell array which is provided in a semiconductor substrate and which includes a first active region surrounded by a first isolation insulator, a transistor in a transistor region which is provided in the semiconductor substrate and which includes second active regions surrounded by a second isolation insulator. The second isolation insulator includes a first film, and a second film between the first film and the second active region, and the upper surface of the first film is located closer to the bottom of the semiconductor substrate than the upper surface of the second film.

Abstract: According to one embodiment, a semiconductor memory device includes a stacked body, a semiconductor pillar, an insulating film, and a charge storage film. The stacked body includes a plurality of electrode films stacked with an inter-layer insulating film provided between the electrode films. The semiconductor pillar pierces the stacked body. The insulating film is provided between the semiconductor pillar and the electrode films on an outer side of the semiconductor pillar with a gap interposed. The charge storage film is provided between the insulating film and the electrode films. The semiconductor pillar includes germanium. An upper end portion of the semiconductor pillar is supported by an interconnect provided above the stacked body.

Abstract: According to one embodiment, a semiconductor memory includes a memory cell provided in a first active area surrounded with a first isolation insulating film, a first transistor provided in a second active area surrounded with a second isolation insulating film, a shield gate electrode on the second isolation insulating film. The bottom surface of the shield gate electrode is positioned more closely to a semiconductor substrate side as compared with the highest upper surface of the second isolation insulating film.

Abstract: According to one embodiment, a method of manufacturing a semiconductor memory device is provided. In the method, a laminated body in which a first silicon layer, a first sacrificial layer, a second silicon layer, and a second sacrificial layer are laminated in turn is formed. A first insulating film is formed on the laminated body. A trench is formed in the laminated body and the first insulating film. A third sacrificial layer is formed into the trench. The third sacrificial layer is etched by wet etching to be retreated from a top surface of the third sacrificial layer, thereby etching end faces of the first sacrificial layer and the second sacrificial layer.

Abstract: The invention relates to a gate stack structure suitable for use in a semiconductor flash memory device and its fabricating method. The gate stack structure is fabricated on a p-type 100 silicon substrate, which also includes the following components in sequence from bottom to top: a charge tunnel layer of Al2O3 film, the first charge trapping layer of RuOx nanocrystals; the second charge trapping layer of high-k HxAlyOz film, a charge blocking layer of Al2O3 film, and a top electrode. In this invention, the RuOx nanocrystals have excellent thermal stability, and do not diffuse easily at high temperatures. The high-k HfxAlyOz film has high density charge traps.Pd with a high work function is used as the top electrode. Therefore, the present gate stack structure has vast practical prospects for nanocrystal memory devices.

Abstract: According to one embodiment, a control gate is formed on the semiconductor substrate and includes a cylindrical through hole. A block insulating film, a charge storage film, a tunnel insulating film, and a semiconductor layer are formed on a side surface of the control gate inside the through hole. The tunnel insulating film comprises a first insulating film having SiO2 as a base material and containing an element that lowers a band gap of the base material by being added. A density and a density gradient of the element monotonously increase from the semiconductor layer toward the charge storage film.

Abstract: There is provided a non-volatile semiconductor memory having a charge accumulation layer of a configuration where a metal oxide with a dielectric constant sufficiently higher than a silicon nitride, e.g., a Ti oxide, a Zr oxide, or a Hf oxide, is used as a base material and an appropriate amount of a high-valence substance whose valence is increased two levels or more (a VI-valence) is added to produce a trap level that enables entrance and exit of electrons with respect to the base material.

Abstract: An SRAM cell and a method of forming an SRAM cell. The SRAM cell includes a first pass gate field effect transistor (FET) and a first pull-down FET sharing a first common source/drain (S/D) and a first pull-up FET having first and second S/Ds; a second pass gate FET and a second pull-down FET sharing a second common S/D and a second pull-up FET having first and second S/Ds; a first gate electrode common to the first pull-down FET and the first pull-up FET and physically and electrically contacting the first S/D of the first pull-up FET; a second gate electrode of the first pull-up FET; a third gate electrode common to the second pull-down FET and the second pull-up FET and physically and electrically contacting the first S/D of the second pull-up FET; and a fourth gate electrode of the first pull-up FET.

Abstract: According to an embodiment, a semiconductor device includes a semiconductor layer, a first semiconductor region provided on the semiconductor layer, a second semiconductor region, a first control electrode and a second control electrode. The first control electrode faces the first and second semiconductor regions through an insulating film in a trench, the trench piercing through the first semiconductor region, the trench having a bottom face at a position deeper than the first semiconductor region. The second control electrode extends to the bottom face of the trench and has a portion between the bottom face and the first control electrode. The semiconductor layer includes a first portion between an end of the first semiconductor region and an end of the second control electrode, a first conductive type carrier concentration in the first portion being lower than a first conductive type carrier concentration in other portions in the semiconductor layer.

Abstract: A semiconductor device includes a semiconductor layer of a second conductive type, a first diffused region of a first conductive type formed in the semiconductor layer, a second diffused region of the second conductive type selectively formed in the first diffused region, a trench formed in the semiconductor layer, a gate electrode housed in the trench with a gate insulator intervening, a top surface of the gate electrode being lower than a top surface of the second diffused region, a first oxide film housed in the trench and formed over the gate electrode, a second oxide film housed in the trench and formed over the first oxide film, a third oxide film housed in the trench and formed over the second oxide film, and a source electrode formed over the third oxide film and electrically connecting to the first and second diffused regions.

Abstract: A semiconductor device has a source region, channel region, and drain region disposed in order from the surface of the device in the thickness direction of a semiconductor substrate. The device includes a source metal embedded in a source contact groove penetrating the source region and reaching the channel region, a gate insulating film formed on the side wall of a gate trench that is formed to penetrate the source region and channel and reach the drain region, a polysilicon gate embedded in trench so that at least a region facing the channel region in the insulating film is covered with the gate and so that the entire gate is placed under a surface of the source region, and a gate metal that is embedded in a gate contact groove formed in the gate so as to reach the depth of the channel region and in contact with the gate.

Abstract: A device comprising a p-type base region, and a p-type region formed over the p-type base region and in contact with the p-type base region is disclosed. The device also includes an n-well region surrounded by the p-type region, wherein the n-well is formed from an n-type epitaxial layer and the p-type region is formed by counter-doping the same n-type epitaxial layer.

Abstract: According to one embodiment, a half-FinFET semiconductor device comprises a gate structure formed over a semiconductor body. The semiconductor body includes a source region comprised of a plurality of fins extending beyond a first side of the gate structure and a continuous drain region adjacent a second side of the gate structure opposite the plurality of fins. The continuous drain region causes the half-FinFET semiconductor device to have a reduced ON-resistance. A method for fabricating a semiconductor device having a half-FinFET structure comprises designating source and drain regions in a semiconductor body, etching the source region to produce a plurality of source fins while masking the drain region during the etching to provide a continuous drain region, thereby resulting in the half-FinFET structure having a reduced ON-resistance.

Abstract: A semiconductor device which provides compactness and enhanced drain withstand voltage. The semiconductor device includes: a gate electrode; a source electrode spaced from the gate electrode; a drain electrode located opposite to the source electrode with respect to the gate electrode in a plan view and spaced from the gate electrode; at least one field plate electrode located between the gate and drain electrodes in a plan view, provided over the semiconductor substrate through an insulating film and spaced from the gate electrode, source electrode and drain electrode; and at least one field plate contact provided in the insulating film, coupling the field plate electrode to the semiconductor substrate. The field plate electrode extends from the field plate contact at least either toward the source electrode or toward the drain electrode in a plan view.

Abstract: A semiconductor device includes: a semiconductor substrate having a first conductivity type; a well having a second conductivity type and provided inside the semiconductor substrate; a first impurity region having the first conductivity type and provided within the well; a second impurity region having the second conductivity type, provided inside the well and away from the first impurity region; and a third impurity region having a first conductivity type, provided surrounding the well and away from the second impurity region. In this semiconductor device, the well is formed to be deeper than the first impurity region, the second impurity region, and the third impurity region, in a thickness direction of the semiconductor substrate; and a minimum distance between the first impurity region and the second impurity region is smaller than a minimum distance between the second impurity region and the third impurity region.

Abstract: A semiconductor device and manufacturing method for the same are disclosed. The method includes providing a substrate that has an insulator layer and a semiconductor layer overlying the insulator layer. The method further includes forming a hard mask layer pattern on the semiconductor layer and etching the semiconductor layer using the patterned hard mask layer to form portions having different thickness in the semiconductor layer. The method also includes performing an oxygen-based treatment on the semiconductor layer to form a supporting oxide layer. A portion of the semiconductor layer is buried in the supporting oxide layer.

Abstract: The present invention provides an SOI semiconductor structure with a hybrid of coplanar germanium (Ge) and III-V, and a method for preparing the same. A heterogeneous integrated semiconductor structure with a hybrid of Ge and the group III-V semiconductor material coplanar on an insulator includes at least one Ge substrate formed on the insulating layer, and the other substrate is a group III-V semiconductor material formed on the Ge semiconductor.

Abstract: A semiconductor device capable of dissipating heat, which has been produced in an ESD protection element, to the exterior of the device rapidly and efficiently includes an ESD protection element having a drain region, a source region and a gate electrode, and a thermal diffusion portion. The thermal diffusion portion, which has been formed on the drain region, has a metal layer electrically connected to a pad, and contacts connecting the drain region and metal layer. The metal layer has a first wiring trace extending along the gate electrode, and second wiring traces intersecting the first wiring trace perpendicularly. The contacts are connected to intersections between the first wiring trace and the second wiring traces. Heat that has been produced at a pn-junction of the ESD protection element and transferred through a contact is diffused simultaneously in three directions through the first wiring trace and second wiring trace in the metal layer and is released into the pad.

Abstract: An electronic device can include a nonvolatile memory cell, wherein the nonvolatile memory cell can include an access transistor, a read transistor, and an antifuse component coupled to the access transistor and the read transistor. In an embodiment, the read transistor can include a gate electrode, and the antifuse component can include a first electrode and a second electrode overlying the first electrode. The gate electrode and the first electrode can be parts of the same gate member. In another embodiment, the access transistor can include a gate electrode, and the antifuse component can include a first electrode, an antifuse dielectric layer, and a second electrode. The electronic device can further include a conductive member overlying the antifuse dielectric layer and the gate electrode of the access transistor, wherein the conductive member is configured to electrically float. Processes for making the same are also disclosed.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed. In one embodiment, the semiconductor device may comprise a semiconductor layer, a fin formed by patterning the semiconductor layer, and a gate stack crossing over the fin. The fin may comprise a doped block region at the bottom portion thereof. According to the embodiment, it is possible to effectively suppress current leakage at the bottom portion of the fin by the block region.

Abstract: A semiconductor device according to the present invention has an n-type MIS transistor. The n-type MIS transistor has a first active region surrounded by a device isolation region in a semiconductor substrate, a first gate insulating film having a first high-dielectric-constant insulating film containing a first metal for adjustment, and a first electrode formed on the first gate insulating film. A protrusion amount of one end of the first high-dielectric-constant insulating film on the first device isolation part is smaller than a protrusion amount of an end of the first gate electrode above the first device isolation part.

Abstract: A manufacturing method of a semiconductor device includes the following steps. First, a substrate is provided. At least one sacrificial gate structure is formed on the substrate, at least one diffusion region is formed in the substrate at each of two sides of the sacrificial gate structure, and a first inter-layer dielectric layer is formed to cover the diffusion region. A gate recess is then formed in the sacrificial gate structure. A first diffusion contact hole is then formed in the first inter-layer dielectric layer and at least partially exposes the diffusion region. A metal layer is subsequently formed in the gate recess and the first diffusion contact hole.

Abstract: A method of forming a complementary metal oxide semiconductor (CMOS) structure having multiple threshold voltage devices includes forming a first transistor device and a second transistor device on a semiconductor substrate. The first transistor device and second transistor device initially have sacrificial dummy gate structures. The sacrificial dummy gate structures are removed and a set of vertical oxide spacers are selectively formed for the first transistor device. The set of vertical oxide spacers are in direct contact with a gate dielectric layer of the first transistor device such that the first transistor device has a shifted threshold voltage with respect to the second transistor device.

Abstract: An electronic device can include a nonvolatile memory cell, wherein the nonvolatile memory cell can include a substrate, an access transistor, a read transistor, and an antifuse component. Each of the access and read transistors can include source/drain regions at least partly within the substrate, a gate dielectric layer overlying the substrate, and a gate electrode overlying the gate dielectric layer. An antifuse component can include a first electrode lying at least partly within the substrate, an antifuse dielectric layer overlying the substrate, and a second electrode overlying the antifuse dielectric layer. The second electrode of the antifuse component can be coupled to one of the source/drain regions of the access transistor and to the gate electrode of the read transistor. In an embodiment, the antifuse component can be in the form of a transistor structure. The electronic device can be formed using a single polysilicon process.

Abstract: A complementary metal oxide semiconductor (CMOS) structure having multiple threshold voltage devices includes a first transistor device and a second transistor device formed on a semiconductor substrate. A set of vertical oxide spacers selectively formed for the first transistor device are in direct contact with a gate dielectric layer of the first transistor device such that the first transistor device has a shifted threshold voltage with respect to the second transistor device.

Abstract: In a semiconductor device, a gate electrode having a uniform composition prevents deviation in a work function. Controlling a Vth provides excellent operation properties. The semiconductor device includes an NMOS transistor and a PMOS transistor with a common line electrode. The line electrode includes electrode sections (A) and (B) and a diffusion barrier region formed over an isolation region so that (A) and (B) are kept out of contact. The diffusion barrier region meets at least one of: (1) The diffusion coefficient in the above diffusion barrier region of the constituent element of the above electrode section (A) is lower than the interdiffusion coefficient of the constituent element between electrode section (A) materials; and (2) The diffusion coefficient in the above diffusion barrier region of the constituent element of the above electrode section (B) is lower than the interdiffusion coefficient of the constituent element between electrode section (B) materials.

Abstract: An electronic module includes a first semiconductor chip and a passive component, wherein the first semiconductor chip is arranged on a surface of the passive component.

Abstract: A dummy cell pattern includes a dummy diffusion pattern disposed within a predetermined region A; a trench isolation pattern encompassing the dummy diffusion pattern in the predetermined region A; a first dummy gate pattern disposed on the dummy diffusion pattern with two ends of the first dummy gate pattern extending above the trench isolation pattern, thereby forming overlapping areas C1 and C2; and a second dummy gate pattern directly on the trench isolation pattern forming an overlapping area C therebetween, wherein the combination of C1, C2 and C is about 5%-20% of the predetermined region A.

Abstract: A semiconductor device structure, a method for manufacturing the same, and a method for manufacturing a semiconductor fin are disclosed. In one embodiment, the method for manufacturing the semiconductor device structure comprises: forming a fin in a first direction on a semiconductor substrate; forming a gate line in a second direction, the second direction crossing the first direction on the semiconductor substrate, and the gate line intersecting the fin with a gate dielectric layer sandwiched between the gate line and the fin; forming a dielectric spacer surrounding the gate line; and performing inter-device electrical isolation at a predetermined position, wherein isolated portions of the gate line form independent gate electrodes of respective devices.

Abstract: Disposable gate structures are formed on a semiconductor substrate. A planarization dielectric layer is deposited over the disposable gate structures and planarized to provide a top surface that is coplanar with top surface of the disposable gate structures. The planarization dielectric layer at this point includes gap-fill keyholes between narrowly spaced disposable gate structures. A printable dielectric layer is deposited over the planarization dielectric layer to fill the gap-fill keyholes. Areas of the printable dielectric layer over the gap-fill keyholes are illuminated with radiation that cross-links cross-linkable bonds in the material of the printable dielectric layer. Non-crosslinked portions of the printable dielectric layer are subsequently removed selective to crosslinked portions of the printable dielectric layer, which fills at least the upper portion of each gate-fill keyhole. The disposable gate structures are removed to form gate cavities.

Abstract: A micro electrical mechanical system includes a membrane structure and a backplate structure. The backplate structure includes a backplate material and at least one pre-tensioning element mechanically connected to the backplate material. The at least one pre-tensioning element causes a mechanical tension on the backplate material for a bending deflection of the backplate structure in a direction away from the membrane structure.

Abstract: A semiconductor-centered MEMS device (100) integrates the movable microelectromechanical parts, such as mechanical elements, flexible membranes, and sensors, with the low-cost device package, and leaving only the electronics and signal-processing parts in the integrated circuitry of the semiconductor chip. The package is substrate-based and has an opening through the thickness of the substrate. Substrate materials include polymer tapes with attached metal foil, and polymer-based and ceramic-based multi-metal-layer dielectric composites with attached metal foil. The movable part is formed from the metal foil attached to a substrate surface and extends at least partially across the opening. The chip is flip-assembled to span at least partially across the membrane, and is separated from the membrane by a gap.