Abstract: According to one embodiment, provided is a semiconductor device including a lower layer wiring, and an upper layer wiring that is drawn in the same direction as a direction in which the lower layer wiring is drawn. Intermediate wirings include at least a first intermediate wiring and a second intermediate wiring. Conductors include at least a plurality of first conductors connecting between the lower layer wiring and the first intermediate wiring, a plurality of second conductors connecting between the upper layer wiring and the second intermediate wiring, and a plurality of third conductors which connect between the first intermediate wiring and the second intermediate wiring, and are less in number than the first conductors or the second conductors on a drawn side of the lower layer wiring and the upper layer wiring.

Abstract: The present invention discloses a through silicon via and method of manufacturing the same comprising the steps of providing a substrate, forming a plurality of through silicon via (TSV) holes in said substrate, forming a seed layer on the surface of said substrate and said a plurality of TSV holes, forming a patterned mask on said substrate, wherein said patterned mask comprises a plurality of first openings corresponding to said TSV holes and a plurality of second openings adjacent to or surrounding said a plurality of first openings, forming a material layer on said substrate, wherein said material layer is filled into said TSV holes and said first openings to form a plurality of through silicon vias, and said material layer is filled into said second openings to form a plurality of dummy bumps.

Abstract: A package component includes a metal trace on a top surface of the package component, and an anchor via underlying and in contact with the metal trace. The anchor via is configured not to conduct currents flowing through the metal trace.

Abstract: A device includes a substrate having a front side and a backside, a through-via extending from the backside to the front side of the substrate, and a conductive pad on the backside of the substrate and over the through-via. The conductive pad has a substantially planar top surface. A conductive bump has a non-planar top surface over the substantially planar top surface and aligned to the through-via. The conductive bump and the conductive pad are formed of a same material. No interface is formed between the conductive bump and the conductive pad.

Abstract: A semiconductor device has a semiconductor wafer with a first conductive layer formed over a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and first conductive layer. A second conductive layer is formed over the first insulating layer and first conductive layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A plurality of openings is formed in the second insulating layer in a bump formation area of the semiconductor wafer to expose the second conductive layer and reduce adverse effects of electro-migration. The openings are separated by portions of the second insulating layer. A UBM layer is formed over the openings in the second insulating layer in the bump formation area electrically connected to the second conductive layer. A bump is formed over the UBM layer.

Abstract: A wiring substrate includes an insulating layer having a first surface on which a projecting part is formed, and an electrode pad being formed on the projecting part and including a first electrode pad surface and a second electrode pad surface on a side opposite to the first electrode pad surface. The first electrode pad surface is exposed from the projecting part of the insulating layer. The second electrode pad surface is covered by the insulating layer. A cross-section of the projecting part is a tapered shape. One side of the cross-section toward the first electrode pad surface is narrower than another side of the cross-section toward the first surface of the insulating layer.

Abstract: A method for forming an integrated circuit including the steps of: a) forming openings in a front surface of a first semiconductor wafer, the depth of the openings being smaller than 10 ?m, and filling them with a conductive material; b) forming doped areas of components in active areas of the front surface, forming interconnection levels on the front surface and leveling the surface supporting the interconnection levels; c) covering with an insulating layer a front surface of a second semiconductor wafer, and leveling the surface coated with an insulator; d) applying the front surface of the second wafer coated with insulator on the front surface of the first wafer supporting interconnection levels, to obtain a bonding between the two wafers; e) forming vias from the rear surface of the second wafer, to reach the interconnection levels of the first wafer; and f) thinning the first wafer to reach the openings filled with conductive material.

Abstract: A flip chip package includes a substrate having a die attach surface; and a die mounted on the die attach surface with an active surface of the die facing the substrate, wherein the die is interconnected to the substrate via a plurality of copper pillar bumps on the active surface, wherein at least one of the plurality of copper pillar bumps has a bump width that is substantially equal to or smaller than a line width of a trace on the die attach surface of the substrate.

Abstract: Solder bump connections and methods for fabricating solder bump connections. The method includes forming a layer stack containing first and second conductive layers, forming a dielectric passivation layer on a top surface of the second conductive layer, and forming a via opening extending through the dielectric passivation layer to the top surface of the second conductive layer. The method further includes forming a conductive plug in the via opening. The solder bump connection includes first and second conductive layers comprised of different conductors, a dielectric passivation layer on a top surface of the second conductive layer, a via opening extending through the dielectric passivation layer to the top surface of the second conductive layer, and a conductive plug in the via opening.

Abstract: A semiconductor device includes a first substrate; a plurality of first electrodes formed on the first substrate; and a first insulating film formed on sidewalls of the plurality of first electrodes. The first insulating film is formed not to fill spaces between the plurality of first electrodes.

Abstract: Provided are electrode-connecting structures or semiconductor devices, including a lower device including a lower substrate, a lower insulating layer formed on the lower substrate, and a lower electrode structure formed in the lower insulating layer, wherein the lower electrode structure includes a lower electrode barrier layer and a lower metal electrode formed on the lower electrode barrier layer, and an upper device including an upper substrate, an upper insulating layer formed under the upper substrate, and an upper electrode structure formed in the upper insulating layer, wherein the upper electrode structure includes an upper electrode barrier layer extending from the inside of the upper insulating layer under a bottom surface thereof and an upper metal electrode formed on the upper electrode barrier layer. The lower metal electrode is in direct contact with the upper metal electrode.

Abstract: Described are doped TaN films, as well as methods for providing the doped TaN films. Doping TaN films with Ru, Cu, Co, Mn, Al, Mg, Cr, Nb, Ti and/or V allows for enhanced copper barrier properties of the TaN films. Also described are methods of providing films with a first layer comprising doped TaN and a second layer comprising one or more of Ru and Co, with optional doping of the second layer.

Abstract: A semiconductor device with a connection pad in a substrate, the connection pad having an exposed surface made of a metallic material that diffuses less readily into a dielectric layer than does a metal of a wiring layer connected thereto.

Abstract: Provided is a method of manufacturing a TSV structure, which prevents a substrate from warping even if it is made thin. A method of manufacturing a semiconductor device comprises integrating semiconductor elements on a surface of a semiconductor substrate to form at least a part of a circuit, forming holes from the surface of the semiconductor substrate, forming an insulating film and a barrier film on an inner surface of each hole, forming a conductive metal on a surface of the barrier film to fill each hole, processing a back surface of the semiconductor substrate to reduce the thickness thereof to thereby protrude the conductive metal, and providing a SiCN film on the back surface of the semiconductor substrate.

Abstract: A silver-containing solderable contact on a semiconductor die has its outer edge spaced from the confronting edge of an epoxy passivation layer so that, after soldering, silver ions are not present and are not therefor free to migrate under the epoxy layer to form dendrites.

Abstract: A fastening device is provided that includes a semiconductor body with an integrated circuit, and a dielectric passivation layer formed on the surface of the semiconductor body, and a trace formed underneath the passivation layer, and an oxide layer formed beneath the trace, and a connecting component that forms a frictional connection between a component formed above the passivation layer and the semiconductor body, wherein a formation passing through the passivation layer and the oxide layer and having a bottom surface is formed, and a conductive layer is formed on the bottom surface and the connecting component forms an electrical connection between the conductive layer and the component.

Abstract: Annular, linear, and point contact structures are described which exhibit a greatly reduced susceptibility to process deviations caused by lithographic and deposition variations than does a conventional circular contact plug. In one embodiment, a standard conductive material such as carbon or titanium nitride is used to form the contact. In an alternative embodiment, a memory material itself is used to form the contact. These contact structures may be made by various processes, including chemical mechanical planarization and facet etching.

Abstract: A capacitive micromachined ultrasonic transducer (CMUT), which has a conductive structure that can vibrate over a cavity, utilizes a thick oxide layer to substantially increase the volume of the cavity which, in turn, allows the CMUT to receive and transmit low frequency ultrasonic waves. In addition, the CMUT can include a back side bond pad structure that eliminates the need for and cost of one patterned photoresist layer.

Abstract: Aspects of the present invention are directed to circuits, circuit packages and related methods. In accordance with various example embodiments, respective electrodes are implemented to facilitate contact to a semiconductor device via different surfaces and/or sidewalls, as may be useful in connecting the device to an external package having a plurality of semiconductor devices in which same-surface connections to the devices are spatially restricted. The semiconductor device has opposing surfaces and sidewalls connecting the surfaces, and contacts to respective different regions in the device. Respective electrodes are coupled to the respective contacts and extend along/around the device to provide access to the contacts via different surfaces.

Abstract: A wafer level chip scale semiconductor device comprises a semiconductor die, a first under bump metal structure and a second under bump metal structure. The first under bump metal structure having a first enclosure is formed on a corner region or an edge region of the semiconductor die. A second under bump metal structure having a second enclosure is formed on an inner region of the semiconductor die. The first enclosure is greater than the second enclosure.

Abstract: A semiconductor device includes: a plurality of line features including at least one real feature which includes a gate electrode portion, and at least one dummy feature. Two of multiple ones of the dummy feature, and at least one of the line features interposed between the two dummy features and including the at least one real feature form parallel running line features which are evenly spaced. The parallel running line features have an identical width, and line end portions of the parallel running line features are substantially flush. Line end portion uniformization dummy features are formed on extensions of the line end portions of the parallel running line features. The line end portion uniformization dummy features include a plurality of linear features each having a same width as each of the line features and spaced at intervals equal to an interval between each adjacent pair of the line features.

Abstract: A method of fabricating a semiconductor device includes the following steps. A semiconductor substrate having a first side and a second side facing to the first side is provided. At least an opening is disposed in the semiconductor substrate of a protection region defined in the first side. A first material layer is formed on the first side and the second side, and the first material layer partially fills the opening. Subsequently, a part of the first material layer on the first side and outside the protection region is removed. A second material layer is formed on the first side and the second side, and the second material layer fills the opening. Then, a part of the second material layer on the first side and outside the protection region is removed. Finally, the remaining first material layer and the remaining second material layer on the first side are planarized.

Abstract: To provide a technique adopting a TSV technique, capable of improving manufacturing yield and reliability of semiconductor devices. By partitioning a connection pad-forming region into a plurality of regions and by forming, respectively, connection pads 17 having a relatively small planar area, spaced apart from an adjacent connection pad 17 in each of partitioned regions, dishing generated in the connection pad 17 is lightened. In addition, by not forming a through hole 23 for forming a through electrode 27 in an interlayer insulating film 9 covering a semiconductor element, intrusion of H2O, a metal ion such as Na+ or K+, etc. into an element-forming region from the through hole, via the interlayer insulating film is prevented.

Abstract: A semiconductor device includes a semiconductor chip having a wire and a passivation film formed on the outermost surface with an opening partially exposing the wire. A resin layer is stacked on the semiconductor chip and provided with a through-hole in a position opposed to a portion of the wire facing the opening. A pad is formed on a peripheral portion of the through-hole in the resin layer and in the through-hole so that an external connection terminal is arranged on the surface thereof. The peripheral portion of the resin layer is formed more thickly than the remaining portion of the resin layer other than the peripheral portion.

Abstract: A semiconductor device includes a stacked via structure including a plurality of first vias formed over a substrate, a first interconnect formed on the plurality of first vias, a plurality of second vias formed on the first interconnect, and a second interconnect formed on the plurality of second vias. One of the first vias closest to one end part of the first interconnect and one of the second vias closest to the one end part of the first interconnect at least partially overlap with each other as viewed in the plane, and the first interconnect has a first extension part extending from a position of an end of the first via toward the one end part of the first interconnect and having a length which is more than six times as long as a via width of the first via.

Abstract: The invention discloses an array substrate, an LCD device, and a method for manufacturing the array substrate. The array substrate comprises scan line(s) and data line(s); the width of data line at the junction of the data line and the scan line is more than the width of the rest part of the data line. The invention can improve the final passed yield of LCD devices on the premise of not adding additional processes, and has the advantages of simple technology and low cost.

Abstract: The present disclosure relates to a method for fast and precise alignment and mounting of a top die onto an interposer wafer. The method is performed by applying a hydrophobic self assembled monolayer to a carrier wafer in a pattern defining a top die placement region correlating to an arrangement of a top die on an interposer wafer. A liquid is provided into the top die placement region and a top die is placed into contact with the liquid. The surface tension of the liquid automatically aligns the top die by generating a force causing the top die to overlap with the top die placement region. The liquid is then eliminated and the top die is affixed to the carrier wafer. The carrier wafer is bonded to the interposer wafer, bringing the top die into contact with an interposer.

Abstract: In a QFN that includes a die pad, a semiconductor chip mounted on the die pad, a plurality of leads arranged around the semiconductor chip, a plurality of wires that electrically connect the plurality of electrode pads of the semiconductor chip with the plurality of leads, respectively, and a sealing member sealing the semiconductor chip and the plurality of wires, first and second step portions are formed at shifted positions on the left and right sides of each of the leads to make the positions of the first and second step portions shifted between the adjacent leads. As a result, the gap between the leads is narrowed, thereby achieving the miniaturization or the increase in the number of pins of the QFN.

Abstract: Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 ?m, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.

Abstract: A microelectronic device, e.g., semiconductor chip, is connected with an interconnection element having signal contacts and reference contacts, the reference contacts being connectable to a reference potential such as ground or power. Signal conductors, e.g., signal wirebonds can be connected to device contacts of the microelectronic device, and at least one reference conductor, e.g., reference wirebond can be connected with two reference contacts. The reference wirebond can have a run extending at an at least substantially uniform spacing from an at least a substantial portion of a length of a signal conductor, e.g., signal wirebond. In such manner a desired impedance may be achieved for the signal conductor.

Abstract: A semiconductor device includes a substrate, a multi-layer wiring layer formed on the substrate, and including a signal line and ground lines extending above the signal line, one of the ground lines extending toward a direction in a layer and another one of the ground lines extending from the one of the ground lines toward another direction in the layer, a first pad on the multi-layer wiring layer, and a redistribution layer formed on the multi-layer wiring layer, including a second pad, a redistribution line coupling the first pad and the second pad, and an insulation film covering the redistribution line.

Abstract: A chip identification for organic laminate packaging and methods of manufacture is provided. The method includes forming a material on a wafer which comprises a plurality of chips. The method further includes modifying the material to provide a unique identification for each of the plurality of chips on the wafer. The organic laminate structure includes a chip with a device and a material placed on the chip which is modified to have a unique identification mark for the chip.

Abstract: A semiconductor device has a semiconductor die and encapsulant deposited over the semiconductor die. A first insulating layer is formed over the die and encapsulant. The first insulating layer is cured with multiple dwell cycles to enhance adhesion to the die and encapsulant. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. The second insulating layer is cured with multiple dwell cycles to enhance adhesion to the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. The first, second, and third insulating layers have different CTE. The second insulating layer or third insulating layer is cured to a dense state to block moisture.

Abstract: A method of manufacturing a non-volatile memory device includes forming a number of memory cells. The method also includes depositing a first dielectric layer over the memory cells, where the first dielectric layer is a conformal layer having a substantially uniform thickness. The method further includes depositing a second dielectric layer over the first dielectric layer. Together, the first and second dielectric layers form an interlayer dielectric without voids.

Abstract: A device for aerating a liquid, such as wine, includes a cup portion with a cavity that receives an amount of liquid therein, the cavity extending between a proximal opening and a distal opening. A neck portion of the device defines an aeration section in fluid communication with the cavity. Passages in the aeration section extend laterally to an outer surface of the neck portion through which air is drawn into the aeration section. A central passage through the neck portion is in fluid communication with the aeration section and extends to a distal opening of the device. A diffuser element between the cavity and the aeration section has arms that are configured to contact the liquid as it flows from the cavity to inhibit a swirling flow of the liquid so that the liquid passes into the aeration section in a generally vertical and linear manner.

Abstract: A distillation column is provided with a downcomer having an enlarged upper region to increase a processing rate for the removal of permanganate reducing compounds (PRCs) formed by the carbonylation of methanol in the presence of a catalyst to produce acetic acid. The distillation column includes a vertically extending distillation housing; and a plurality of tray assemblies, at least one of which includes a horizontally extending tray panel and a downcomer having, in a downward direction, an enlarged, funnel-shaped upper region defined by a top downcomer panel oriented at an angle to the vertical, and a lower region of substantially constant cross-sectional area defined by a vertically-oriented bottom downcomer panel.

Abstract: According to embodiments of the invention, the design and fabrication of a binary superimposed grating (BSG) results in better performing devices that may be fabricated using existing technology. The fabrication process includes forming grating features based upon repeating features of the desired superposition function. The design process also relaxes the processing requirement for equivalently performing devices.

Abstract: An aspect of the present invention relates to a method of determining a manufacturing condition of a polythiourethane eyeglass lens obtained via a process of obtaining polythiourethane by polymerization reaction of an iso(thio)cyanate compound and a thiol compound, comprising determining a candidate composition for a starting material mixture and a candidate polymerization reaction condition employed in the polymerization reaction in actual manufacturing; polymerizing the starting material mixture of the candidate composition that has been determined under the candidate polymerization reaction condition to obtain a test sample; testing the obtained test sample by irradiation with a xenon lamp to determine whether or not change into red-like color is present following irradiation with the xenon lamp; and determining a starting material mixture composition and a polymerization reaction condition to be employed in the polymerization reaction in actual manufacturing with the use of a result of the determination a

Abstract: The present invention provides a nozzle plate and the use of the nozzle plate for producing filaments, preferably silica gel fibers.

Abstract: A system for encapsulating a cable 12 for the purpose of splice closures, breakout closures, jacket repair closures or end capping, in which a casing is fitted around a part of the cable to be sealed, defining within it a cavity surrounding the cable, and a sealant material in the form of a two part acrylic structural adhesive material is injected to fill the cavity and cured in situ. The two part adhesive has a base resin including a methacrylate monomer and a minor part including an oligomeric synthetic rubber and a curative for the monomer, preferably an organoborane accelerator such as an organoborane amine complex, which may be carried by a polyfunctional aziridine. The two parts are preferably mixed at a volume ratio of 2:1 to 15:1.

Abstract: a method comprising injection molding a plastic part from a polymer formulation comprising an injection moldable thermoplastic and an additive, wherein the additive has a decomposition temperature that establishes a maximum processing temperature for the polymer formulation. The additive will thermally decompose to generate gaseous products causing visible bubble formation in the surface of the plastic part in response to exposure to a processing temperature that exceeds the decomposition temperature of the additive. A suitable additive may be, for example, selected from oxalates, carbamic acids, carbonic acids, diazocarbonyl compounds, and combinations thereof.

Abstract: Thermoplastic particle foams which have cells having a mean cell size in the range from 20 to 500 ?m and in which the cell membranes have a nanocellular or fibrous structure having pore or fiber diameters below 1500 nm, and also processes for producing them.

Abstract: The invention relates to a method and a device for producing a crimped composite thread, wherein the inventive method consists in extruding, cooling and in drawing several yarns in the form of a plurality of strand filaments and in jointly crimping them in order to obtain a crimped composite thread. The aim of said invention is to make it possible to pre-treat the threads in a manner adaptable to each treatment step. The aim is attained by that at least one multi-treaded yarn is whirl-tangled many times during several operations prior to crimping. For this purpose, a whirl-tangling device provided with a plurality of whirl-tangling units following each other in a direction of the yarn displacement is used.

Abstract: A process for manufacturing a plastic hollow body by molding two sheets of molten plastic in a mold including two cavities, the process including: a) two molten plastic sheets are manufactured by extrusion of at least one stream of molten plastic and transverse cutting thereof; b) these sheets are introduced between the mold cavities; c) the mold is closed and the hollow body is manufactured by conforming the two sheets to the mold cavities; d) the hollow body thus obtained is removed from the mold; e) all of operations a) to d) are repeated to manufacture another hollow body from two new sheets; and before, during, or after the transverse cutting operation, the lower portion of the two new sheets is cooled using a specific device that makes possible a local cooling of the sheets in the lower portion.

Abstract: An exemplary method of, for instance, forming a baffle or reinforcer includes extruding an expandable material to have a particular cross-sectional profile, inserting the expandable material into a molding tool, cutting the expandable material to a predetermined length within the molding tool, and overmolding a carrier material onto a portion of the expandable material within the molding tool.

Abstract: A die for coextruding a plurality of fluid layers generally includes a primary forming stem, one or more distribution plates, and a microlayer assembly. The microlayer assembly includes a microlayer forming stem and a plurality of microlayer distribution plates.

Abstract: A continuous forming apparatus for molding foam material into foam products that includes a first endless belt and a second endless belt that cooperates with the first endless belt to mold the foam material. The continuous forming apparatus may also include a first plurality of cleats and a second plurality of cleats opposed to the first plurality of cleats that support the first endless belt and the second endless belt respectively. The first plurality of cleats may include a three-dimensional abutment surface that provides transverse and lateral support to the first endless belt. Additionally, the continuous forming apparatus may include a first frame disposed to support the first plurality of cleats, a second frame disposed to support the second plurality of cleats, and a drive mechanism for imparting motion to the first endless belt, the second endless belt, the first plurality of cleats, and the second plurality of cleats.

Abstract: A method and system for compression molding a dual core of a golf ball is disclosed. The method may include a first cycle in which a top mold plate, a middle mold plate, and a bottom mold plate may be used to compression mold concave shells. During the first cycle, the top mold plate and the bottom mold plate may be held at a first temperature T1 and the middle mold plate may be held at a second temperature T2. During the first cycle, the mold plates may be pressed together with a first pressure P1 for a first time t1. A second cycle may include compression molding the concave shells about a solid core. During the second cycle, the top mold plate and the bottom mold plate may be held at the first temperature T1 and pressed together with a second pressure P2 for a second time t2.

Abstract: [PROBLEM] To provide a method of molding a composite molded article enabling compression molding without requiring a large sized injection molding machine and a mold system used for that. [MEANS FOR SOLUTION] A method of molding a composite molded article using a first mold member 13 to mold a primary molded article 29 by primary molding, switching a movable mold member 14 holding the primary molded article 29 with a movable mold member 14 positioned with a second mold member 15, then using a second mold member 15 in which the primary molded article 29 is inserted to mold a secondary molded article 30 by secondary molding, wherein the primary molding and the secondary molding are executed by non-continuous different steps at points of time different from each other.

Abstract: The mask of the invention is used for plugging of the cells of a honeycomb structure, and it has a plurality of first through-holes running through a thickness direction of the mask, in a region that is to contact with an end face of the honeycomb structure when used. The first through-holes have an open area of 0.03 mm2 or greater, and less than 90% of an open area of the cells to be plugged through the first through-holes.