Abstract: A polarization structure for a display device is disclosed. In one embodiment, the structure includes a retardation layer, a first polarizing layer, a first uniaxial optical compensation layer, a second polarizing layer and a second uniaxial optical compensation layer. The retardation layer may be configured to create a phase difference between two polarization components of an incident light. The first polarizing layer may be disposed on the retardation layer. The first uniaxial optical compensation layer may be disposed on the first polarizing layer. The second polarizing layer may be disposed on the first uniaxial optical compensation layer. The second uniaxial optical compensation layer may be disposed between the first polarizing layer and the first uniaxial optical compensation layer or between the first polarizing layer and the second polarizing layer.

Abstract: Exemplary embodiments of the present invention disclose a light emitting diode (LED) and a method of fabricating the same. The LED includes a substrate, a semiconductor stack arranged on the substrate, the semiconductor stack including an upper semiconductor layer having a first conductivity type, an active layer, and a lower semiconductor layer having a second conductivity type, isolation trenches separating the semiconductor stack into a plurality of regions, connectors disposed between the substrate and the semiconductor stack, the connectors electrically connecting the plurality of regions to one another, and a distributed Bragg reflector (DBR) having a multi-layered structure, the DBR disposed between the semiconductor stack and the connectors. The connectors are electrically connected to the semiconductor stack through the DBR, and portions of the DBR are disposed between the isolation trenches and the connectors.

Abstract: An organic light emitting device includes, a base part, patterned first electrodes on the base part, conductive material layers spaced apart from the patterned first electrodes and between the first electrodes, pixel defining layers between the patterned first electrodes, the pixel defining layers overlapping only a portion of upper surfaces of the conductive material layers, light emitting layers on the first electrodes, and a second electrode on the light emitting layers.

Abstract: The present application provides a light-emitting device comprising a first light-emitting diode group with a first hot/cold factor comprising a plurality of first light-emitting diode units electrically connected to one another; and a temperature compensation element electrically connected to the first light-emitting diode group, and comprising a first resistor and a second resistor; wherein the first resistor has a first temperature coefficient of resistance and the second resistor has a second temperature coefficient of resistance; and the absolute value of the first temperature coefficient of resistance is ten times greater than that of the second temperature coefficient of resistance.

Abstract: The present disclosure provides a light emitting diode (LED) apparatus. The LED apparatus includes an LED emitter having a top surface; and a phosphor feature disposed on the LED emitter. The phosphor feature includes a first phosphor film disposed on the top surface of the LED emitter and having a first dimension defined in a direction parallel to the top surface of the LED emitter; a second phosphor film disposed on the first phosphor film and having a second dimension defined in the direction; and the second dimension is substantially less than the first dimension.

Abstract: A light emitting diode structure and methods of manufacturing the same are disclosed. In an example, a light emitting diode structure includes a crystalline substrate having a thickness that is greater than or equal to about 250 ?m, wherein the crystalline substrate has a first roughened surface and a second roughened surface, the second roughened surface being opposite the first roughened surface; a plurality of epitaxy layers disposed over the first roughened surface, the plurality of epitaxy layers being configured as a light emitting diode; and another substrate bonded to the crystalline substrate such that the plurality of epitaxy layers are disposed between the another substrate and the first roughened surface of the crystalline substrate.

Abstract: A light emitting diode including a substrate, a first semiconductor layer, an active layer, and a second semiconductor layer is provided. The first semiconductor layer includes a first surface and a second surface, and the first surface is connected to the substrate. The active layer and the second semiconductor layer are stacked on the second surface in that order, and a surface of the second semiconductor layer away from the active layer is configured as the light emitting surface. A first electrode electrically is connected with the first semiconductor layer. A second electrode is electrically connected with the second semiconductor layer. A number of three-dimensional nano-structures are located on the surface of the first surface of the first semiconductor layer and aligned side by side, and a cross section of each of the three-dimensional nano-structure is M-shaped.

Abstract: A light emitting diode including a substrate, a first semiconductor layer, an active layer, and a second semiconductor layer is provided. A surface of the substrate away from the active layer is configured as the light emitting surface. The first semiconductor layer includes a first surface and a second surface, and the first surface is connected to the substrate. The active layer and the second semiconductor layer are stacked on the second surface in that order. A first electrode electrically is connected with the first semiconductor layer. A second electrode is electrically connected with and covers a surface of the second semiconductor layer. A number of three-dimensional nano-structures are located on the surface of the first surface of the first semiconductor layer and the light emitting surface, and a cross section of each of the three-dimensional nano-structure is M-shaped.

Abstract: A light emitting diode including a first semiconductor layer, an active layer, and a second semiconductor layer is provided. The first semiconductor layer includes a first surface and a second surface. The active layer and the second semiconductor layer are stacked on the second surface in that order, and a surface of the second semiconductor layer away from the active layer is configured as the light emitting surface. A first electrode is electrically connected with and covers the first surface of the first semiconductor layer. A second electrode is electrically connected with the second semiconductor layer. A number of three-dimensional nano-structures are located on the surface of the first surface of the first semiconductor layer and the light emitting surface, and a cross section of each of the three-dimensional nano-structure is M-shaped.

Abstract: A light emitting diode including a first semiconductor layer, an active layer, and a second semiconductor layer is provided. The first semiconductor layer includes a first surface and a second surface, and the first surface is connected to the substrate. The active layer and the second semiconductor layer are stacked on the second surface in that order, and a surface of the second semiconductor layer away from the active layer is configured as the light emitting surface. A first electrode covers the entire surface of the first semiconductor layer. A second electrode is electrically connected with the second semiconductor layer. A number of three-dimensional nano-structures are located on the surface of the first surface of the first semiconductor layer and aligned side by side, and a cross section of each of the three-dimensional nano-structure is M-shaped.

Abstract: In an organic light emitting device and a method of manufacturing the organic light emitting device, reflective layers are formed on pixel definition layers to prevent the generation of an open edge defect (or a non-transfer defect) in forming light emitting layers. The organic light emitting device includes a base, first electrodes patterned and formed on the base, light emitting layers formed on the first electrodes, and a second electrode formed on the light emitting layers. Pixel definition layers are formed between the patterned first electrodes, and reflective layers are disposed in the pixel definition layers.

Abstract: A method for producing an optoelectronic semiconductor chip is specified, comprising the following steps: providing an n-conducting layer (2), arranging a p-conducting layer (4) on the n-conducting layer (2), arranging a metal layer sequence (5) on the p-conducting layer (4),arranging a mask (6) at that side of the metal layer sequence (5) which is remote from the p-conducting layer (4),in places removing the metal layer sequence (5) and uncovering the p-conducting layer (4) using the mask (6), and in places neutralizing or removing the uncovered regions (4a) of the p-conducting layer (4) as far as the n-conducting layer (2) using the mask (6), wherein the metal layer sequence (5) comprises at least one mirror layer (51) and a barrier layer (52), and the mirror layer (51) of the metal layer sequence (5) faces the p-conducting layer (4).

Abstract: A textile-type organic light-emitting device and a method of manufacturing the textile-type organic light-emitting device are provided. The light-emitting device includes a textile-type first electrode; an organic light-emitting material layer formed on a surface of the textile-type first electrode; and a second electrode formed on the organic light-emitting material layer, the second electrode being transparent.

Abstract: In various embodiments, the present invention provides a light emitting device cap configured for location on a light emitting device comprising or consisting essentially of a primary light source. The cap defines a well region within which is received a population of semiconductor nanoparticles such that the semiconductor nanoparticles are in optical communication with the primary light source of the light emitting device when the cap is located on the light emitting device. There is further provided a light emitting device comprising or consisting essentially of a primary light source and such a cap, as well as methods for fabricating such a cap and device.

Abstract: The disclosed recessed thyristor-based memory cell comprises in one embodiment a conductive plug recessed into the bulk of the substrate, which is coupled to or comprises the enable gate of the cell. Vertically disposed around this recessed gate is a thyristor, whose anode is connected to the bit line and cathode is connected to the word line. The disclosed cell comprises no other gate, such as an access transistor, and hence is essentially a one-transistor device. As facilitated by the vertical disposition of the thyristor, the disclosed cell takes up a small amount of area on an integrated circuit when compared to a traditional DRAM cell. The disclosed cell is simple to manufacture in its various embodiments, and is easy to configure into an array of cells. Isolation underneath the cell assists in improving the data retention of the cell and extends the time needed between cell refresh.

Abstract: According to one disclosed embodiment, a power semiconductor package includes an insulated-gate bipolar transistor (IGBT) residing on a package substrate, where the IGBT includes a plurality of solderable front metal (SFM) coated emitter segments situated atop the IGBT and connected to an emitter of the IGBT. The power semiconductor package also includes a conductive clip coupling the plurality of SFM coated emitter segments to an emitter pad on the package substrate. Additionally, the power semiconductor package includes a gate pad on the package substrate coupled to a gate of the IGBT, a collector pad on the package substrate situated under the IGBT and coupled to a collector of the IGBT, and an emitter terminal, a collector terminal and a gate terminal of the package substrate that are routed to the emitter pad, collector pad, and gate pad, respectively.

Abstract: Provided is a power semiconductor device including a semiconductor substrate, in which a current flows in a thickness direction of the semiconductor substrate. The semiconductor substrate includes a resistance control structure configured so that a resistance to the current becomes higher in a central portion of the semiconductor substrate than a peripheral portion of the semiconductor substrate.

Abstract: A silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) is disclosed, including: a substrate; two field oxide regions formed in the substrate; two pseudo buried layers, each being formed under a corresponding one of the field oxide regions; a collector region formed between the field oxide regions, the collector region laterally extending under a corresponding one of the field oxide regions and each side of the collector region being connected with a corresponding one of the pseudo buried layers; a matching layer formed under both the pseudo buried layers and the collector region; and two deep hole electrodes, each being formed in a corresponding one of the field oxide regions, the deep hole electrodes being connected to the corresponding ones of the pseudo buried layers for picking up the collector region. A manufacturing method of the SiGe HBT is also disclosed.

Abstract: A method of fabricating a multi-layer structure for a power transistor device includes performing, within a reaction chamber, a nitrogen plasma strike, resulting in the formation of a nitride layer directly on a nitride-based active semiconductor layer. A top surface of the nitride layer is then exposed to a second source. A subsequent nitrogen-oxygen plasma strike results in the formation of an oxy-nitride layer directly on the nitride layer. The nitride layer comprises a passivation layer and the oxy-nitride layer comprises a gate dielectric of the power transistor device.

Abstract: A complementary logic device includes: an insulating layer formed on a substrate; a source electrode formed of a ferromagnetic body on the insulating layer; a gate insulating film; a gate electrode formed on the gate insulating film and controlling a magnetization direction of the source electrode; a channel layer formed on each of a first side surface and a second side surface of the source electrode and transmitting spin-polarized electrons from the source electrode; a first drain electrode formed on the first side surface of the source electrode; and a second drain electrode formed on the second side surface of the source electrode, wherein a magnetization direction of the first drain electrode and a magnetization direction of the second drain electrode are antiparallel to each other. Therefore, not only characteristics of low power and high speed but also characteristics of non-volatility and multiple switching by spin may be obtained.

Abstract: Disclosed are structures and methods related to metallization of a doped gallium arsenide (GaAs) layer. In some embodiments, such metallization can include a tantalum nitride (TaN) layer formed on the doped GaAs layer, and a metal layer formed on the TaN layer. Such a combination can yield a Schottky diode having a low turn-on voltage, with the metal layer acting as an anode and an electrical contact connected to the doped GaAs layer acting as a cathode. Such a Schottky diode can be utilized in applications such as radio-frequency (RF) power detection, reference-voltage generation using a clamp diode, and photoelectric conversion. In some embodiments, the low turn-on Schottky diode can be fabricated utilizing heterojunction bipolar transistor (HBT) processes.

Abstract: In a photoelectric conversion device, groups of unit pixels are arranged in a well, where each of the unit pixels includes photoelectric conversion elements, an amplifier transistor, and transfer transistors. The photoelectric conversion device includes a line used to supply a voltage to the well, a well-contact part used to connect the well-voltage-supply line to the well, and transfer-control lines used to control the transfer transistors. The transfer-control lines are symmetrically arranged with respect to the well-voltage-supply line in respective regions of the unit-pixel groups.

Abstract: The invention relates to image sensors, more particularly but not exclusively to scanning sensors with signal integration (or TDI sensors, for ‘Time Delay Integration linear sensors’). The adjacent pixels along a column each comprise an alternation of at least one photodiode and one storage gate adjacent to the photodiode. The gates comprise a main body and, on the upstream side in the direction of the transfer of the charges but not on the downstream side, a series of narrow fingers extending from the main body toward the upstream side, the ends of the fingers on the upstream side being adjacent to a photodiode situated upstream of the gate, the narrow fingers being separated from one another by doped insulating regions of the first type of conductivity, with a higher doping and preferably deeper than the surface regions, connected, as they are, to the reference potential of the active layer, these insulating regions being interposed between the main body of the gate and the photodiode.

Abstract: A solid-state imaging device which includes a plurality of pixels in an arrangement, each of the pixels including a photoelectric conversion element, pixel transistors including a transfer transistor, and a floating diffusion region, in which the channel width of transfer gate of the transfer transistor is formed to be larger on a side of the floating diffusion region than on a side of the photoelectric conversion element.

Abstract: The present disclosure relates to a pressure sensor having a nanostructure and a method for manufacturing the same. More particularly, it relates to a pressure sensor having a nanostructure attached on the surface of the pressure sensor and thus having improved sensor response time and sensitivity and a method for manufacturing the same. The pressure sensor according to the present disclosure having a nanostructure includes: a substrate; a source electrode and a drain electrode arranged on the substrate with a predetermined spacing; a flexible sensor layer disposed on the source electrode and the drain electrode; and a nanostructure attached on the surface of the flexible sensor layer and having nanosized wrinkles.

Abstract: A back-bias region is disposed on a substrate. A buried insulating layer covers the substrate and the back-bias region. A body is formed on the buried insulating layer and partially overlaps the back-bias region. A drain is in contact with the body. A gate electrode covers top and lateral surfaces of the body.

Abstract: A method of manufacturing a CMOS image sensor is disclosed. A silicon-on-insulator substrate is provided, which includes providing a silicon-on-insulator substrate including a mechanical substrate, an insulator layer substantially overlying the mechanical substrate, and a seed layer substantially overlying the insulator layer. A semiconductor substrate is epitaxially grown substantially overlying the seed layer. The mechanical substrate and at least a portion of the insulator layer are removed. An ultrathin oxide later is formed substantially underlying the semiconductor substrate. A mono layer of metal is formed substantially underlying the ultrathin oxide layer.

Abstract: A method for manufacturing a semiconductor device comprises: forming a lower electrode on a semiconductor substrate, sputtering a ferroelectric film on the lower electrode using a target, thermal treating the ferroelectric film in an atmosphere containing oxygen in accordance with an accumulated period of use of the target for fabricating the ferroelectric film, and forming an upper electrode on the ferroelectric film.

Abstract: Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more STT memory cell structures include a tunneling barrier material positioned between a ferromagnetic storage material and a pinned ferromagnetic material in contact with an antiferromagnetic material and a multiferroic material in contact with the ferromagnetic storage material, wherein the antiferromagnetic material, the ferromagnetic storage material, and the pinned ferromagnetic material are located between a first electrode and a second electrode.

Abstract: In one embodiment of an integrated circuit, the integrated circuit includes a power transistor with a power control terminal, a first power load terminal and a second power load terminal. The integrated circuit further includes an auxiliary transistor with an auxiliary control terminal, a first auxiliary load terminal and a second auxiliary load terminal. The first auxiliary load terminal is electrically coupled to the power control terminal. The integrated circuit further includes a capacitor with a first capacitor electrode, a second capacitor electrode and a capacitor dielectric layer. The capacitor dielectric layer includes at least one of a ferroelectric material and a paraelectric material. The first capacitor electrode is electrically coupled to the auxiliary control terminal.

Abstract: A semiconductor device capable of high-speed operation. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is supplied with a first signal. One of a source and a drain of the second transistor is supplied with a first potential. A gate of the second transistor is supplied with a second signal. A first electrode of the capacitor is electrically connected to the other of the source and the drain of the first transistor. A second electrode of the capacitor is electrically connected to the other of the source and the drain of the second transistor. In a first period, the first signal is low and the second signal is high. In a second period, the first signal is high and the second signal is either low or high.

Abstract: A semiconductor structure having U-shaped transistors includes source/drain regions at the tops of pairs of pillars defined by crossing trenches in the substrate. One pillar is connected to the other pillar in the pair by a ridge that extends above the surrounding trenches. The ridge and lower portions of the pillars define U-shaped channels on opposite sides of the U-shaped structure, facing a gate structure in the trenches on those opposite sides, forming a two sided surround transistor. Optionally, the space between the pillars of a pair is also filled with gate electrode material to define a three-sided surround gate transistor. One of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. Methods of forming semiconductor structures are also disclosed.

Abstract: A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.

Abstract: The present invention discloses a flash memory. The flash memory includes a substrate and a memory string, a plurality of landing pads, a plurality of common source lines, a plurality of bit line contacts and at least a bit line, which are disposed on the substrate in sequence. The memory string includes a plurality of storage transistors. The landing pads are disposed between each of the storage transistors. The common source lines and the bit line contact are electrically connected to the landing pads alternatively. The common line is disposed on the common line contacts and is electrically connected thereto. The present invention further provides a manufacturing method of making the same.

Abstract: A MONOS Charge-Trapping flash (CTF), with record thinnest 3.6 nm ENT trapping layer, has a large 3.1V 10-year extrapolated retention window at 125° C. and excellent 106 endurance at a fast 100 is and ±16 V program/erase. This is achieved using As+-implanted higher ? trapping layer with deep 5.1 eV work-function of As. In contrast, the un-implanted device only has a small 10-year retention window of 1.9 V at 125° C. A MoN—[SiO2—LaAlO3]—[Ge—HfON]—[LaAlO3—SiO2]—Si CTF device is also provided with record-thinnest 2.5-nm Equivalent-Si3N4-Thickness (ENT) trapping layer, large 4.4 V initial memory window, 3.2 V 10-year extrapolated retention window at 125° C., and 3.6 V endurance window at 106 cycles, under very fast 100 ?s and low ±16 V program/erase. These were achieved using Ge reaction with HfON trapping layer for better charge-trapping and retention.

Abstract: A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced.

Abstract: A three-dimensional semiconductor memory device may include gap-fill insulating layers extending upward from a substrate, an electrode structure delimited by sidewalls of the gap-fill insulating layers, vertical structures provided between adjacent ones of the gap-fill insulating layers to penetrate the electrode structure, and at least one separation pattern extending along the gap-fill insulating layers and penetrating at least a portion of the electrode structure. The separation pattern may include at least one separation semiconductor layer.

Abstract: The invention discloses a semiconductor structure comprising: a substrate, a conductor layer, and a dielectric layer surrounding the conductor layer on the substrate; a first insulating layer covering both of the conductor layer and the dielectric layer; a gate conductor layer formed on the first insulating layer, and a dielectric layer surrounding the gate conductor layer; and a second insulating layer covering both of the gate conductor layer and the dielectric layer surrounding the gate conductor layer; wherein a through hole filled with a semiconductor material penetrates through the gate conductor layer perpendicularly, the bottom of the through hole stops on the conductor layer, and a first conductor plug serving as a drain/source electrode is provided on the top of the through hole; and a second conductor plug serving as a source/drain electrode electrically contacts the conductor layer, and a third conductor plug serving as a gate electrode electrically contacts the gate conductor layer.

Abstract: The present invention belongs to the field of microelectronic device technologies. Specifically, an asymmetric source/drain field-effect transistor and its methods of making are disclosed. A structure of the field-effect transistor comprises: a semiconductor substrate, a gate structure, and a source region and a drain region having a mixed junction and a P-N junction, respectively. The source region and the drain region are asymmetrical structured with respect to each other, one of which comprises a P-N junction, and the other of which comprises a mixed junction, the mixed junction being a combination of a Schottky junction and a P-N junction. According to the present disclosure, a location of a doped region formed by ion implantation is controlled by adjusting an implantation angle, and a unique structure is formed for the asymmetric source/drain field-effect transistor.

Abstract: Embodiments relate to a field-effect device that includes a body region, a first source/drain region of a first conductivity type, a second source/drain region, and a pocket implant region adjacent to the first source/drain region, the pocket implant region being of a second conductivity type, wherein the second conductivity type is different from the first conductivity type. The body region physically contacts the pocket implant region.

Abstract: A SGT production method includes a step of forming first and second fin-shaped silicon layers, forming a first insulating film, and forming first and second pillar-shaped silicon layers; a step of forming diffusion layers by implanting an impurity into upper portions of the first and second pillar-shaped silicon layers, upper portions of the first and second fin-shaped silicon layers, and lower portions of the first and second pillar-shaped silicon layers; a step of forming a gate insulating film and first and second polysilicon gate electrodes; a step of forming a silicide in upper portions of the diffusion layers formed in the upper portions of the first and second fin-shaped silicon layers; and a step of depositing an interlayer insulating film, exposing and etching the first and second polysilicon gate electrodes, then depositing a metal, and forming first and second metal gate electrodes.

Abstract: A semiconductor device includes a cylindrical main pillar that is formed on a substrate and of which a central axis is perpendicular to the surface of the substrate, source and drain diffused layers that are formed in a concentric shape centered on the central axis at upper and lower portions of the main pillar and made from a first-conduction-type material, a body layer that is formed at an intermediate portion of the main pillar sandwiched between the source and drain diffused layers and made from the first-conduction-type material, and a front gate electrode that is formed on a lateral face of the main pillar while placing a gate insulating film therebetween. Moreover, a back gate electrode made from a second-conduction-type material is formed in a pillar shape penetrating from an upper portion to a lower portion on an inner side of the main pillar.

Abstract: A transistor having at least one passivated Schottky barrier to a channel includes an insulated gate structure on a p-type substrate in which the channel is located beneath the insulated gate structure. The channel and the insulated gate structure define a first and second undercut void regions that extend underneath the insulated gate structure toward the channel from a first and a second side of the insulated gate structure, respectively. A passivation layer is included on at least one exposed sidewall surface of the channel, and metal source and drain terminals are located on respective first and second sides of the channel, including on the passivation layer and within the undercut void regions beneath the insulated gate structure. At least one of the metal source and drain terminals comprises a metal that has a work function near a valence band of the p-type substrate.

Abstract: A trench Schottky diode and a manufacturing method thereof are provided. The manufacturing method includes the following steps. Firstly, a semiconductor substrate is provided. A multi-trench structure including a wide trench and a plurality of narrow trenches is formed in the semiconductor substrate, a gate oxide layer is formed on a surface of the multi-trench structure, and a polysilicon structure is formed over the gate oxide layer and the first oxide layer. The polysilicon structure is etched to partially expose the first oxide layer and the gate oxide layer on a bottom surface of the wide trench. The semiconductor substrate, the polysilicon structure and the gate oxide layer are partially exposed by a photolithography and etching process. A metal sputtering layer is formed. Afterwards, the metal sputtering layer is etched to expose a part of the second oxide layer.

Abstract: A method of formation of an isolation structure for vertical semiconductor devices, the resulting isolation structure, and a memory device to prevent leakage among adjacent vertical semiconductor devices are described.

Abstract: A transistor component includes an active transistor region arranged in the semiconductor body. And insulation region surrounds the active transistor region in the semiconductor body in a ring-shaped manner. A source zone, a drain zone, a body zone and a drift zone are disposed in the active transistor region. The source zone and the drain zone are spaced apart in a lateral direction of the semiconductor body and the body zone is arranged between the source zone and the drift zone and the drift zone is arranged between the body zone and the drain zone. A gate and field electrode is arranged over the active transistor region. The dielectric layer has a first thickness in in a region near the body zone and a second thickness in a region near the drift zone.

Abstract: In one embodiment, a Super Junction metal oxide semiconductor field effect transistor (MOSFET) device can include a substrate and a charge compensation region located above the substrate. The charge compensation region can include a plurality of columns of P type dopant within an N type dopant region. In addition, the Super Junction MOSFET can include a termination region located above the charge compensation region and the termination region can include an N? type dopant. Furthermore, the Super Junction MOSFET can include an edge termination structure. The termination region includes a portion of the edge termination structure.

Abstract: A method of replacing semiconductor material with metal, Replacement Metal Gate Field Effect Transistors (RMG FETs) and Contacts (RMCs), and Integrated Circuit (IC) chips including the FETs and/or RMCs. A patterned semiconductor layer, e.g., silicon, is formed on a dielectric layer, e.g., a layered gate dielectric. A field dielectric layer fills between shapes in the patterned semiconductor layer. Metal is deposited on the shapes. The wafer is annealed to replace semiconductor in each shape with metal to form metal FET gates or contacts.

Abstract: A semiconductor device includes a gate, a first electrode, a first insulating layer, an active layer, an etching stop layer, a second insulating layer, a source, a drain and a second electrode. The first insulating layer covers the gate and the first electrode. The active layer and the etching stop layer are disposed on the first insulating layer above the gate and the first electrode respectively. The second insulating layer covers the active layer and the etching stop layer and has a first opening and a second opening exposing the active layer and a third opening exposing the etching stop layer. The source and the drain are disposed on the second insulating layer and contact with the active layer through the first opening and the second opening respectively. The second electrode is located on the second insulating layer and contacts with the etching stop layer through the third opening.

Abstract: A stressed channel field effect transistor (FET) includes a substrate; a gate stack located on the substrate; a channel region located in the substrate under the gate stack; source/drain stressor material located in cavities in the substrate on either side of the channel region; and vertical source/drain buffers located in the cavities in the substrate between the source/drain stressor material and the substrate, wherein the source/drain stressor material abuts the channel region above the source/drain buffers.