Patents Issued in June 6, 2013
  • Fin-Like Field Effect Transistor (FinFET) Device and Method of Manufacturing Same
    Publication number: 20130140637
    Abstract: A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary method includes providing a semiconductor substrate; forming a fin structure over the semiconductor substrate, the fin structure including a first material portion over the semiconductor substrate and a second material portion over the first material portion; forming a gate structure over a portion of the fin structure, such that the gate structure traverses the fin structure, thereby separating a source region and a drain region of the fin structure, wherein the source and drain regions of the fin structure define a channel therebetween; removing the second material portion from the source and drain regions of the fin structure; and after removing the second material portion, forming a third material portion in the source and drain regions of the fin structure.
    Type: Application
    Filed: February 1, 2013
    Publication date: June 6, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Taiwan Semiconductor Manufacturing Company, Ltd.
  • HIGH DENSITY SIX TRANSISTOR FINFET SRAM CELL LAYOUT
    Publication number: 20130140638
    Abstract: Dual orientation of finFET transistors in a static random access memory (SRAM) cell allows aggressive scaling to a minimum feature size of 15 nm and smaller using currently known masking techniques that provide good manufacturing yield. A preferred layout and embodiment features inverters formed from adjacent, parallel finFETs with a shared gate and different conductivity types developed through a double sidewall image transfer process while the preferred dimensions of the inverter finFETs and the pass transistors allow critical dimensions of all transistors to be sufficiently uniform despite the dual transistor orientation of the SRAM cell layout.
    Type: Application
    Filed: February 4, 2013
    Publication date: June 6, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: International Business Machines Corporation
  • HIGH GATE DENSITY DEVICES AND METHODS
    Publication number: 20130140639
    Abstract: A semiconductor device with an isolation feature is disclosed. The semiconductor device includes a plurality of gate structures disposed on a semiconductor substrate, a plurality of gate sidewall spacers of a dielectric material formed on respective sidewalls of the plurality of gate structures, an interlayer dielectric (ILD) disposed on the semiconductor substrate and the gate structures, an isolation feature embedded in the semiconductor substrate and extended to the ILD and a sidewall spacer of the dielectric material disposed on sidewalls of extended portion of the isolation feature.
    Type: Application
    Filed: December 1, 2011
    Publication date: June 6, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Feng Shieh, Chang-Yun Chang, Hsin-Chih Chen
  • N-WELL/P-WELL STRAP STRUCTURES
    Publication number: 20130140640
    Abstract: Embodiments of N-well or P-well strap structures are disclosed with lower requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.
    Type: Application
    Filed: August 4, 2011
    Publication date: June 6, 2013
    Applicant: ALTERA CORPORATION
    Inventors: Dustin Do, Andy L. Lee, Giles V. Powell, Bradley Jensen, Swee Aun Lau, Wuu-Cherng Lin
  • METAL GATE FEATURES OF SEMICONDUCTOR DIE
    Publication number: 20130140641
    Abstract: A CMOS semiconductor die comprises a substrate; an insulation layer over a major surface of the substrate; a plurality of P-metal gate areas formed within the insulation layer collectively covering a first area of the major surface; a plurality of N-metal gate areas formed within the insulation layer collectively covering a second area of the major surface, wherein a first ratio of the first area to the second area is equal to or greater than 1; a plurality of dummy P-metal gate areas formed within the insulation layer collectively covering a third area of the major surface; and a plurality of dummy N-metal gate areas formed within the insulation layer collectively covering a fourth area of the major surface, wherein a second ratio of the third area to the fourth area is substantially equal to the first ratio.
    Type: Application
    Filed: December 6, 2011
    Publication date: June 6, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Harry-Hak-Lay CHUANG, Ming ZHU
  • ANALOG CIRCUIT CELL ARRAY AND ANALOG INTEGRATED CIRCUIT
    Publication number: 20130140642
    Abstract: An analog circuit cell array includes a plurality of transistor cell arranged in an array. Each of the transistor cells includes a first source region, a first channel region, a common drain region, a second channel region, and a second source region arranged in sequence one adjacent to another; and a first gate electrode and a second gate electrode formed on the first channel region and the second channel region, respectively, and wherein the first gate electrode and the second gate electrode are connected together for use, and the first source region and the second source region are connected together for use.
    Type: Application
    Filed: January 22, 2013
    Publication date: June 6, 2013
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: FUJITSU SEMICONDUCTOR LIMITED
  • INTEGRATED HIGH-K/METAL GATE IN CMOS PROCESS FLOW
    Publication number: 20130140643
    Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first active region and a second active region, forming a first metal layer over a high-k dielectric layer, removing at least a portion of the first metal layer in the second active region, forming a second metal layer on first metal layer in the first active region and over the high-k dielectric layer in the second active region, and thereafter, forming a silicon layer over the second metal layer. The method further includes removing the silicon layer from the first gate stack thereby forming a first trench and from the second gate stack thereby forming a second trench, and forming a third metal layer over the second metal layer in the first trench and over the second metal layer in the second trench.
    Type: Application
    Filed: February 1, 2013
    Publication date: June 6, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Taiwan Semiconductor Manufacturing Company, Ltd.
  • METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    Publication number: 20130140644
    Abstract: A method of manufacturing a semiconductor device involves process for forming gate insulating films of different thickness on a semiconductor substrate, depositing films that constitute a gate electrode, removing the gate insulating films having different thickness formed on an impurity diffusion region surface of a transistor including the gate electrode, and doping impurities into a portion where the gate insulating film is removed.
    Type: Application
    Filed: January 17, 2013
    Publication date: June 6, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: KABUSHIKI KAISHA TOSHIBA
  • SEMICONDUCTOR FUSES IN A SEMICONDUCTOR DEVICE COMPRISING METAL GATES
    Publication number: 20130140645
    Abstract: In a replacement gate approach, the semiconductor material of the gate electrode structures may be efficiently removed during a wet chemical etch process, while this material may be substantially preserved in electronic fuses. Consequently, well-established semiconductor-based electronic fuses may be used instead of requiring sophisticated metal-based fuse structures. The etch selectivity of the semiconductor material may be modified on the basis of ion implantation or electron bombardment.
    Type: Application
    Filed: January 2, 2013
    Publication date: June 6, 2013
    Applicant: Globalfoundries Inc.
    Inventors: Jens Heinrich, Ralf Ritcher, Kai Frohberg
  • TRANSISTOR WITH REDUCED DEPLETION FIELD WIDTH
    Publication number: 20130140646
    Abstract: Devices such as transistors having an oxide layer that provide a depletion field in a conduction channel. A barrier layer is formed over the oxide layer. A gate electrode is formed over the barrier layer. The barrier layer and gate electrode are configured to reduce the width of the depletion field absent a voltage applied to the gate electrode.
    Type: Application
    Filed: January 28, 2013
    Publication date: June 6, 2013
    Applicant: Round Rock Research, LLC
    Inventor: Round Rock Research, LLC
  • III-V METAL-OXIDE-SEMICONDUCTOR DEVICE
    Publication number: 20130140647
    Abstract: A hafnium oxide layer, between a III-V semiconductor layer and a metal oxide layer is used to prevent interaction between the III-V semiconductor layer and the metal oxide layer.
    Type: Application
    Filed: February 4, 2013
    Publication date: June 6, 2013
    Applicant: NATIONAL CHIAO TUNG UNIVERSITY
    Inventor: NATIONAL CHIAO TUNG UNIVERSITY
  • ELECTROCHEMICAL TRANSISTOR
    Publication number: 20130140648
    Abstract: The object of the invention is to provide a three-terminal switch (electrochemical transistor) capable of achieving sharp on-off operation. A source electrode and a drain electrode are juxtaposed with an insulator interposed between them, and on the assembly there is an ion diffusion member such as Ta2O5 located. On the opposite surface of the ion diffusion member, there is a gate electrode located that is capable of supplying metal ions such as copper ions. By application of voltage to the gate electrode, the metal ions going out of the gate electrode are reversibly precipitated as metal on both source and drain electrodes as well as on the insulator near them, thereby controlling conduction and non-conduction between the source electrode and the drain electrode.
    Type: Application
    Filed: September 8, 2011
    Publication date: June 6, 2013
    Inventors: Tsuyoshi Hasegawa, Masakazu Aono, Kazuya Terabe, Tohru Tsuruoka, Yaomi Itoh
  • TRANSIENT DEVICES DESIGNED TO UNDERGO PROGRAMMABLE TRANSFORMATIONS
    Publication number: 20130140649
    Abstract: The invention provides transient devices, including active and passive devices that electrically and/or physically transform upon application of at least one internal and/or external stimulus. Materials, modeling tools, manufacturing approaches, device designs and system level examples of transient electronics are provided.
    Type: Application
    Filed: September 21, 2012
    Publication date: June 6, 2013
    Inventors: John A. ROGERS, Fiorenzo G. OMENETTO, Suk-Won HWANG, Hu TAO, Dae-Hyeong KIM, David KAPLAN
  • MEMS Devices and Methods for Forming the Same
    Publication number: 20130140650
    Abstract: A method includes forming a Micro-Electro-Mechanical System (MEMS) device on a front surface of a substrate. After the step of forming the MEMS device, a through-opening is formed in the substrate, wherein the through-opening is formed from a backside of the substrate. The through-opening is filled with a dielectric material, which insulates a first portion of the substrate from a second portion of the substrate. An electrical connection is formed on the backside of the substrate. The electrical connection is electrically coupled to the MEMS device through the first portion of the substrate.
    Type: Application
    Filed: December 2, 2011
    Publication date: June 6, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Te-Hao Lee, Yuan-Chih Hsieh
  • MICROELECTROMECHANICAL SYSTEMS (MEMS) RESONATORS AND RELATED APPARATUS AND METHODS
    Publication number: 20130140651
    Abstract: Devices having piezoelectric material structures integrated with substrates are described. Fabrication techniques for forming such devices are also described. The fabrication may include bonding a piezoelectric material wafer to a substrate of a differing material. A structure, such as a resonator, may then be formed from the piezoelectric material wafer.
    Type: Application
    Filed: November 20, 2012
    Publication date: June 6, 2013
    Applicant: Sand 9, Inc.
    Inventors: David M. Chen, Jan H. Kuypers, Pritiraj Mohanty, Klaus Juergen Schoepf, Guiti Zolfagharkhani, Jason Goodelle, Reimund Rebel
  • MAGNETIC PRESSURE SENSOR
    Publication number: 20130140652
    Abstract: A magnetic pressure sensor is provided that includes a semiconductor body with a top side and a back side, a Hall sensor formed on the top side of the semiconductor body, a spacer connected to the semiconductor body, whereby the spacer has a recess in the center, and a membrane covering the recess, whereby the membrane has a first material and has a ferromagnetic substance. The ferromagnetic substance concentrates a magnetic flux density of a source formed outside the ferromagnetic material, and the spacer is formed as a circumferential wall and has a second material and the second material is different from the first material in at least one element.
    Type: Application
    Filed: December 6, 2012
    Publication date: June 6, 2013
    Applicant: Micronas GmbH
    Inventor: Micronas GmbH
  • MEMS DEVICE ETCH STOP
    Publication number: 20130140653
    Abstract: The present disclosure provides a micro-electro-mechanical systems (MEMS) device and a method for fabricating such a device. In an embodiment, a MEMS device includes a substrate, a dielectric layer above the substrate, an etch stop layer above the dielectric layer, and two anchor plugs above the dielectric layer, the two anchor plugs each contacting the etch stop layer or a top metal layer disposed above the dielectric layer. The device further comprises a MEMS structure layer disposed above a cavity formed between the two anchor plugs and above the etch stop layer from release of a sacrificial layer.
    Type: Application
    Filed: February 1, 2013
    Publication date: June 6, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Taiwan Semiconductor Manufacturing Company, Ltd.
  • Low Frequency CMUT with Vent Holes
    Publication number: 20130140654
    Abstract: A capacitive micromachined ultrasonic transducer (CMUT), which has a conductive structure that can vibrate over a cavity, has a number of vent holes that are formed in the bottom surface of the cavity. The vent holes eliminate the deflection of the CMUT membrane due to atmospheric pressure which, in turn, allows the CMUT to receive and transmit low frequency ultrasonic waves.
    Type: Application
    Filed: December 2, 2011
    Publication date: June 6, 2013
    Inventors: Steven Adler, Peter Johnson, Ira Oaktree Wygant
  • MEMS ACOUSTIC TRANSDUCER AND METHOD FOR FABRICATING THE SAME
    Publication number: 20130140655
    Abstract: A MEMS acoustic transducer is provided, which includes a substrate, a MEMS chip, and a housing. The substrate has a first opening area and a lower electrode layer disposed over a surface of the substrate, wherein the first opening area includes at least one hole allowing acoustic pressure to enter the MEMS acoustic transducer. The MEMS chip is disposed over the surface of the substrate, including a second opening area and an upper electrode layer partially sealing the second opening area, wherein the upper electrode layer and the lower electrode layer, which are parallel to each other and have a gap therebetween, form an induction capacitor. The housing is disposed over the MEMS chip or the surface of the substrate creating a cavity with the MEMS chip or the substrate. In addition, a method for fabricating the above MEMS acoustic transducer is also provided.
    Type: Application
    Filed: October 26, 2012
    Publication date: June 6, 2013
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventor: Industrial Technology Research Institute
  • MEMS Microphone And Method For Producing The MEMS Microphone
    Publication number: 20130140656
    Abstract: The invention relates to a method for producing a microphone, in which a transducer element (WE) is mounted on a carrier (TR); a cover is arranged over the transducer element (WE) and the carrier (TR) such that the transducer element (WE) is enclosed between the cover and the carrier (TR); a first sound inlet opening (SO1) is produced in the carrier (TR); a functional test of the microphone is carried out; the first sound inlet opening (SO1) is closed; and a second sound inlet opening (SO2) is created in the cover. The present invention further relates to a microphone resulting from the method, in which the first sound inlet opening (SO1) is prepared but closed.
    Type: Application
    Filed: July 7, 2011
    Publication date: June 6, 2013
    Applicant: EPCOS AG
    Inventors: Wolfgang Pahl, Hans Krueger, Gregor Feiertag, Alois Stelzl, Anton Leidl, Stefan Seitz
  • MAGNETIC MEMORY DEVICES INCLUDING FREE MAGNETIC LAYER HAVING THREE-DIMENSIONAL STRUCTURE
    Publication number: 20130140657
    Abstract: Magnetic memory devices including a free magnetic layer having a three-dimensional structure, include a switching device and a magnetic tunnel junction (MTJ) cell connected thereto. The MTJ cell includes a lower magnetic layer, a tunnel barrier layer, and a free magnetic layer, which are sequentially stacked. A portion of the free magnetic layer protrudes in a direction away from an upper surface of the tunnel barrier layer.
    Type: Application
    Filed: August 10, 2012
    Publication date: June 6, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-chul LEE, Kwang-seok KIM, Kee-won KIM, Young-man JANG, Ung-hwan PI
  • MEMORY ELEMENT AND MEMORY APPARATUS
    Publication number: 20130140658
    Abstract: A memory element includes a layered structure and a negative thermal expansion material layer. The layered structure includes a memory layer, a magnetization-fixed layer, and an intermediate layer. The memory layer has magnetization perpendicular to a film face in which a magnetization direction is changed depending on information, and includes a magnetic layer having a positive magnetostriction constant. The magnetization direction is changed by applying a current in a lamination direction of the layered structure to record the information in the memory layer. The magnetization-fixed layer has magnetization perpendicular to a film face that becomes a base of the information stored in the memory layer. The intermediate layer is formed of a non-magnetic material and is provided between the memory layer and the magnetization-fixed layer.
    Type: Application
    Filed: November 26, 2012
    Publication date: June 6, 2013
    Applicant: Sony Corporation
    Inventor: Sony Corporation
  • FLUX-CLOSED STRAM WITH ELECTRONICALLY REFLECTIVE INSULATIVE SPACER
    Publication number: 20130140659
    Abstract: Flux-closed spin-transfer torque memory having a specular insulative spacer is disclosed. A flux-closed spin-transfer torque memory unit includes a multilayer free magnetic element including a first free magnetic layer anti-ferromagnetically coupled to a second free magnetic layer through an electrically insulating and electronically reflective layer. An electrically insulating and non-magnetic tunneling barrier layer separates the free magnetic element from a reference magnetic layer.
    Type: Application
    Filed: January 24, 2013
    Publication date: June 6, 2013
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventor: SEAGATE TECHNOLOGY LLC
  • MAGNETIC MEMORY DEVICE AND MAGNETIC MEMORY
    Publication number: 20130140660
    Abstract: In a perpendicular magnetization domain wall motion MRAM in which the magnetizations of both ends of a magnetization free layer are pinned by magnetization pinned layers, the increase of a write current due to leakage magnetic field from the magnetization pinned layer is prevented. A first displacement is present between a first boundary line and a first vertical line, where a curve portion, which crosses a first magnetization free layer, of an outer circumferential line of a first magnetization pinned layer is the first boundary line, a segment which links a center of a magnetization free region and a center of a first magnetization pinned region is a first segment, and a segment, which is a vertical line of the first segment, and which comes in contact with the first boundary line is the first vertical line.
    Type: Application
    Filed: June 16, 2011
    Publication date: June 6, 2013
    Inventors: Shunsuke Fukami, Tetsuhiro Suzuki, Kiyokazu Nagahara, Nobuyuki Ishiwata, Norikazu Ohshima
  • PEROVSKITE MANGANESE OXIDE THIN FILM AND MANUFACTURING METHOD THEREFOR
    Publication number: 20130140661
    Abstract: A perovskite manganese oxide thin film formed on a substrate that allows a first order phase transition and has A-site ordering. The thin film contains Ba and a rare earth element in the A sites of a perovskite crystal lattice and has an (m10) orientation for which m=2n, and 9?n?1. A method for manufacturing the film includes forming in a controlled atmosphere using laser ablation an atomic layer or thin film that assumes a pyramidal structure having oxygen-deficient sites in a plane containing the rare earth element and oxygen; and filling the oxygen-deficient sites with oxygen. The controlled atmosphere has an oxygen partial pressure controlled to a thermodynamically required value for creating oxygen deficiencies and contains a gas other than oxygen, and has a total pressure that is controlled to a value at which the A sites have a fixed compositional ratio.
    Type: Application
    Filed: November 28, 2011
    Publication date: June 6, 2013
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Yasushi Ogimoto
  • PHOTODIODE DEVICE FOR IMPROVING THE DETECTIVITY AND THE FORMING METHOD THEREOF
    Publication number: 20130140662
    Abstract: A method for forming the photodiode device is provided. The method comprises providing a substrate, then a transparent conductive film is formed on the substrate. A conductive polymer is formed on the transparent conductive film. A photoactive layer is formed on the conductive polymer. A charge blocking layer is formed on the photoactive layer. Finally, a cathode metal is formed on the charge blocking layer.
    Type: Application
    Filed: May 8, 2012
    Publication date: June 6, 2013
    Applicant: National Chiao Tung University
    Inventors: Fang-Chung Chen, Shu-Cheng Lin
  • IMAGE SENSOR AND IMAGE CAPTURE APPARATUS
    Publication number: 20130140663
    Abstract: An image sensor in which each pixel includes a first sub-pixel including a first semiconductor layer, a second sub-pixel including a second semiconductor layer having a polarity different from a polarity of the first semiconductor layer, a third semiconductor layer having a polarity equal to the polarity of the first semiconductor layer, and a microlens, and which includes a plurality of pixels in which the first semiconductor is included in the second semiconductor layer, and the second semiconductor layer is included in the third semiconductor layer, wherein a center of gravity position of a light-receiving surface defining the first semiconductor layer is different from a center of gravity position of a light-receiving surface defining both the first semiconductor layer and the second semiconductor layer.
    Type: Application
    Filed: August 12, 2011
    Publication date: June 6, 2013
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Koichi Fukuda
  • FLIP CHIP PACKAGING STRUCTURE
    Publication number: 20130140664
    Abstract: The present invention discloses a flip chip packaging structure which is applied to a process of a compact camera module (CCM), and the structure thereof comprises an image sensor component, at least one connection member, a circuit board and an insulating plate. The image sensor component is electrically connected with the circuit board via an electrical-conduction of the connection body. Hence, by disposing the insulating plate between the image sensor component and the circuit board, the present invention not only can provide a thermal insulating protection to the image sensor component but also use enough space to execute a surface mount technology (SMT), so as to simplify the flip chip process and to increase the yield of manufacture.
    Type: Application
    Filed: December 2, 2011
    Publication date: June 6, 2013
    Applicant: Cheng Uei Precision Industry Co., LTD.
    Inventors: JUI-HSIANG LO, Tsung-shih Lee
  • SOLID STATE IMAGE PICKUP DEVICE AND CAMERA
    Publication number: 20130140665
    Abstract: A solid state image pickup device which can prevent color mixture by using a layout of a capacitor region provided separately from a floating diffusion region and a camera using such a device are provided. A photodiode region is a rectangular region including a photodiode. A capacitor region includes a carrier holding unit and is arranged on one side of the rectangle of the photodiode region as a region having a side longer than the one side. In a MOS unit region, an output unit region including an output unit having a side longer than the other side which crosses the one side of the rectangle of the photodiode region is arranged on the other side. A gate region and the FD region are arranged between the photodiode region and the capacitor region.
    Type: Application
    Filed: January 29, 2013
    Publication date: June 6, 2013
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: CANON KABUSHIKI KAISHA
  • SELF-ALIGNED IMPLANTS TO REDUCE CROSS-TALK OF IMAGING SENSORS
    Publication number: 20130140666
    Abstract: A method of preparing self-aligned isolation regions between two neighboring sensor elements on a substrate. The method includes patterning an oxide layer to form an opening between the two neighboring sensor elements on the substrate. The method further includes performing a first implant to form a deep doped region between the two neighboring sensor elements and starting at a distance below a top surface of the substrate. The method further includes performing a second implant to form a shallow doped region between the two neighboring sensor elements, wherein a bottom portion of the shallow doped region overlaps with a top portion of the deep doped region.
    Type: Application
    Filed: January 8, 2013
    Publication date: June 6, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Chi FU, Kai TZENG, Wen-Chen LU
  • LOCALIZED CARRIER LIFETIME REDUCTION
    Publication number: 20130140667
    Abstract: A semiconductor structure includes a substrate, a first power device and a second power device in the substrate, at least one isolation feature between the first and second power device, and a trapping feature adjoining the at least one isolation feature in the substrate.
    Type: Application
    Filed: December 1, 2011
    Publication date: June 6, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Alex KALNITSKY, Chih-Wen YAO, Jun CAI, Ruey-Hsin LIU, Hsiao-Chin TUAN
  • Forming Structures on Resistive Substrates
    Publication number: 20130140668
    Abstract: A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices.
    Type: Application
    Filed: December 6, 2011
    Publication date: June 6, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alan B. Botula, Renata Camillo-Castillo, James S. Dunn, Jeffrey P. Gambino, Douglas B. Hershberger, Alvin J. Joseph, Mark E. Stidham, Robert M. Rassel
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20130140669
    Abstract: A first MISFET which is a semiconductor element is formed on an SOI substrate. The SOI substrate includes a supporting substrate which is a base, BOX layer which is an insulating layer formed on a main surface (surface) of the supporting substrate, that is, a buried oxide film; and an SOI layer which is a semiconductor layer formed on the BOX layer. The first MISFET as a semiconductor element is formed to the SOI layer. In an isolation region, an isolation groove is formed penetrating though the SOI layer and the BOX layer so that a bottom surface of the groove is positioned in the middle of a thickness of the supporting substrate. An isolation film is buried in the isolation groove being formed. Then, an oxidation resistant film is interposed between the BOX layer and the isolation film.
    Type: Application
    Filed: December 2, 2012
    Publication date: June 6, 2013
    Applicant: Renesas Electronics Corporation
    Inventor: Renesas Electronics Corporation
  • STRUCTURE AND METHOD FOR REDUCTION OF VT-W EFFECT IN HIGH-K METAL GATE DEVICES
    Publication number: 20130140670
    Abstract: A substrate is provided. An STI trench is formed in the substrate. A fill material is formed in the STI trench and then planarized. The substrate is exposed to an oxidizing ambient, growing a liner at a bottom and sidewalls of the STI trench. The liner reduces the Vt-W effect in high-k metal gate devices.
    Type: Application
    Filed: February 5, 2013
    Publication date: June 6, 2013
    Applicant: International Business Machines Corporation
    Inventor: International Business Machines Corporation
  • COMPOUND SEMICONDUCTOR INTEGRATED CIRCUIT WITH THREE-DIMENSIONALLY FORMED COMPONENTS
    Publication number: 20130140671
    Abstract: The present invention relates to a compound semiconductor integrated circuit with three-dimensionally formed components, such as three-dimensionally formed bond pads or inductors, positioned above an electronic device. The dielectric layer inserted between the electronic device and the bond pads or inductors thereon has a thickness between 10 to 30 microns, so that it can effectively mitigate the effect of the structure on the device performance. A protection layer can be disposed to cover the electronic devices to prevent contamination from the bond pad or inductor material to the electronic device, and therefore the lower cost copper can be used as the bond pad and inductor material. The three-dimensional bond pad can be used in wire bonding or bump bonding technology.
    Type: Application
    Filed: December 6, 2011
    Publication date: June 6, 2013
    Applicant: WIN Semiconductors Corp.
    Inventor: Shinichiro TAKATANI
  • VARIABLE INDUCTOR AND SEMICONDUCTOR DEVICE USING SAME
    Publication number: 20130140672
    Abstract: A variable inductor includes a spiral inductor, a loop conductor, and a switch for opening or short-circuiting an end of the loop conductor. The loop conductor is formed in a direction perpendicular to the spiral inductor and is used for adjusting the inductance value of the spiral inductor by opening or short-circuiting the end of the loop conductor by the switch.
    Type: Application
    Filed: January 26, 2012
    Publication date: June 6, 2013
    Applicant: PANASONIC CORPORATION
    Inventors: Junji Sato, Koichi Mizuno, Suguru Fujita
  • MONOLITHIC SEMICONDUCTOR SWITCHES AND METHOD FOR MANUFACTURING
    Publication number: 20130140673
    Abstract: A semiconductor device and method are disclosed. One embodiment provides a semiconductor die with a first n-type channel FET and a second n-type channel FET. A source of the first n-type channel FET and a drain of the second n-type channel FET are electrically coupled to at least one contact area at a first side. A drain of the first n-type channel FET, a gate of the first n-type channel FET, a source of the second n-type channel FET and the gate of the second n-type channel FET are electrically coupled to contact areas at a second side. Contact areas of the first n-type channel FET and the second n-type channel FET are electrically separated from each other.
    Type: Application
    Filed: June 4, 2012
    Publication date: June 6, 2013
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Oliver Haeberlen, Walter Rieger, Martin Vielemeyer, Lutz Goergens, Martin Poelzl, Milko Paolucci, Johannes Schoiswohl, Joachim Krumrey
  • SEMICONDUCTOR DEVICE
    Publication number: 20130140674
    Abstract: A semiconductor device according to this invention includes a first power line that supplies power to a first circuit, a second power line that supplies power to a second circuit, and a capacitive element that is provided between the first power line and the second power line.
    Type: Application
    Filed: November 16, 2012
    Publication date: June 6, 2013
    Applicant: Elpida Memory, Inc.
    Inventor: Elpida Memory, Inc.
  • Method for ALD Deposition Rate Enhancement
    Publication number: 20130140675
    Abstract: A method for fabricating a dynamic random access memory (DRAM) capacitor includes forming a first electrode layer, forming a catalytic layer on the first electrode layer, optionally annealing the catalytic layer, forming a dielectric layer on the catalytic layer, optionally annealing the dielectric layer, forming a second electrode layer on the dielectric layer, and optionally annealing the capacitor stack. Advantageously, the electrode layers are TiN, the catalytic layer is MoO2?x where x is between 0 and 2, and the physical thickness of the catalytic layer is between about 0.5 nm and about 10 nm, and the dielectric layer is ZrO2.
    Type: Application
    Filed: January 10, 2013
    Publication date: June 6, 2013
    Applicant: INTERMOLECULAR, INC.
    Inventor: Intermolecular, Inc.
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME
    Publication number: 20130140676
    Abstract: A semiconductor device includes a substrate and a ferroelectric capacitor including a lower electrode, a ferroelectric film, and an upper electrode. The upper electrode includes a first layer formed of an oxide whose stoichiometric composition is expressed as AOx1 and whose actual composition is expressed as AOx2; a second layer formed on the first layer and formed of an oxide whose stoichiometric composition is expressed as BOy1 and whose actual composition is expressed as BOy2; and a metal layer formed on the second layer. The second layer is higher in ratio of oxidation than the first layer. The composition parameters x1, x2, y1, and y2 satisfy y2/y1>x2/x1, and the second layer includes an interface layer of the stoichiometric composition formed at an interface with the metal layer. The interface layer is higher in ratio of oxidation than the rest of the second layer.
    Type: Application
    Filed: February 1, 2013
    Publication date: June 6, 2013
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: FUJITSU SEMICONDUCTOR LIMITED
  • CAPACITOR STRUCTURES FOR SEMICONDUCTOR DEVICE
    Publication number: 20130140677
    Abstract: A semiconductor device comprising a semiconductor substrate and a composite capacitor structure on the semiconductor substrate, wherein the composite capacitor structure comprises a capacitor stack comprising a lower and an upper capacitor, respectively comprising first and second dielectric materials, wherein the first and second dielectric materials are different materials and/or have different thicknesses from each other. This can minimize the voltage dependence of the capacitance of the composite capacitor structure. It is also possible to provide a composite capacitor structure on the semiconductor substrate, wherein the composite capacitor structure comprises at least a first and a second capacitor stack, each comprising a lower and an upper capacitor. The capacitors can be MIM capacitors.
    Type: Application
    Filed: July 16, 2010
    Publication date: June 6, 2013
    Applicant: X-FAB SEMICONDUCTOR FOUNDRIES AG
    Inventors: Tsui Ping Chu, Peng Yang, Evie Siaw Hei Kho, Yong Kheng Ang, Swee Hua Tia
  • INSULATOR LAYER BASED MEMS DEVICES
    Publication number: 20130140678
    Abstract: The present invention relates to using an insulator layer between two metal layers of a semiconductor die to provide a micro-electromechanical systems (MEMS) device, such as an ohmic MEMS switch or a capacitive MEMS switch. In an ohmic MEMS switch, the insulator layer may be used to reduce metal undercutting during fabrication, to prevent electrical shorting of a MEMS actuator to a MEMS cantilever, or both. In a capacitive MEMS switch, the insulator layer may be used as a capacitive dielectric between capacitive plates, which are provided by the two metal layers. A fixed capacitive element may be provided by the insulator layer between the two metal layers. In one embodiment of the present invention, an ohmic MEMS switch, a capacitive MEMS switch, a fixed capacitive element, or any combination thereof may be integrated into a single semiconductor die.
    Type: Application
    Filed: January 25, 2013
    Publication date: June 6, 2013
    Applicant: RF MICRO DEVICES, INC.
    Inventor: RF Micro Devices, Inc.
  • SEMICONDUCTIVE CERAMIC SINTERED COMPACT
    Publication number: 20130140679
    Abstract: There is provided a semiconductive ceramic sintered compact that has a conductivity high enough to attain static electricity removal and antistatic purposes and, at the same time, has excellent mechanical properties or stability over time. The semiconductive ceramic sintered compact includes a main phase and a conductive phase present between the main phases, wherein the main phase is a ceramic sintered phase including Al2O3 particles, the area ratio of the conductive phase to the main phase is 0% (exclusive) to 10% (inclusive), and the conductive phase includes two or more metals selected from Mn (manganese), Fe (iron), and Ti (titanium) and has a composition meeting a relation of Mn/(Ti+Mn+Fe)>0.08 or Mn/Ti>0.15.
    Type: Application
    Filed: November 30, 2012
    Publication date: June 6, 2013
    Applicant: TOTO LTD.
    Inventor: TOTO LTD.
  • SEMICONDUCTOR DEVICE
    Publication number: 20130140680
    Abstract: A semiconductor device includes: an active region located in an upper portion of a semiconductor substrate; a through-hole electrode penetrating the substrate, and made of a conductor having a thermal expansion coefficient larger than that of a material for the substrate; and a stress buffer region located in the upper portion of the substrate and sandwiched between the through-hole electrode and the active region. The stress buffer region does not penetrate the substrate and includes a stress buffer part made of a material having a thermal expansion coefficient larger than that of the material for the substrate and an untreated region where the stress buffer part is not present. The stress buffer part is located in at least two locations sandwiching the untreated region in a cross section perpendicular to a surface of the substrate and passing through the through-hole electrode and the active region.
    Type: Application
    Filed: January 31, 2013
    Publication date: June 6, 2013
    Applicant: PANASONIC CORPORATION
    Inventor: PANASONIC CORPORATION
  • SUPERFILLED METAL CONTACT VIAS FOR SEMICONDUCTOR DEVICES
    Publication number: 20130140681
    Abstract: In accordance with one aspect of the invention, a method is provided for fabricating a semiconductor element having a contact via. In such method, a hole can be formed in a dielectric layer to at least partially expose a region including at least one of semiconductor or conductive material. A seed layer can be deposited over a major surface of the dielectric layer and over a surface within the hole. In one embodiment, the seed layer can include a metal selected from the group consisting of iridium, osmium, palladium, platinum, rhodium, and ruthenium. A layer consisting essentially of cobalt can be electroplated over the seed layer within the hole to form a contact via in electrically conductive communication with the region.
    Type: Application
    Filed: February 6, 2013
    Publication date: June 6, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: International Business Machines Corporation
  • BURIED WORD LINE AND METHOD FOR FORMING BURIED WORD LINE IN SEMICONDUCTOR DEVICE
    Publication number: 20130140682
    Abstract: A buried word line includes a substrate having thereon a recessed trench, an insulating layer on a bottom surface and a sidewall of the recessed trench, and a lining layer in the recessed trench. The lining layer has a cleaned surface that is cleaned by a cleaning solution comprising HF or H3PO4. A tungsten layer is selectively deposited on the cleaned surface of the lining layer.
    Type: Application
    Filed: December 1, 2011
    Publication date: June 6, 2013
    Inventors: Chi-Wen Huang, Kuo-Hui Su
  • Semiconductor Device and Method of Forming Cavity in Build-Up Interconnect Structure for Short Signal Path Between Die
    Publication number: 20130140683
    Abstract: In a semiconductor device, a first semiconductor die is mounted with its active surface oriented to a temporary carrier. An encapsulant is deposited over the first semiconductor die and temporary carrier. The temporary carrier is removed to expose a first side of the encapsulant and active surface of the first semiconductor die. A masking layer is formed over the active surface of the first semiconductor die. A first interconnect structure is formed over the first side of the encapsulant. The masking layer blocks formation of the first interconnect structure over the active surface of the first semiconductor die. The masking layer is removed to form a cavity over the active surface of the first semiconductor die. A second semiconductor die is mounted in the cavity. The second semiconductor die is electrically connected to the active surface of the first semiconductor die with a short signal path.
    Type: Application
    Filed: December 24, 2012
    Publication date: June 6, 2013
    Applicant: STATS CHIPPAC, LTD.
    Inventor: STATS CHIPPAC, LTD.
  • Semiconductor Device Assembly Utilizing a DBC Substrate
    Publication number: 20130140684
    Abstract: A semiconductor device package is formed of DBC in which thinned MOSgated and/or diode die are soldered to the bottom of an etched depression in the upper conductive layer. A via in the insulation layer of the DBC is filled with a conductive material to form a resistive shunt. Plural packages may be formed in a DBC card and may be separated individually or in clusters. The individual packages are mounted in various arrays on a support DBC board and heat sink. Integrated circuits may be mounted on the assembly and connected to the die for control of the die conduction.
    Type: Application
    Filed: February 1, 2013
    Publication date: June 6, 2013
    Applicant: International Rectifier Corporation
    Inventor: International Rectifier Corporation
  • Electronic Device and a Method for Fabricating an Electronic Device
    Publication number: 20130140685
    Abstract: The electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.
    Type: Application
    Filed: December 1, 2011
    Publication date: June 6, 2013
    Applicant: Infineon Technologies AG
    Inventors: Alexander Heinrich, Michael Juerss, Konrad Roesl, Oliver Eichinger, Kok Chai Goh, Tobias Schmidt
  • SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20130140686
    Abstract: A method of manufacturing a semiconductor package structure is provided. A heat-conductive block is adhered to a portion of a second surface of a conductive substrate via a first adhesive layer. An opening is formed by performing a half-etching process on a first surface of the conductive substrate. The remaining conductive substrate is patterned to form leads and expose a portion of the heat-conductive block. Each lead has a first portion and a second portion. A thickness of the first portion is greater than a thickness of the second portion. A first lower surface of the first portion and a second lower surface of the second portion are coplanar. A chip is disposed on the exposed portion of the heat-conductive block and electrically connected to the second portions of the leads. A first bottom surface of the heat-conductive block and a second bottom surface of a molding compound are coplanar.
    Type: Application
    Filed: October 9, 2012
    Publication date: June 6, 2013
    Applicant: CHIPMOS TECHNOLOGIES INC.
    Inventor: ChipMOS Technologies Inc.