Abstract: Disclosed is an organic light-emitting display device defined into a non-display area and a display area which is provided with pixels. Each of the pixels includes: first through fourth nodes; an organic light emission element connected to the fourth node; a drive transistor disposed between the second, third, and fourth nodes and configured to generate a drive current which drives the organic light emission element to emit light; a storage capacitor disposed between the first and third nodes; first through fifth transistors; wherein the fifth transistor is disposed between the second node with the non-display area and a reference voltage line and configured to control an initialization of the second node.

Abstract: An electro-optical device includes a first pixel circuit having a first light emitting element; a second pixel circuit having a second light emitting element arranged adjacent to the first light emitting element along a first direction; a first data line arranged along a second direction crossing the first direction, the first data line being electrically connected to the first pixel circuit; a second constant potential wiring line arranged along the second direction, the second constant potential wiring line being electrically connected to the second pixel circuit; a wiring line connected to the second constant potential wiring line. The first data line and the wiring line overlap when seen from a third direction perpendicular to the first direction and to the second direction.

Abstract: A host material is disclosed. The host material, as a compound which is represented by the following formula 1, has a chemical structure in which nitrogen and silicon atoms are chemically and directly bonded to each other. Wherein the “a” is one selected from a material group which includes N, S, O, SO2 and NSiG1G2G2, and the “G1, G2 and G3” each become one of a hydrogen, and aromatic, heterocyclic and aliphatic groups which are or not substituted, respectively.

Abstract: Articles utilizing strengthened glass substrates, for example, ion-exchanged glass substrates, in combination with organic molecules or polymers are described along with methods for making the articles. The articles are useful in electronics-based devices that utilize organic thin film transistors.

Abstract: The present invention provides a layer structure comprising a substrate (1), at least one LEC (7) (light emitting electrochemical cell) and at least one further electrotechnical structural element (4, 5, 8), a process for the production of this layer structure, and the use thereof in the production of small and large display and control elements and in the production of casing elements for mobile or stationary electronic devices or small or large household appliances or in the production of keyboard systems without moving components.

Abstract: An organic EL element comprises: an anode; a cathode; a functional layer including at least a light-emitting layer; a hole injection layer disposed between the anode and the functional layer; and a bank. The hole injection layer contains tungsten oxide. Tungsten atoms constituting the tungsten oxide include both tungsten atoms with a valence of six and tungsten atoms with a valence less than six. The hole injection layer includes a crystal of the tungsten oxide. A particle diameter of the crystal is on an order of nanometers. The hole injection layer has a recessed portion whose inner side surface has an upper edge that is one of (i) aligned with part of a lower edge of the bank, the part being in contact with the light-emitting layer, and (ii) in contact with a bottom surface of the bank.

Abstract: An organic EL element comprises: an anode; a cathode; a functional layer that is disposed between the anode and the cathode and includes at least a light-emitting layer; a hole injection layer disposed between the anode and the functional layer; and a bank. The hole injection layer contains tungsten oxide, and has a recessed portion. A UPS spectrum of the hole injection layer, obtained from a UPS measurement, has a protrusion appearing near a Fermi surface and within a region corresponding to a binding energy range lower than a top of a valence band. The tungsten oxide contained in the hole injection layer satisfies a condition, determined from an XPS measurement, that a ratio in a number density of atoms other than tungsten atoms and oxygen atoms to the tungsten atoms does not exceed approximately 0.83.

Abstract: This invention relates to deuterated indolocarbazole compounds that are useful in electronic applications. It also relates to electronic devices in which the active layer includes such a deuterated compound.

Abstract: A moisture absorption filling material for an organic light-emitting device may include a fibrous web structure including an assembly of fibers, the fibers including a binder resin and hygroscopic particles, the hygroscopic particles being secured into the fibers. A method of preparing a moisture absorption filling material for an organic light-emitting device may include electrospinning a mixture including about 10 wt % to about 60 wt % of hygroscopic particles and about 40 wt % to about 90 wt % of a binder.

Abstract: A hygroscopic filler for an organic EL getter, a method of manufacturing the same, and an organic EL device including the same, the hygroscopic filler including a sheet having pores; and a mixture of an organic binder and a hygroscopic material, the mixture being secured to the sheet.

Abstract: An organic light-emitting device including a barrier layer that includes a silicon oxide layer and a silicon-rich silicon nitride layer. The organic light-emitting device includes a flexible substrate that includes a barrier layer and plastic films disposed under and over the barrier layer. The barrier layer includes a silicon-rich silicon nitride layer and a silicon oxide layer. The order in which the silicon-rich silicon nitride layer and the silicon oxide layer are stacked is not limited and the silicon oxide layer may be first formed and then the silicon-rich silicon nitride layer may be stacked on the silicon oxide layer. The silicon-rich silicon nitride layer has a refractive index of 1.81 to 1.85.

Abstract: To provide an organic semiconductor composition that can exhibit a high carrier transport property and give uniform characteristics. An organic semiconductor composition characterized by containing a high molecular weight compound having a carrier transport property and a low molecular weight compound, in which the low molecular weight compound has a structure represented by Formula (1) and a content ratio of the low molecular weight compound is from 5 to 95 parts by mass relative to a total of 100 parts by mass of the high molecular weight compound and the low molecular weight compound, [where, E represents a sulfur atom or a selenium atom, three E's may be the same or may be different from one another, and an aromatic ring in Formula may have substituents].

Abstract: Novel organic compounds comprising a bicarbazole core are provided. In particular, the compounds has a 3,3?-bicarbazole core substituted at the 9-position with a triazine or pyrimidine. The compounds may be used in organic light emitting devices to provide devices having improved efficiency and improved lifetime.

Abstract: The present invention relates to an organic light-emitting element and a production method thereof. Specifically, the present invention relates to an organic light-emitting element, which has excellent productivity during mass production thereof and may allow simplification of vapor deposition equipment, and the like, and a production method thereof.

Abstract: A transistor may include a channel layer formed of an oxide semiconductor. The oxide semiconductor may include GaZnON, and a proportion of Ga content to a total content of Ga and Zn of the channel layer is about 0.5 to about 4.5 at %.

Abstract: A semiconductor device (100) according to the present invention includes: an oxide semiconductor layer (31) formed on an insulating layer (21), the oxide semiconductor layer (31) containing at least one element selected from the group consisting of In, Zn, and Sn; first and second sacrificial layers (41a) and (41b) formed, with an interspace from each other, on the oxide semiconductor layer (31); a second electrode (52a) formed in contact with an upper face of the first sacrificial layer (41a) and an upper face of the oxide semiconductor layer (31); and a third electrode (52b) formed in contact with an upper face of the second sacrificial layer (41b) and an upper face of the oxide semiconductor layer (31). The first and second sacrificial layers (41a) and (41b) contain an oxide having at least one element selected from the group consisting of Zn, Ga, Mg, Ca, and Sr.

Abstract: A highly reliable semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device is manufactured with a high yield, so that high productivity is achieved. In a semiconductor device including a transistor in which a source electrode layer and a drain electrode layer are provided over and in contact with an oxide semiconductor film, entry of impurities and formation of oxygen vacancies in an end face portion of the oxide semiconductor film are suppressed. This can prevent fluctuation in the electric characteristics of the transistor which is caused by formation of a parasitic channel in the end face portion of the oxide semiconductor film.

Abstract: A semiconductor device including a minute transistor with a short channel length is provided. A gate insulating layer is formed over a gate electrode layer; an oxide semiconductor layer is formed over the gate insulating layer; a first conductive layer and a second conductive layer are formed over the oxide semiconductor layer; a conductive film is formed over the first conductive layer and the second conductive layer; a resist mask is formed over the conductive film by performing electron beam exposure; and then a third conductive layer and a fourth conductive layer are formed over and in contact with the first conductive layer and the second conductive layer, respectively, by selectively etching the conductive film.

Abstract: Provided is a miniaturized transistor with stable and high electrical characteristics with high yield. In a semiconductor device including the transistor in which an oxide semiconductor film, a gate insulating film, and a gate electrode layer are stacked in this order, a first sidewall insulating layer is provided in contact with a side surface of the gate electrode layer, and a second sidewall insulating layer is provided to cover a side surface of the first sidewall insulating layer. The first sidewall insulating layer is an aluminum oxide film in which a crevice with an even shape is formed on its side surface. The second sidewall insulating layer is provided to cover the crevice. A source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor film and the second sidewall insulating layer.

Abstract: An array substrate includes a gate line on a substrate including a pixel region, the gate line extending in one direction; a gate electrode in the pixel region and extending from the gate line; a gate insulating layer on the gate line and the gate electrode; a data line on the gate insulating layer and crossing the gate line to define the pixel region; an oxide semiconductor layer on the gate insulating layer and having three ends, the oxide semiconductor layer corresponding to the gate electrode; an etch stopper on the oxide semiconductor layer to expose the three ends of the oxide semiconductor layer; a source electrode contacting two ends of the three ends of the oxide semiconductor layer and extending from the data line; and a drain electrode contacting one end of the three ends of the oxide semiconductor layer and spaced apart from the source electrode.

Abstract: To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed.

Abstract: Disclosed is a semiconductor device functioning as a multivalued memory device including: memory cells connected in series; a driver circuit selecting a memory cell and driving a second signal line and a word line; a driver circuit selecting any of writing potentials and outputting it to a first signal line; a reading circuit comparing a potential of a bit line and a reference potential; and a potential generating circuit generating the writing potential and the reference potential. One of the memory cells includes: a first transistor connected to the bit line and a source line; a second transistor connected to the first and second signal line; and a third transistor connected to the word line, bit line, and source line. The second transistor includes an oxide semiconductor layer. A gate electrode of the first transistor is connected to one of source and drain electrodes of the second transistor.

Abstract: An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.

Abstract: An intrinsic or substantially intrinsic semiconductor, which has been subjected to a step of dehydration or dehydrogenation and a step of adding oxygen so that the carrier concentration is less than 1×1012/cm3 is used for an oxide semiconductor layer of an insulated gate transistor, in which a channel region is formed. The length of the channel formed in the oxide semiconductor layer is set to 0.2 ?m to 3.0 ?m inclusive and the thicknesses of the oxide semiconductor layer and the gate insulating layer are set to 15 nm to 30 nm inclusive and 20 nm to 50 nm inclusive, respectively, or 15 nm to 100 nm inclusive and 10 nm to 20 nm inclusive, respectively. Consequently, a short-channel effect can be suppressed, and the amount of change in threshold voltage can be less than 0.5 V in the range of the above channel lengths.

Abstract: A p-type semiconductor layer containing a solid solution of NiO and ZnO as a principal component is joined to an n-type semiconductor layer containing ZnO as a principal component, and the p-type semiconductor layer contains a rare earth element R. The content of the rare earth element R is preferably 0.001 to 1 mole with respect to 100 moles of the principal component. Further, Y, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm and Yb can be used as the rare earth element, for example. An internal electrode 4 is preferably principally composed of a composite oxide containing the rare earth element R and Ni. Thereby, photoelectric conversion efficiency can be improved, and ultraviolet light can be directly detected as a photocurrent without externally disposing a power source circuit.

Abstract: A display substrate includes a gate line, a gate insulation layer, a data line, a switching element, a protection insulation layer, a gate pad portion and a data pad portion. The gate insulation layer is disposed on the gate line. The switching element is connected to the gate line and the data line. The protection insulation layer is disposed on the switching element. The gate pad portion includes a first gate pad electrode which makes contact with an end portion of the gate line through a first hole formed through the gate insulation layer, and a second gate pad electrode which makes contact with the first gate pad electrode through a second hole formed through the protection insulation layer. The data pad portion includes a data pad electrode which makes contact with an end portion of the data line through a third hole formed through the protection insulation layer.

Abstract: A system and method for plating a contact connected to a test pad is provided. An embodiment comprises inserting a blocking material into vias between the contact and the test pad. In another embodiment a blocking structure may be inserted between the contact and the test pad. In yet another embodiment a blocking layer may be inserted into a contact stack. Once the blocking material, the blocking structure, or the blocking layer have been formed, the contact may be plated, with the blocking material, the blocking structure, or the blocking layer reducing or preventing degradation of the test pad due to galvanic effects.

Abstract: Disclosed herein are various electrical test structures for evaluating semiconductor devices that employ high-k dielectrics and/or metal gate electrode structures. In one example, the test structure disclosed herein includes a first line formed over an isolation material, a first active region defined in a semiconducting substrate and a first extension formed over an isolation material, the first extension extending from a first side of the first line, wherein the first extension is positioned proximate the first active region and wherein the first line and the first extension are comprised of at least one of a high-k layer of insulating material or a metal layer.

Abstract: A semiconductor structure including a test structure for detection of a gap in a conductive layer of the semiconductor structure includes a semiconductor substrate; the test structure, the test structure being located on the semiconductor substrate, the test structure comprising a multilayer gate stack, wherein the multilayer gate stack includes a single conductive layer region including: a gate dielectric located on the semiconductor substrate; the conductive layer located on the gate dielectric; and an undoped amorphous silicon layer located on the conductive layer; and wherein the test structure is configured to detect the presence of the gap in the conductive layer.

Abstract: Methods for fabricating bipolar junction transistors with self-aligned emitter and extrinsic base, bipolar junction transistors made by the methods, and design structures for a BiCMOS integrated circuit. The bipolar junction transistor is fabricated using a sacrificial emitter pedestal that provides a sacrificial mandrel promoting self-alignment between the emitter and the extrinsic base. The sacrificial emitter pedestal is subsequently removed to open an emitter window extending to the intrinsic base. An emitter is formed in the emitter window that lands on the intrinsic base.

Abstract: Crack formation and propagation in a silicon substrate may be reduced by forming a crack reducing portion. The silicon substrate includes a silicon main portion and a silicon edge portion formed around the silicon main portion. The crack reducing portion is formed on the silicon edge portion of the silicon substrate such that the directions of crystal faces in the crack reducing portion are randomly oriented.

Abstract: An image detector comprises: an active matrix-type TFT array substrate having a pixel area, in which photoelectric conversion elements and thin film transistors are arranged in a matrix shape, a data line, and a bias line; a conversion layer, which is arranged on the TFT array substrate and converts radiation into light; and a conductive cover, which covers the conversion layer, wherein the conductive cover is adhered in an adhesion area in an upper layer than an area, in which at least one of the data line and the bias line extend from the pixel area to each of terminals, and wherein inorganic insulation films configured by at least two layers are formed between the at least one of the data line and the bias line and the adhesion area.

Abstract: A semiconductor device includes a first transistor which includes a first gate electrode below its oxide semiconductor layer and a second gate electrode above its oxide semiconductor layer, and a second transistor which includes a first gate electrode above its oxide semiconductor layer and a second gate electrode below its oxide semiconductor layer and is provided so as to at least partly overlap with the first transistor. In the semiconductor device, a conductive film serving as the second gate electrode of the first transistor and the second gate electrode of the second transistor is shared between the first transistor and the second transistor. Note that the second gate electrode not only controls the threshold voltages (Vth) of the first transistor and the second transistor but also has an effect of reducing interference of an electric field applied from respective first gate electrodes of the first transistor and the second transistor.

Abstract: A thin film transistor array panel includes an insulation substrate; a gate line on the insulation substrate; a gate insulating layer on the gate line; a data line on the gate insulating layer; a first insulating layer on the data line and including a first contact hole which exposes a portion of the data line; a first connection assistant member in the first contact hole; and further including a first field generating electrode on the first insulating layer. The first field generating electrode is in connection with the exposed portion of the data line through the first connection assistant member.

Abstract: In one embodiment, an array substrate for a flat display device includes a gate line extending in a first direction, a source line extending a in second direction orthogonally crossing the first direction. A switching element includes a semiconductor layer, a gate electrode electrically connected with the gate line, a source electrode electrically connected with the gate line in contact with the semiconductor layer and a drain electrode in contact with the semiconductor layer. An insulating film covers the source line and the switching element, and includes a contact hole exposing the drain electrode. A pixel electrode is formed on the insulating film. An insulating filling component is filled in the contact hole of the insulating film so as to be interposed between the drain electrode and the pixel electrode in a pixel in which the source line is short-circuited with the drain electrode.

Abstract: An array substrate having a wiring of a pad region formed without an insulating film or without an insulating film and an organic film to reduce abnormal operations due to an increase in resistance caused by a contact margin at a high temperature, and a method for manufacturing the same are provided. The array substrate includes: an insulating substrate including a pad region and a thin film transistor (TFT) formation region; a first electrode layer formed in the pad region of the substrate; and a second electrode formed on the first electrode layer in an overlapping manner.

Abstract: An object is to form a crystalline semiconductor film including a plurality of semiconductor regions with different average grain sizes by a simple manufacturing process. The surface of a crystalline silicon film 30b is irradiated with a laser beam 5, to crystallize the crystalline silicon film 30b. At this time, in the crystalline silicon film 30b below which a gate electrode 21 and a radiation portion 22 having a large area are provided, part of generated heat energy escapes to the radiation portion 22, and hence the crystalline silicon film 30b is insufficiently melted. For this reason, a formed first silicon region 30c1 has a large average grain size. On the other hand, in the crystalline silicon film 30b below which agate electrode 71 having a small area is provided, generated heat is resistant to escaping, and hence the crystalline silicon film 30b is completely melted. Thereby, the second silicon region 30c2 has a small average grain size.

Abstract: Embodiments of the present invention disclose a thin film transistor array substrate and a method for manufacturing the same and an electronic device.

Abstract: Herein disclosed a display apparatus including: a pixel array having a matrix of pixel circuits each including respective electrooptical elements for determining a display brightness level and respective drive circuits for driving the electrooptical elements; wherein adjacent two of the pixel circuits are paired with each other, and each of the drive circuits of the adjacent two pixel circuits includes at least one transistor having a low-concentration source/drain region or an offset region of an offset gate structure, the electrooptical elements and the drive circuits of the adjacent two pixel circuits being laid out such that a line interconnecting a drain region and a source region of the at least one transistor extends parallel to a direction of pixel columns of the pixel circuits of the pixel array.

Abstract: A semiconductor device, and a method for manufacturing the same, comprises a source/drain region formed using a solid phase epitaxy (SPE) process to provide partially isolated source/drain transistors. Amorphous semiconductor material at the source/drain region is crystallized and then shrunk through annealing, to apply tensile stress in the channel direction.

Abstract: A semiconductor device and a method for preparing the same that can solve crack of a semiconductor film, capacitance electrodes and the like due to stress when forming a source electrode and a drain electrode in a semiconductor device having a thin film transistor and a holding capacitance with three or more capacitance electrodes is provided. Before forming the source electrode and the drain electrode, a crystalline silicon film for relaxing the stress is formed, then a contact hole connecting to the semiconductor film of the thin film transistor is opened, and a metal film to be the source electrode and the drain electrode is formed.

Abstract: A circuit structure includes a substrate, an unintentionally doped gallium nitride (UID GaN) layer over the substrate, a donor-supply layer over the UID GaN layer, a gate structure, a drain, and a source over the donor-supply layer. A number of islands are over the donor-supply layer between the gate structure and the drain. The gate structure disposed between the drain and the source. The gate structure is adjoins at least a portion of one of the islands and/or partially disposed over at least a portion of at least one of the islands.

Abstract: A method of integrating benzocyclobutene (BCB) layers with a substrate is provided along with a corresponding device. A method includes forming a first BCB layer on the substrate and depositing a first metal layer on the first BCB layer and within vias defined by the first metal layer. The method also forms a second BCB layer on the first metal layer and deposits a second metal layer on the second BCB layer and within vias defined by the second metal layer. The second metal layer extends through the vias defined by the second metal layer to establish an operable connection with the first metal layer. The first and second metal layers are independent of an electrical connection to any circuit element carried by the substrate, but the first and second metal layers secure the second BCB layer to the underlying structure and reduce the likelihood of delamination.

Abstract: An optoelectronic component can be used for mixing electromagnetic radiation having different wavelengths, in particular in the far field. The optoelectronic component includes a carrier. A first semiconductor chip has a first radiation exit surface for emitting electromagnetic radiation in a first spectral range is provided on the carrier and a second semiconductor chip as a second radiation exit surface for emitting electromagnetic radiation in a second spectral range is provided on the carrier. A diffusing layer is provided on the radiation exit surfaces of the semiconductor chips which face away from the carrier.

Abstract: An optical device is provided. Multi-layer structures are disposed on a substrate, wherein each of the multi-layer structures is consisting of at least two insulated layers with different refractive indexes formed alternately. A buffer layer covers the multi-layer structures, so that said multi-layer structures are disposed between the buffer layer and the substrate, wherein said buffer layer is an un-doped GaN based semiconductor layer. A first conductive semiconductor layer is disposed on the buffer layer. An active layer is disposed on said first conductive semiconductor layer. A second conductive semiconductor layer is disposed on said active layer and a transparent conductive layer is disposed on said second conductive semiconductor layer.

Abstract: The present invention relates to a semiconductor device and a method for manufacturing the same. A RESURF layer (101) including a plurality of P-type implantation layers having a relatively low concentration of P-type impurity is formed adjacent to an active region (2). The RESURF layer (101) includes a first RESURF layer (11), a second RESURF layer (12), a third RESURF layer (13), a fourth RESURF layer (14), and a fifth RESURF layer (15) that are arranged sequentially from the P-type base (2) side so as to surround the P-type base (2). The second RESURF layer (12) is configured with small regions (11?) having an implantation amount equal to that of the first RESURF layer (11) and small regions (13?) having an implantation amount equal to that of the third RESURF layer (13) being alternately arranged in multiple.

Abstract: First, third, and fourth regions have a first conductivity type, and a second region has a second conductivity type. The second region is provided with a plurality of through holes exposing the first region. The third region includes a contact portion, a connecting portion, and a filling portion. The contact portion is in contact with a first portion of the second region. The connecting portion extends from the contact portion to each of the plurality of through holes in the second region. The filling portion fills each of the plurality of through holes in the second region. The fourth region, is provided on the first portion of the second region.

Abstract: Disclosed is a JBS diode wherein an increase in an on-voltage is suppressed by sufficiently spreading a current to the lower portion of a junction barrier (p+) region. The JBS diode has a structure, which has an n region having a relatively high concentration compared with the n? drift layer concentration, said n region being in the lower portion of the junction barrier (p+) region.

Abstract: A junction barrier Schottky (JBS) rectifier device and a method of making the device are described. The device comprises an epitaxially grown first n-type drift layer and p-type regions forming p+-n junctions and self-planarizing epitaxially over-grown second n-type drift regions between and, optionally, on top of the p-type regions. The device may include an edge termination structure such as an exposed or buried P+ guard ring, a regrown or implanted junction termination extension (JTE) region, or a “deep” mesa etched down to the substrate. The Schottky contact to the second n-type drift region and the ohmic contact to the p-type region together serve as an anode. The cathode can be formed by ohmic contact to the n-type region on the backside of the wafer. The devices can be used in monolithic digital, analog, and microwave integrated circuits.

Abstract: This silicon carbide semiconductor element includes: a body region of a second conductivity type which is located on a drift layer of a first conductivity type; an impurity region of the first conductivity type which is located on the body region; a trench which runs through the body region and the impurity region to reach the drift layer; a gate insulating film which is arranged on surfaces of the trench; and a gate electrode which is arranged on the gate insulating film. The surfaces of the trench include a first side surface and a second side surface which is opposed to the first side surface. The concentration of a dopant of the second conductivity type is higher at least locally in a portion of the body region which is located beside the first side surface than in another portion of the body region which is located beside the second side surface.