Abstract: The invention relates to an apparatus comprising a differential driver module configured to generate at least one differential signal having steep rise and fall times for at least partially reducing common-mode noise. The invention also relates to a method for causing the differential driver to generate the signal and a system comprising the differential driver and a conductor module for transmission of the generated differential signal. A computer program for performing the method and a computer-readable medium is also part of the invention.

Abstract: A dead time generation circuit includes a high-side control signal generation circuit and a low-side control signal generation circuit which are separate circuits. The high-side control signal generation circuit inverts a level of a high-side control signal from a driving prohibition level to a driving permission level when a time corresponding to a first clock number has elapsed in a state where a control signal keeps a first level after the control signal transitions from a second level to the first level. The low-side control signal generation circuit inverts a level of a low-side control signal from the driving prohibition level to the driving permission level when a time corresponding to a second clock number has elapsed in a state where the control signal keeps the second level after the control signal transitions from the first level to the second level.

Abstract: An asynchronous sampling frequency conversion device includes: a storage unit configured to store input digital signals; a data specifying unit configured to specify first data and second data based on a ratio of a sampling frequency of the input digital signal to a sampling frequency of an output digital signal, the first data being sampled at a sampling timing immediately before an ith (where i is a natural number) sampling timing of the output digital signal among the input digital signals stored in the storage unit, the second data being sampled at the sampling timing immediately after the ith sampling timing of the output digital signal; and an output data value calculator configured to calculate a value of ith data of the output digital signal based on the first data and the second data specified by the data specifying unit and the ratio.

Abstract: To provide a clock frequency divider circuit that generates a clock signal enabling an expected proper communication in communication with a circuit operating by a clock having a different frequency. A clock frequency division circuit according to the present invention generates an output clock signal obtained by dividing a frequency of an input clock signal into N/S by subtracting (S?N) clock pulses from S clock pulses of the input clock signal based on a frequency division ratio defined as N/S. The clock frequency division circuit generates a control signal used to preferentially subtract a clock pulse at a timing other than a communication timing of data communication performed by a target circuit using the output clock signal among S clock pulses of the input clock signal. Further, it generates the output clock signal by subtracting a clock pulse of the input clock signal according to the generated control signal.

Abstract: A power on reset (POR) circuit is provided. For the POR circuit, a PMOS transistor is coupled to a first voltage rail at its source. A drive circuit is coupled to the drain of the PMOS transistor and is configured to output a POR signal. A voltage divider is coupled between the drain of the PMOS transistor and the second voltage rail. A switch network is provided as well, which has first and second switches. The first switch is coupled between the gate of the PMOS transistor and the voltage divider, and the second switch is coupled between the gate of the PMOS transistor and the voltage divider. A controller is also coupled to control the first and second switches, wherein the first and second switches are complementary driven.

Abstract: A semiconductor integrated circuit includes a logic circuit having a plurality of operation modes, a power source circuit that generates a power source voltage to be supplied to the logic circuit, a power source wiring that couples the power source circuit and the logic circuit, and a charge control block that holds charges for controlling the voltage of the power source wiring. The power source circuit generates a first power source voltage for causing the logic circuit to operate in a computing mode and a second power source voltage for causing the logic circuit to operate in a sleep mode. The charge control block includes a capacitor, a first switch, and a voltage supply unit that supplies the second power source voltage or a third power source voltage lower than the second power source voltage, to the capacitor.

Abstract: The power-on reset circuit includes: a NMOS transistor having a source connected to a second power supply terminal and a gate connected to a drain thereof; a depletion-type NMOS transistor having a source connected to the drain of the NMOS transistor, a drain connected to a first power supply terminal and a gate connected to the second power supply terminal; a PMOS transistor having a source connected to the first power supply terminal, a gate connected to the drain of the NMOS transistor and a drain; a capacitor having one end connected to the drain of the PMOS transistor and the other end connected to the second power supply terminal; and a waveform shaping circuit having an input terminal connected to the drain of the PMOS transistor and an output terminal from which a power-on reset signal is output.

Abstract: A phase-locked loop system is provided. The system includes a charge pump, a voltage-controlled oscillator (VCO) and a bias converter. The charge pump outputs a control voltage according to a phase frequency detection signal, and generates an output current according to a bias signal. The VCO generates an output signal according to the control voltage. The bias converter is coupled between the VCO and the charge pump and for generating the bias signal according to the control voltage.

Abstract: Apparatuses and methods related to altering the timing of command signals for executing commands is disclosed. One such method includes calculating a forward path delay of a clock circuit in terms of a number of clock cycles of an output clock signal provided by the clock circuit and adding a number of additional clock cycles of delay to a forward path delay of a signal path. The forward path delay of the clock circuit is representative of the forward path delay of the signal path and the number of additional clock cycles is based at least in part on the number of clock cycles of forward path delay.

Abstract: A receiver circuit includes a buffering unit configured to buffer an input signal and generate a buffering signal; a variation detection unit configured to generate a control signal according to a level of a reference voltage; a driving unit configured to drive the buffering signal and generate an output signal; and a compensation unit configured to control a slew rate of the output signal in response to the control signal.

Abstract: The disclosure relates to a method for the scheduling and/or the operation of a system of at least two power supplies (11) providing DC pulses to a consumer (5), typically an electrostatic precipitator, wherein the power supplies (11) are energised by a common feeding (1). According to the proposed method one power supply (11) is defined to be the reference power supply, and the initial pulses of each further power supply (11) are shifted by controlled delays (?Pri) with respect to the pulses of the reference power supply so as to fill the gaps between the pulses of the reference power supply by the pulses of the further power supplies (11).

Abstract: A system and method for generating a power efficient clock gating network for a Very Large Scale Integration (VLSI) circuit. Statistical analysis is performed upon the activity of component registers of the circuit and registers having correlated toggling behavior are clustered into sets and provided with common clock gaters. The clock gating network may be generated independently from the logical structure of the circuit.

Abstract: A phase shifter with selectable phase shift and comprises a switchable phase shifting element that includes a first and second signal path coupled between an input and an output and providing a, respective, first and second phase shift for a signal coupled through the respective signal paths; a switch circuit for selecting between the first and second signal paths where the first and second signal paths and the switch circuit are configured to equalize the insertion loss for the first and second signal path, the phase shifter further including control circuit for controlling the switch circuit.

Abstract: An inductor architecture for resonant clock distribution networks is described. This architecture allows for the adjustment of the natural frequency of a resonant clock distribution network, so that it achieves energy-efficient operation at multiple clock frequencies. The proposed architecture exhibits no inductor overheads. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. Moreover, it is applicable to the binning of semiconductor devices according to achievable performance levels.

Abstract: The semiconductor integrated circuit includes a clock tree that transmits a clock signal to a plurality of tree branches, a plurality of pulse generators, and a plurality of pulse distribution networks. Each pulse generator generates a pulse in response to the clock signal transmitted through the tree branches. Each pulse distribution network is in communication with a pulse generator of the plurality of pulse generators, and is constructed and arranged to transmit the pulse generated by each pulse generator to a plurality of pulse sinks.

Abstract: An integrated circuit has a level shifter, a pull-circuit, and a voltage regulator. The level shifter and the pull-up circuit receive power from the same supply voltage. The voltage regulator changes the voltage level from the supply voltage to another voltage level used by the level shifter.

Abstract: An asynchronous level shifter electronic circuit including: a transmitter, which can be coupled to a first voltage and generates a communication signal; a receiver, which can be coupled to a second voltage; and a capacitive coupling stage, which receives the communication signal and supplies a corresponding filtered signal to the receiver. The receiver includes: a threshold device, which has an input terminal and an output terminal and switches an electrical quantity on the output terminal between a first value and a second value, as a function of corresponding transitions through a threshold of a first intermediate signal present on the input terminal, to generate a second intermediate signal; and a biasing circuit, which generates the first intermediate signal to have a d.c. component, which is a function of the second intermediate signal, and superposed on which is a variable component, which is a function of the filtered signal.

Abstract: The present invention relates to a radio frequency mixer circuit comprising a first terminal (102), a local oscillator terminal (103) and a second terminal (104); a wave propagation medium (105) having a first (105a) and second end (105b), where the mixer circuit further comprises a circulator (106) coupling together the first terminal (102), the first end (105a) of the wave propagation medium and the second terminal (104), a switching means (107) operable according to a signal coupled to the LO terminal (103), the switching means being coupled to the second end (105b) of the wave propagation medium for causing a reflection with unchanged voltage wave polarity when the switching means is in an open state, or a reflection with inverted voltage wave polarity when the switching means is in a closed state, at the second end of the wave propagation medium when a wave is travelling therein.

Abstract: An adjustable power splitter includes: a power divider with an input and a first and second divider output; a first adjustable phase shifter and first adjustable attenuator series coupled to the first divider output and providing a first power output; and a second adjustable phase shifter and second adjustable attenuator series coupled to the second divider output and providing a second power output.

Abstract: A semiconductor device prevents recognition failure in mutual recognition between a host and a device compliant with USB Specifications. The semiconductor device includes: an interterminal opening/closing section having a plurality of first conductivity type MOS transistors, the respective sources or drains of which are cascaded, in which the source or drain of a first-stage MOS transistor among the cascaded MOS transistors is used as a first terminal, the source or drain of a final-stage MOS transistor among the cascaded MOS transistors is used as a second terminal, and the respective gates of the cascaded MOS transistors receive a control signal for controlling the opening or short-circuiting between the first and second terminals; and a current bypass section that reduces a current flowing into either one connection node coupling the respective sources or drains of the cascaded MOS transistors.

Abstract: A driving circuit of a schottky type transistor includes an input terminal supplied with an input signal, and an output terminal connected to a gate of the schottky type transistor. The driving circuit outputs a first voltage lower than a breakdown voltage of the schottky type transistor to the output terminal at the time of rising of the input signal, and thereafter supplies a second voltage higher than the breakdown voltage to a resistance connected to the output terminal.

Abstract: A circuit includes a high-side switch, a low-side switch, a diode, a transformer having a primary winding and a secondary windowing, and an input connected to a first terminal of the primary winding. The high-side switch has a source, a gate connected to a drive source and a drain connected to a second terminal of the primary winding. The low-side switch has a source connected to ground, a gate connected to a drive source and a drain connected to the source of the high-side switch. The diode is connected between the gate of the high-side switch and the first terminal of the primary winding. The diode forms a current loop with the primary winding and the high-side switch to circulate current when low side switch is off until the high side switch turns off.

Abstract: A cascode switch includes a first power transistor configured to be coupled to a load and a second power transistor coupled in series with the first power transistor so that the second power transistor is between ground and the first power transistor. The second power transistor is operable to switch on and off responsive to a pulse source coupled to a gate of the second power transistor. The first power transistor is operable to switch on and off responsive to the same pulse source as the second power transistor or a DC source coupled to a gate of the first power transistor. Alternatively or in addition, a transistor device is coupled to the gate of the first power transistor and operable to actively turn off the first power transistor independent of the load current.

Abstract: The invention relates to a spring (1), in particular for a push button, for fixing to a carrier (2) and for registering a vertical force (F). The spring (3) is designed in such a way that when actuated it converts a vertical movement into a horizontal movement that can be detected by sensor means (4).

Abstract: An input apparatus includes a touch plate, a decoration layer, a film sensor, an electrode portion, a wire portion, and a guard layer. The touch plate is a basal plate for finger manipulation. The decoration layer is on a front side of the touch plate to decorate the front side. The film sensor is bonded to a rear side of the touch plate. The electrode portion is on the film sensor. The wire portion is on the film sensor and connected to the electrode portion to transmit a signal outputted from the electrode portion. The guard layer contains a guard layer formation material to suppress an electrostatic capacity between the finger and the wire portion. The guard layer formation material is combined into the decoration layer such that the decoration layer and the guard layer are provided as a single integrated member.

Abstract: An electronic switch, or an electronic equipment having such switch that has a tap-sensing detection region for a user to perform finger-tapping, foot-tapping, or other finger movements on a contact surface in this region and effectuate sending of a signal to turn on, turn off, or perform other contemplated functions of the electronic equipment. This switch emits a radiation, such as infrared light, towards the detection region. The reflection of the radiation off of an object is collected and compared to a predetermined value. If there is a match, the switch would send a signal to the device to perform the predetermined function. In operation, the switch would allow an electrical equipment to have a “virtual switch” where the user can control the device by manipulating his finger or his foot in the designated detection region. The equipment may optionally have a LED illuminator to shine a lit marking indicating where the contact surface is and how it is to be used.

Abstract: One embodiment of the present invention sets forth a mechanism for transmitting and receiving differential signals. A transmitter combines a direct current (DC) to DC converter including a capacitor with a 2:1 multiplexer to drive a pair of differential signaling lines. The transmitter drives a pair of voltages that are symmetric about the ground power supply level. Signaling currents are returned to the ground plane to minimize the generation of noise that is a source of crosstalk between different differential signaling pairs. Noise introduced through the power supply is correlated with the switching rate of the data and may be reduced using an equalizer circuit.

Abstract: Apparatuses, multi-chip modules, capacitive chips, and methods of providing capacitance to a power supply voltage in a multi-chip module are disclosed. In an example multi-chip module, a signal distribution component may be configured to provide a power supply voltage. A capacitive chip may be coupled to the signal distribution component and include a plurality of capacitive units. The capacitive chip may be configured to provide a capacitance to the power supply voltage. The plurality of capacitive units may be formed from memory cell capacitors.

Abstract: A signal processing circuit of the present invention includes: first and second input terminals; an output terminal; a bootstrap capacitor; a first output section connected to the second input terminal and the output terminal; a second output section connected to the first input terminal, a first power source, and the output terminal; an electric charge control section for controlling the electric charge of the bootstrap capacitor, the electric charge control section being connected to the first input terminal; and a resistor having (i) a first end connected to the output terminal and (ii) a second end connected to a second power source. This arrangement allows the signal processing circuit to maintain an output potential even after a bootstrap effect has worn off.

Abstract: An apparatus includes a biquad filter having first and second lossy integrators and multiple input networks. Each lossy integrator includes an amplifier, and each input network is coupled to an input of the amplifier in one of the lossy integrators. Each input network includes multiple resistors and a capacitor arranged in a T-structure. In a single-ended configuration, each input network includes a grounded capacitor. In a fully-differential configuration, each input network includes one of: a grounded capacitor and a floating capacitor coupled to another input network. The amplifiers and resistors could form a portion of an integrated circuit chip, which also includes multiple input/output pins. A single grounded capacitor could be coupled to a single input/output pin of the integrated circuit chip for an input network. A single floating capacitor could be coupled to two input/output pins of the integrated circuit chip for a pair of input networks.

Abstract: A semiconductor device includes a regulator including an operational amplifier configured of a current mirror and generating the second voltage V2 from a first voltage V1; and a control circuit that generates the current control signal OVDR, makes a current that is flowed by the current mirror increase by a first transition of the current control signal OVDR, and makes the current that is flowed by the current mirror decrease by a second transition of the current control signal OVDR. The control circuit includes a slew-rate processing unit that makes a second slew rate of the current control signal OVDR related to the second transition be smaller than a first slew rate of the current control signal OVDR related to the first transition.

Abstract: An envelope detection apparatus dynamically controlled in response to an input signal and an envelope detection method thereof are provided. The envelope detection apparatus includes an envelope detector configured to output an envelope of an input signal. The envelope detection apparatus further includes a detection band determination unit configured to determine a detection band based on the input signal. The envelope detection apparatus further includes a detection band controller configured to control a detection band of the envelope detector based on the determined detection band.

Abstract: The present invention allows amplification with low distortion and high efficiency. A power amplifier of the present invention comprises signal conversion means which generates a digital signal and an analog signal from an input signal that is an amplification target based on a signal generation parameter, a switching amplifier which amplifies the digital signal, a linear amplifier which amplifies the analog signal, and DC level detection means which detect a DC level of at least one of the signal amplified by the linear amplifier and the amplified signal and output a detection result to the signal conversion means, wherein the signal conversion means adjust the signal generation parameter so that the DC level inputted by the DC level detection means is virtually equal to zero.

Abstract: A signal processing apparatus includes a corrector that corrects a digital signal in accordance with a correction value, a converter that converts the digital signal corrected by the corrector into an analog signal, a sample-and-hold unit that holds an instantaneous value of the analog signal that has been obtained by the converter and that has been amplified by an amplifier for a certain frequency that is smaller than twice a maximum frequency of the analog signal, a digitizer that converts the instantaneous value held by the sample-and-hold unit into a digital value when the digitizer received an operation clock having the certain frequency, and an updater that updates, on the basis of the digital value obtained by the digitizer, the correction value of the corrector such that the correction value becomes a correction value that reduces nonlinear distortion in the analog signal amplified by the amplifier.

Abstract: A differential amplifier circuit includes a differential operational amplifier that includes a differential pair circuit and operates based on a constant bias current supplied from a bias current source circuit, and the differential amplifier circuit includes a bias current generator circuit. A current monitor circuit detects two currents flowing through the differential pair circuit in correspondence with differential input voltages inputted to the differential pair circuit, and detect a minimum current of the two currents for a difference voltage of the differential input voltages as a monitored current. A current comparator circuit compares the monitored current with the constant bias current.

Abstract: A method including receiving an input signal; amplifying the input signal to generate an output signal using a cascade of a plurality of amplifier stages including a first amplifier stage and a last amplifier stage; generating a voltage signal by sensing the output signal in a noninvasive manner so that the sensing results in substantially no change to the output signal; generating a current signal from the voltage signal using a transconductance amplifier; and injecting the current signal into an output node of the first amplifier stage in a noninvasive manner so that the injecting results in substantially no change to an amplification function of the first amplifier stage.

Abstract: An automatic gain control device includes: a variable gain adjusting unit, for adjusting an input signal by a variable gain and outputting an adjustment result; an analog-digital converting unit, for performing analog-digital conversion on the adjustment result to obtain an analog-digital conversion result; and a gain determining unit, for determining a distribution status over a predetermined period of time of a maximum or a minimum of the analog-digital conversion result, comparing the distribution status with a first distribution condition, and if the distribution status meets the first distribution condition, then keeping the variable gain unchanged, otherwise changing the variable gain and determining newly a distribution status until the newly determined distribution status meets a second distribution condition which is at least as strict as the first distribution condition.

Abstract: A multi-stage amplifier is provided that uses tunable transmission lines, as well as a calibration method for the multi-stage amplifiers. A multi-stage amplifier, comprises a plurality of tunable amplification stages, wherein each of the tunable amplification stages comprises a tunable resonator based on a transmission line having a tunable element. The tunable elements may vary a capacitance or an inductance to tune a frequency of an applied signal. A calibration method is provided for a multi-stage amplifier having a plurality of transmission lines, an input stage and an output stage. The multi-stage amplifier is calibrated by generating a signal to determine a frequency for a substantially maximum power; generating an error signal by comparing the frequency for the substantially maximum power with a desired frequency; varying a digital control code applied to each of the tunable transmission lines, input stage and output stage until the error signal satisfies predefined criteria.

Abstract: In one embodiment, a voltage-controlled oscillator (VCO) is provided that includes: a plurality of differential inverters coupled to form a loop, each differential inverter having a differential pair of transistors configured to steer a tail current from a current source, the current source sourcing the tail current responsive to a bias voltage, wherein each transistor in the differential pair couples to a power source through a corresponding switching-capacitor circuit; and a bias circuit configured to generate the bias voltage such that a transconductance for each transistor in the differential pairs is proportional to a factor that is a function of a ratio of transistor widths within the bias circuit.

Abstract: In one embodiment, one or more circuits convert an n-bit control code of a phase interpolator to a coupling control signal of k-bit wide. The one or more circuits couple one or more output signals of the phase interpolator to a reference clock of the phase interpolator based on the coupling control signal.

Abstract: According to the invention there is provided a method of producing an output signal including the steps of: providing an electronic oscillator having a switching arrangement allowing the oscillator to be switched between at least a first configuration having an associated first oscillator frequency and period, and a second configuration having an associated second oscillator frequency and period, and a control arrangement for controlling the switching arrangement; dithering the oscillator between at least the first configuration and the second configuration to produce the output signal, having an intermediate frequency and period, in which the dithering is performed by switching from the first configuration to the second configuration for a pre-determined subset of each output signal period over successive cycles of the output signal frequency.

Abstract: Embodiments of the present invention provide improved systems and methods for external frit mounted components on a sensor device. In one embodiment, a method for fabricating a sensor device comprises securing at least one component stack on a sensor body over at least one opening in the sensor body, wherein the at least one component stack comprises a plurality of components and applying a frit to the plurality of components in the at least one component stack and the sensor body. The method further comprises heating the frit, the at least one component stack, and the sensor body such that the frit melts and cooling the frit, the at least one component stack, and the sensor body such that the at least one component stack is secured to the sensor body.

Abstract: A clock distributor includes unit circuit parts each including an oscillator, a first element configured to convert output voltage of the oscillator into a current, a second element having a voltage current conversion characteristic of an opposite phase to that of the first element, the second element being feedback connected to the first element and the oscillator, a third element configured to convert output voltage of the oscillator into a current, a fourth element having a voltage current conversion characteristic of an opposite phase to that of the third element, the fourth element being feedback connected to the third element and the oscillator; a wiring part to connect a connection part of the first and second elements of a unit circuit part to a connection part of the third and fourth elements of another unit circuit part; and a synchronization circuit connected to the oscillator of a unit circuit part.

Abstract: Doubly-clamped nanowire electromechanical resonators that can be used to generate parametric oscillations and feedback self-sustained oscillations. The nanowire electromechanical resonators can be made using conventional NEMS and CMOS fabrication methods. In very thin nanowire structures (sub-micron-meter in width), additive piezoresistance patterning and fabrication can be highly difficult and thus need to be avoided. This invention shows that, in piezoresistive nanowires with homogeneous material composition and symmetric structures, no conventional and additive piezoresistance loops are needed. Using AC and DC drive signals, and bias signals of controlled frequency and amplitude, output signals having a variety of frequencies can be obtained. Various examples of such resonators and their theory of operation are described.

Abstract: A vibrator element includes: a base having a mounting surface; a vibrating arm which is extended from the base and has a first surface and a second surface that faces the first surface and is positioned on the mounting surface side, and which performs flexural vibration in a direction normal to the first and second surfaces; and a laminated structure which is provided on at least one of the first and second surfaces of the vibrating arm, and which includes at least a first electrode, a second electrode, and a piezoelectric layer disposed between the first and second electrodes, in which the vibrating arm is warped toward the mounting surface side.

Abstract: A variable capacitor is provided. The variable capacitor includes a plurality of capacitor segments. The plurality of capacitor segments are connected in parallel within the variable capacitor. When a plurality of candidate capacitances allowable to the variable capacitor according to a connection state of the plurality of capacitor segments connected in parallel are sorted in a magnitude sequence, the plurality of candidate capacitances form a geometric series. The variable capacitor is used for a Voltage Controlled Oscillator (VCO), and the VCO is used for a Phase Locked Loop (PLL).

Abstract: Analog-to-digital pulse width modulation circuitry includes thermometer code generator circuitry, clock generator circuitry, delay selection circuitry, and an output stage. The thermometer code generator circuitry is adapted to generate a digital thermometer code based upon a received analog input voltage. The clock generator circuitry is adapted to generate a reference clock and a plurality of delayed clock signals. The delay selection circuitry is connected between the thermometer code generator circuitry and the clock generator circuitry, and is adapted to select one of the delayed clock signals to present to the output stage based upon the generated thermometer code. The selected delayed clock signal is delayed by an amount of time that is proportional to the generated thermometer code. The reference clock signal and the selected delayed clock signal are delivered to the output stage where they are used to generate a pulse width modulated output signal.

Abstract: Apparatus for receiving and transmitting electromagnetic signals are disclosed herein. In some embodiments, an apparatus includes a positive refractive index (PRI) medium; a negative refractive index (NRI) medium having a first side and a second side disposed in the PRI medium; a plurality of first transmission lines, each first transmission line having a first end extending toward the first side of the NRI medium; and a plurality of second transmission lines, each second transmission line having a second end extending toward the second side of the NRI medium, wherein a plurality of electromagnetic signals travelling in a first direction, enters the PRI medium and travels along the plurality of first transmissions lines and exits into first side of the NRI medium, passes through the NRI medium and exits through the second side of the NRI medium into the PRI medium along a first one of the second transmission lines.

Abstract: A circuit can include multiple data input ports and data output ports, pickoff tees coupled therebetween, and a resistive network coupled between the pickoff tees. A differential signal generator can be coupled with the resistive network and the pickoff tees. Resistances of the pickoff tees and resistive network can be selected such that impedances looking into the data input ports and data output ports are matched to a desired system impedance.

Abstract: An output circuit with an integrated directional coupler and impedance matching circuit is disclosed. In an exemplary design, an apparatus includes a switchplexer and an output circuit. The switchplexer is coupled to at least one power amplifier. The output circuit is coupled to the switchplexer and a load (e.g., an antenna) and includes a directional coupler and an impedance matching circuit sharing at least one inductor. The output circuit performs impedance matching for the load. The output circuit also acts as a directional coupler and provides an input radio frequency (RF) signal as an output RF signal and further couples a portion of the input RF signal as a coupled RF signal. Reusing the at least one inductor for both the directional coupler and the impedance matching circuit may reduce circuitry, size, and cost of the wireless device and may also improve performance.