Abstract: In one embodiment, a semiconductor device includes a resistor element and a stacked-gate type memory cell transistor. The resistor element includes a first conductive layer which is formed on a second conductive layer via a first insulating layer, and is electrically connected to an interconnect, the second conductive layer being on a substrate and in a floating state. The stacked-gate type memory cell transistor is on the substrate, and includes a floating gate formed of the same material as the second conductive layer.

Abstract: In a method of making a semiconductor device, a gate dielectric is formed over the semiconductor body. A floating gate is formed over the gate dielectric, an insulating region over the floating gate, and a control gate over the insulating region. The gate dielectric, floating gate, insulating region, and control gate constitute a gate stack. A stress is caused in the gate stack, whereby the band gap of the gate dielectric is changed by the stress.

Abstract: An dielectric film is formed above the semiconductor substrate. A first conductive layer is formed in the dielectric film and extending in a first direction. The first conductive layer is connected to a first select transistor. A second conductive layer formed in the dielectric film and extending in the first direction. The second conductive layer is connected to a second select transistor. A semiconductor layer is connected to both the first and second conductive layers and functioning as a channel layer of a memory transistor. A gate-insulating film is formed on the semiconductor layer. The gate-insulating film includes a charge accumulation film as a portion thereof. A third conductive layer is surrounded by the gate-insulating film.

Abstract: A semiconductor device includes an isolation region (11a) formed in a semiconductor substrate (10), an active region made of the semiconductor substrate (10) surrounded by the isolation region (11a) and having a trench portion, a MIS transistor of a first-conductivity type having a gate electrode (13) formed on the active region, a first sidewall (19) formed on a side surface of the gate electrode between the gate electrode (13) and the trench portion as viewed in the top, and a silicon mixed crystal layer (21) of the first-conductivity type, the trench portion being filled with the silicon mixed crystal layer (21) of the first-conductivity type, a substrate region provided between the trench portion and the isolation region (11a, 11b) and made of the semiconductor substrate (10), and an impurity region (22) of the first-conductivity type formed in the substrate region. The silicon mixed crystal layer (21) generates stress in a channel region of the active region.

Abstract: A semiconductor device includes a plurality of trenches including active gate trenches in an active area and gate runner/termination trenches and shield electrode pickup trenches in a termination area outside the active area. The gate runner/termination trenches include one or more trenches that define a mesa located outside an active area. A first conductive region is formed in the plurality of trenches. An intermediate dielectric region and termination protection region are formed in the trenches that define the mesa. A second conductive region is formed in the portion of the trenches that define the mesa. The second conductive region is electrically isolated from the first conductive region by the intermediate dielectric region. A first electrical contact is made to the second conductive regions and a second electrical contact to the first conductive region in the shield electrode pickup trenches. One or more Schottky diodes are formed within the mesa.

Abstract: Provided is a semiconductor device which is capable of preventing an increase in power consumption of an SGT, i.e., a three-dimensional semiconductor transistor, due to an increase in off-leak current. The semiconductor device comprises: a first-conductive type first silicon pillar: a first dielectric surrounding a side surface of the first silicon pillar; a gate surrounding the dielectric; a second silicon pillar provided underneath the first silicon pillar; and a third silicon pillar provided on a top of the first silicon pillar. The second silicon pillar has a second-conductive type high-concentration impurity region formed in a surface thereof except at least a part of a contact surface region with the first silicon pillar, and a first-conductive type impurity region formed therein and surrounded by the second-conductive type high-concentration impurity region.

Abstract: A semiconductor substrate capable of detecting operating current of a MOSFET and diode current in a miniaturized MOSFET such as a trench-gate type MOSFET is provided. A semiconductor substrate includes a main current region and a current sensing region in which current smaller than main current flowing in the main current region flows. The main current region has a source electrode disposed on a main surface, the source electrode being in contact with a p-type semiconductor region (body) and an n+-type semiconductor region (source), and the current sensing region has a MOSFET current detecting electrode and a diode current detecting electrode on a main surface, the MOSFET current detecting electrode being in contact with the p-type semiconductor region (body) and the n+-type semiconductor region (source), the diode current detecting electrode being in contact with the p-type semiconductor region (body).

Abstract: According to an embodiment, a semiconductor device includes a semiconductor layer of a first conductive type, a base region of a second conductive type provided on the semiconductor layer and a first contact region of a second conductive type provided on the base region. The device includes a gate electrode provided in a trench piercing through the first contact region and the base region, and an interlayer insulating film provided on the gate electrode and containing a first conductive type impurity element. The device further includes a source region of a first conductive type provided between the interlayer insulating film and the first contact region, the source region being in contact with a side face of the interlayer insulating film and extending in the base region.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate and a first semiconductor element provided on the semiconductor substrate. The first semiconductor element includes: a first semiconductor; a second semiconductor layer; a third semiconductor layer; a first insulating layer; a first base region; a first source region; a first gate electrode; a first drift layer; a first drain region; a first source; and a first drain electrode. A concentration of an impurity element of the first conductivity type included in the first drift layer is lower than a concentration of an impurity element of the first conductivity type included in the first semiconductor layer. The concentration of the impurity element of the first conductivity type included in the first drift layer is higher than a concentration of an impurity element of the first conductivity type included in the second semiconductor layer.

Abstract: An integrated circuit includes a semiconductor carrier including a first side and a second side opposite the first side. An FET is in a first area of the semiconductor carrier, and has a drain electrically coupled to a drain contact area at the first side and a source electrically coupled to a source contact area at the second side. First circuit elements are in a second area of the semiconductor carrier. The second area is electrically insulated from the semiconductor carrier surrounding the second area via a trench insulation extending through the semiconductor carrier from the first side to the second side. An interconnection level electrically interconnects the first circuit elements at the second side, and is electrically insulated from the source contact area in the entire second area via an insulating layer at the second side.

Abstract: A low cost integration method for a plurality of deep isolation trenches on the same chip is provided. The trenches have an additional n-type or p-type doped region surrounding the trench—silicon interface. Providing such variations of doping the trench interface is achieved by using implantation masking layers or doped glass films structured by a simple resist mask. By simple layout variation of the top dimension of the trench various trench depths at the same time can be ensured. Using this method, wider trenches will be deeper and smaller trenches will be shallower.

Abstract: A body layer of a first conductivity type is formed on a semiconductor substrate, and a source layer of a second conductivity type is formed in a surface region of the body layer. An offset layer of the second conductivity type is formed on the semiconductor substrate, and a drain layer of the second conductivity type is formed in a surface region of the offset layer. An insulating film is embedded in a trench formed in the surface region of the offset layer between the source layer and the drain layer. A gate insulating film is formed on the body layer and the offset layer between the source layer and the insulating film. A gate electrode is formed on the gate insulating film. A first peak of an impurity concentration profile in the offset layer is formed at a position deeper than the insulating film.

Abstract: Provided is a III nitride semiconductor electronic device having a structure capable of reducing leakage current. A laminate 11 includes a substrate 13 and a III nitride semiconductor epitaxial film 15. The substrate 13 is made of a III nitride semiconductor having a carrier concentration of more than 1×1018 cm?3. The epitaxial structure 15 includes a III nitride semiconductor epitaxial film 17. A first face 13a of the substrate 13 is inclined at an angle ? of more than 5 degrees with respect to an axis Cx extending in a direction of the c-axis. A normal vector VN and a c-axis vector VC make the angle ?. The III nitride semiconductor epitaxial film 17 includes first, second and third regions 17a, 17b and 17c arranged in order in a direction of a normal to the first face 13a. A dislocation density of the third region 17c is smaller than that of the first region 17a. A dislocation density of the second region 17b is smaller than that of the substrate 13.

Abstract: It is disclosed a semiconductor transistor, comprising a semiconductor substrate (111) in which a channel region (115) and a drain extension region (119) connected to the channel region are provided; a gate electrode (127) configured to provide an electric field for influencing the channel region; a first electrically conductive shield element (131) extending in a horizontal direction (103) parallel to a main surface of the semiconductor substrate and being arranged beside the gate electrode spaced apart from the drain extension region in a vertical direction (105) perpendicular to the horizontal direction; and a second electrically conductive shield element (133) arranged spaced apart from the first shield element in the vertical direction, wherein the gate electrode protrudes over the first shield element in the vertical direction.

Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of deep trenches. The deep trenches are filled with an epitaxial layer thus forming a top epitaxial layer covering areas above a top surface of the deep trenches covering over the semiconductor substrate. The semiconductor power device further includes a plurality of transistor cells disposed in the top epitaxial layer whereby a device performance of the semiconductor power device is dependent on a depth of the deep trenches and not dependent on a thickness of the top epitaxial layer. Each of the plurality of transistor cells includes a trench DMOS transistor cell having a trench gate opened through the top epitaxial layer and filled with a gate dielectric material.

Abstract: This document discusses, among other things, a semiconductor device including a first metal layer coupled to a source region and a second metal layer coupled to a gate structure, wherein at least a portion of the first and second metal layers overlap vertically.

Abstract: This document discusses, among other things, a semiconductor device including first and second conductive layers, the first conductive layer including a gate runner and a drain contact and the second conductive layer including a drain conductor, at least a portion of the drain conductor overlying at least a portion of the gate runner. A first surface of the semiconductor device can include a gate pad coupled to the gate runner and a drain pad coupled to the drain contact and the drain conductor.

Abstract: A semiconductor device includes a source, a drain, and a gate configured to selectively enable a current to pass between the source and the drain. The semiconductor device includes a drift zone between the source and the drain and a first field plate adjacent the drift zone. The semiconductor device includes a dielectric layer electrically isolating the first field plate from the drift zone and charges within the dielectric layer close to an interface of the dielectric layer adjacent the drift zone.

Abstract: An integrated circuit structure includes a semiconductor substrate including an active region. A first shallow trench isolation (STI) region adjoins a first side of the active region. A gate electrode of a MOS device is over the active region and the first STI region. A source/drain stressor region of the MOS device includes a portion in the semiconductor substrate and adjacent the gate electrode. A trench is formed in the semiconductor substrate and adjoining a second side of the active region. The trench has a bottom no lower than a bottom of the source/drain region. An inter-layer dielectric (ILD) extends from over the gate electrode to inside the trench, wherein a portion of the ILD in the trench forms a second STI region. The second STI region and the source/drain stressor region are separated from each other by, and adjoining, a portion of the semiconductor substrate.

Abstract: A level shifter circuit for integrated circuits has one or more inputs that operate in a first voltage domain, and a signal output that operates in a second voltage domain. In some embodiments, the level shifter circuit receives two complementary input signals. The level shifter uses cross-coupled PMOS transistors with drain-bulk breakdown voltage less than the gate-oxide breakdown voltage of high-voltage PMOS transistors to prevent gate-oxide breakdown caused by sub-threshold leakage of auxiliary high-voltage PMOS transistors in the off state. Permanent gate-oxide breakdown is prevented through non-permanent sub-nanoamp drain-bulk junction breakdown. The level shifter circuit has the advantages of small circuit size and low static power consumption.

Abstract: A microelectronic device including, on a substrate, at least one element such as a SRAM memory cell; one or more first transistor(s), respectively including a number k of channels (k?1) parallel in a direction forming a non-zero angle with the main plane of the substrate, and one or more second transistor(s), respectively including a number m of channels, such that m>k, parallel in a direction forming a non-zero angle, or an orthogonal direction, with the main plane of the substrate.

Abstract: Disclosed is a semiconductor device wherein device characteristics are improved by applying a strong stress to a channel region. The semiconductor device includes a semiconductor substrate, a gate insulating film formed over a first plane of the semiconductor substrate, a gate electrode formed over the gate insulating film, a gate sidewall insulating film formed over the sidewall of the gate electrode, source/drain diffusion layer regions into which impurities are implanted, the source/drain diffusion layer regions being adjacent to a channel region formed in the semiconductor substrate below the gate electrode, and a stress applying film formed over the source/drain diffusion layer regions except over the upper part of the gate electrode; and recesses or protrusions are formed in the region where the source/drain diffusion layer regions are formed over the first plane of the semiconductor substrate.

Abstract: A vertically stacked, planar junction Zener diode is concurrently formed with epitaxially grown FET raised S/D terminals. The structure and process of the Zener diode are compatible with Gate-Last high-k FET structures and processes. Lateral separation of diode and transistor structures is provided by modified STI masking. No additional photolithography steps are required. In some embodiments, the non-junction face of the uppermost diode terminal is silicided with nickel to additionally perform as a copper diffusion barrier.

Abstract: A semiconductor device including first and second transistors having first and second gates and first and second source/drain regions, respectively. First and second contacts are electrically connected to the first and the second source/drain regions, respectively. A width of a first bottom surface of the first contacts in a gate width direction of the first-gate is wider than a width of the first bottom surface in a gate length direction of the first-gate. Widths of a second bottom surface of the second-contact are narrower than a longitudinal direction width of the first bottom surface. A high-concentration region is formed between the first source/drain regions and the first-contact. Extending widths of an outline of the high-concentration region extending from an outline of the first bottom surface in the longitudinal direction are larger than extending widths of an outline of the high-concentration region extending from an outline thereof in the short direction.

Abstract: According to the nonvolatile memory device in one embodiment, contact plugs connect between second wires and third wires in a memory layer and a first wire connected to a control element. Drawn wire portions connect the second wires and the third wires with the contact plug. The drawn wire portion connected to the second wires and the third wires of the memory layer is formed of a wire with a critical dimension same as the second wires and the third wires and is in contact with the contact plug on an upper surface and both side surfaces of the drawn wire portion.

Abstract: A field-effect transistor includes a first gate, a second gate held at a substantially fixed potential in a cascode configuration, and a semiconductor channel. The semiconductor channel has an enhancement mode portion and a depletion mode portion. The enhancement mode portion is gated to be turned on and off by the first gate, and has been modified to operate in enhancement mode. The depletion mode portion is gated by the second gate, and has been modified to operate in depletion mode and that is operative to shield the first gate from voltage stress.

Abstract: A wafer including at least a first die and at least a second die, wherein the first die and the second die are separated from each other by an area located between the first die and the second die, is provided. The wafer further includes an alignment mark group used for aligning the wafer to a tool used for patterning the wafer. The alignment mark group is located entirely within the area between the first die and the second die and the alignment mark group includes a plurality of alignment lines, and wherein each line of the plurality of alignment lines is formed using a plurality of segments separated from each other by a plurality of gaps filled with an insulating material.

Abstract: A method forms a metal high dielectric constant (MHK) transistor and includes: providing a MHK stack disposed on a substrate, the MHK stack including a first layer of high dielectric constant material, a second overlying layer, and a third overlying layer, selectively removing only the second and third layers, without removing the first layer, to form an upstanding portion of a MHK gate structure; forming a first sidewall layer on sidewalls of the upstanding portion of the MHK gate structure; forming a second sidewall layer on sidewalls of the first sidewall layer; removing a portion of the first layer to form exposed surfaces; forming an offset spacer layer over the second sidewall layer and over the first layer, and forming in the substrate extensions that underlie the first and second sidewall layers and that extend under a portion but not all of the upstanding portion of the MHK gate structure.

Abstract: An integrated circuit structure includes a semiconductor substrate and a high-voltage metal-oxide-semiconductor (HVMOS) device, which includes a first high-voltage well (HVW) region of a first conductivity type in the semiconductor substrate; a drain region of a second conductivity type opposite the first conductivity type in the semiconductor substrate and spaced apart from the first HVW region; a gate dielectric with at least a portion directly over the first HVW region; and a gate electrode over the gate dielectric. The gate dielectric includes a bottom gate oxide region; and a silicon nitride region over the bottom gate oxide region.

Abstract: Systems and methods for conductive pillars are provided. In one embodiment, a system comprises an electrical board comprising an electrical device, and a packaged die, the packaged die bonded to the electrical board. The packaged die comprises a substrate layer, the substrate layer comprising a recessed area, a conductive trace, wherein a portion of the conductive trace is formed in the recessed area, and an epitaxial device layer bonded to the substrate layer. The device layer comprises a MEMS device, and an epitaxial conductive pillar, wherein a first side of the epitaxial conductive pillar is electrically connected to the conductive trace and the second side of the epitaxial conductive pillar is electrically connected to the electrical board, wherein the epitaxial conductive pillar extends through the epitaxial device layer to electrically couple the conductive trace to an interface surface on the epitaxial device layer.

Abstract: A micro electronic mechanical system structure and a manufacturing method thereof are provided. A substrate has a plurality of conductive regions is provided. A dielectric layer is formed on the substrate. A plurality of openings and recesses are formed in the dielectric layer, wherein the openings expose the conductive regions. The recesses are located between the openings. A conductive layer is formed on the dielectric layer and the openings and the recesses are filled with the conductive layer. The conductive layer is patterned to form a plurality of strips of the first conductive patterns on the dielectric layer and a second conductive pattern on the sidewall and the bottom of each recess, wherein the first conductive patterns are connected with each other through the second conductive patterns. The dielectric layer is removed. The second conductive patterns between the first conductive patterns are removed.

Abstract: A MEMS device includes a substrate. The substrate has a plurality of through holes in the substrate within a diaphragm region and optionally an indent space from the second surface at the diaphragm region. A first dielectric structural layer is then disposed over the substrate from the first surface, wherein the first dielectric structural layer has a plurality of openings corresponding to the through holes, wherein each of the through holes remains exposed by the first dielectric structural layer. A second dielectric structural layer with a chamber is disposed over the first dielectric structural layer, wherein the chamber exposes the openings of the first dielectric structural layer and the through holes of the substrate to connect to the indent space. A MEMS diaphragm is embedded in the second dielectric structural layer above the chamber, wherein an air gap is formed between the substrate and the MEMS diaphragm.

Abstract: According to one embodiment, a magnetoresistive effect element includes a first magnetic layer including perpendicular anisotropy to a film surface and an invariable magnetization direction, the first magnetic layer having a magnetic film including an element selected from a first group including Tb, Gd, and Dy and an element selected from a second group including Co and Fe, a second magnetic layer including perpendicular magnetic anisotropy to the film surface and a variable magnetization direction, and a nonmagnetic layer between the first magnetic layer and the second magnetic layer. The magnetic film includes amorphous phases and crystals whose particle sizes are 0.5 nm or more.

Abstract: A magnetic sensor 1 comprises a main channel layer 7a having first, second, and third regions 71, 72, 73 and extending in a first direction; a first ferromagnetic layer 12A mounted on the first region 71; a second ferromagnetic layer 12B mounted on the second region 72; a projection channel layer 7b projecting in a direction perpendicular to a thickness direction of the main channel layer 7a from a side face of the third region 73 between the first and second regions 71, 72 in the main channel layer 7a; and a magnetic shield S covering both sides in the thickness direction of the projection channel layer 7b and both sides in the first direction of the projection channel layer 7b and exposing an end face 7c in the projecting direction of the projection channel layer 7b.

Abstract: A display device and a fabricating method of the same are disclosed.

Abstract: Disclosed is an image sensor including a photo-sensing device, a color filter positioned on the photo-sensing device, a microlens positioned on the color filter, and an insulation layer positioned between the photo-sensing device and the color filter, and including a trench exposing the photo-sensing device and a filler filled in the trench. The filler has light transmittance of about 85% or more at a visible ray region, and a higher refractive index than the insulation layer. A method of manufacturing the image sensor is also provided.

Abstract: An integrated circuit includes a substrate having a bonding pad region and a non-bonding pad region. A relatively large via, called a “big via,” is formed on the substrate in the bonding region. The big via has a first dimension in a top view toward the substrate. The integrated circuit also includes a plurality of vias formed on the substrate in the non-bonding region. The plurality of vias each have a second dimension in the top view, the second dimension being substantially less than the first dimension.

Abstract: A diode (200) is disclosed having improved efficiency, smaller form factor, and reduced reverse biased leakage current. Schottky diodes (212) are formed on the sidewalls (210) of a mesa region (206). The mesa region (206) is a cathode of the Schottky diode (212). The current path through the mesa region (206) has a lateral and a vertical current path. The diode (200) further comprises a MOS structure (214), p-type regions (220), MOS structures (230), and p-type regions (232). MOS structure (214) with the p-type regions (220) pinch-off the lateral current path under reverse bias conditions. P-type regions (220), MOS structures (230), and p-type regions (232) each pinch-off the vertical current path under reverse bias conditions. MOS structure (214) and MOS structures (230) reduce resistance of the lateral and vertical current path under forward bias conditions. The mesa region (206) can have a uniform or non-uniform doping concentration.

Abstract: A method for manufacturing a Schottky barrier diode includes the following steps. First, a GaN substrate is prepared. A GaN layer is formed on the GaN substrate. A Schottky electrode including a first layer made of Ni or Ni alloy and in contact with the GaN layer is formed. The step of forming the Schottky electrode includes a step of forming a metal layer to serve as the Schottky electrode and a step of heat treating the metal layer. A region of the GaN layer in contact with the Schottky electrode has a dislocation density of 1×108 cm?2 or less.

Abstract: A device includes a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate comprises a first surface and a second surface opposite the first surface. A through-substrate via (TSV) extends from the first surface to the second surface of the semiconductor substrate. A well region of a second conductivity type opposite the first conductivity type encircles the TSV, and extends from the first surface to the second surface of the semiconductor substrate.

Abstract: A semiconductor device has a substrate, first passivation layer formed over the substrate, and integrated passive device formed over the substrate. The integrated passive device can include an inductor, capacitor, and resistor. A second passivation layer is formed over the integrated passive device. System components are mounted to the second passivation layer and electrically connect to the second conductive layer. A mold compound is formed over the integrated passive device. A coefficient of thermal expansion of the mold compound is approximately equal to a coefficient of thermal expansion of the system component. The substrate is removed. An opening is etched into the first passivation layer and solder bumps are deposited over the opening in the first passivation layer to electrically connect to the integrated passive device. A metal layer can be formed over the molding compound or first passivation layer for shielding.

Abstract: A component includes a substrate and a capacitor formed in contact with the substrate. The substrate can consist essentially of a material having a coefficient of thermal expansion of less than 10 ppm/° C. The substrate can have a surface and an opening extending downwardly therefrom. The capacitor can include at least first and second pairs of electrically conductive plates and first and second electrodes. The first and second pairs of plates can be connectable with respective first and second electric potentials. The first and second pairs of plates can extend along an inner surface of the opening, each of the plates being separated from at least one adjacent plate by a dielectric layer. The first and second electrodes can be exposed at the surface of the substrate and can be coupled to the respective first and second pairs of plates.

Abstract: Provided is a trench-type capacitor. To form the capacitor, first and second active regions are disposed in a semiconductor substrate. Node patterns are disposed in the first active region. Each node pattern may have a conductive pattern and an insulating pattern, which are sequentially stacked. Impurity diffusion regions are disposed in the vicinity of the node patterns. Substrate connection patterns in electrical contact with the first and second active regions are disposed. Node connection patterns in electrical contact with the node patterns are disposed in the vicinity of the first and second active regions. In addition, a semiconductor device having the trench-type capacitor and a semiconductor module having the semiconductor device is provided.

Abstract: A nanoelectric memristor device includes a first electrode and a layer of oxygen-vacancy-rich metal oxide deposited upon a surface of the first electrode. A layer of oxygen-rich/stochiometric metal oxide is deposited upon a surface of the oxygen-vacancy-rich metal oxide layer that is opposite from said first electrode. At least one of the oxygen-vacancy-rich metal oxide and oxygen-rich/stochiometric metal oxide layers is doped with one of a magnetic and a paramagnetic material. A second electrode is adjacent to a surface of the oxygen-rich/stochiometric metal oxide layer that is opposite from the oxygen-rich/stochiometric metal oxide layer.

Abstract: A lateral high-breakdown voltage semiconductor device is provided in which the breakdown voltages of elements as a whole are improved, while suppressing increases in cell area. A track-shape gate electrode surrounds a collector electrode extending in a straight line, a track-shape emitter electrode surrounds the gate electrode, and a track-shape first isolation trench surrounds the emitter electrode. A second isolation trench surrounds the first isolation trench. The region between the first isolation trench and the second isolation trench is an n-type isolation silicon region. The isolation silicon region is at the same potential as the emitter electrode. In the cross-sectional configuration traversing the gate electrode, the depth of the p base region in an interval corresponding to an arc-shape portion of the gate electrode is shallower than the depth of the p base region in an interval corresponding to a straight-line portion of the gate electrode.

Abstract: Reverse-conducting insulated gate bipolar transistor in which IGBT region and FWD region are integrated into a single body in a semiconductor substrate with a common active region is disclosed. MOS gate structure is on a first major surface side. Rear surface side structure is in a second major surface side of the semiconductor substrate and includes a plurality of recessed parts vertical to the second major surface, which are repeated periodically along the second major surface. A plurality of protruding parts are interposed between the recessed parts. Rear surface side structure includes p type collector region on a bottom surface of the recessed part, n type first field stop region at a position deeper than the collector region, n type cathode region on the top surface of the protruding part, and n type second field stop region in the protruding part at a position deeper than the cathode region.

Abstract: This invention discloses a semiconductor power device formed in a semiconductor substrate. The semiconductor power device further includes a channel stop region near a peripheral of the semiconductor substrate wherein the channel stop region further includes a peripheral terminal of a diode corresponding with another terminal of the diode laterally opposite from the peripheral terminal disposed on an active area of the semiconductor power device. In an embodiment of this invention, the semiconductor power device is an insulated gate bipolar transistor (IGBT).

Abstract: Bipolar junction transistors are provided in which at least one of an emitter contact, a base contact, or a collector contact thereof is formed by epitaxially growing a doped SixGe1-x layer, wherein x is 0?x?1, at a temperature of less than 500° C. The doped SixGe1-x layer comprises crystalline portions located on exposed surfaces of a crystalline semiconductor substrate and non-crystalline portions that are located on exposed surfaces of a passivation layer which can be formed and patterned on the crystalline semiconductor substrate. The doped SixGe1-x layer of the present disclosure, including the non-crystalline and crystalline portions, contains from 5 atomic percent to 40 atomic percent hydrogen.

Abstract: The present invention provides a differential varactor device including a substrate having a first conductive type, a well having a second conductive type, five doped regions having the second conductive type, a first gate, a second gate, a third gate, and a fourth gate. The well is disposed in the substrate, and the doped regions are disposed in the well and arranged along a direction. The first gate, the second gate, the third gate and the fourth gate are respectively disposed on the well between any two of the adjacent doped regions, and are arranged sequentially along the direction.

Abstract: A PN-junction varactor in a BiCMOS process is disclosed which comprises an N-type region, a P-type region and N-type pseudo buried layers. Both of the N-type and P-type regions are formed in an active area and contact with each other, forming a PN-junction; the P-type region is situated on top of the N-type region. The N-type pseudo buried layers are formed at bottom of shallow trench field oxide regions on both sides of the active area and contact with the N-type region; deep hole contacts are formed on top of the N-type pseudo buried layers in the shallow trench field oxide regions to pick up the N-type region. A manufacturing method of PN-junction varactor in a BiCMOS process is also disclosed.