Abstract: An EEPROM cell including a transfer gate that can suppress a data disturbance phenomenon of the EEPROM cell is provided. The EEPROM cell includes: an inverter; a control plate; a tunneling plate; a data output metal oxide semiconductor field effect transistor (MOSFET) that is connected to the inverter; a floating plate that is connected to the inverter; a tunneling capacitor area that is formed between the floating plate and the tunneling plate; and a transfer gate that is connected to the tunneling plate. As the transfer gate is added between a bit line and the tunneling plate of the EEPROM cell, in a standby (or unselected) operation of the EEPROM cell, the tunneling plate is floated.

Abstract: A flash memory device and a reading method are provided where memory cells are divided into at least two groups. Memory cells are selected according to a threshold voltage distribution. Data stored in the selected memory cells are detected and the data is latched corresponding to one of the at least two groups according to a first read operation. A second read operation detects and latches data of the memory cells corresponding to another one of the at least two groups. The data is processed through a soft decision algorithm during the second read operation.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array includes memory cells and a word line coupling the memory cells. A determination circuit determines whether write to a first memory cell group of the word line succeeded, and whether write to a second memory cell group of the word line succeeded. A test circuit counts application of write voltage during write to the word line, compares with a threshold a difference between a count of write voltage application upon success of one of respective writes to the first and second memory cell groups and a count of write voltage application upon success of the other of respective the writes, and outputs a result of the comparison.

Abstract: Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method includes applying voltages to data lines associated with different groups of memory cells during a programming operation. Such a method applies the voltages to the data lines associated with a last group of memory cells being programmed in a different fashion from the other groups of memory cells after the other groups of memory cells have been programmed. Other embodiments including additional memory devices and methods are described.

Abstract: A bit line bias circuit of a memory architecture includes a varying voltage drop. In some embodiments, the voltage drop can depend on the threshold voltage of the memory cell selected to be read, or on the sense current flowing through the memory cell selected to be read.

Abstract: Methods and apparatus are disclosed, such as those involving a flash memory device that includes an array of memory cells. One such method includes detecting values of charges stored in selected memory cells in the memory cell array. The method also includes processing the detected values in accordance with a Viterbi algorithm so as to determine data stored in the selected memory cells. In one embodiment, the flash memory cell array includes word lines and bit lines. Detecting the values of charges includes detecting values of charges stored in a selected row of memory cells by selecting one of the word lines. The Viterbi algorithm provides correct data where inter-signal interference between the cells affects the accuracy of read data. For example, the Viterbi algorithm can be used to supplement error correction codes (ECC).

Abstract: A semiconductor memory device of the present invention includes a memory cell array configured to include a sensing circuit configured to perform program verifying of the page buffer group selected by the select signal, and configured to output a pass/fail signal corresponding to the page buffer group, a verifying result signal generation section configured to output one or more of a first verifying signal and a second verifying signal in accordance with pass or fail of the program for total page buffer groups by using the pass/fail signal, and a control circuit configured to output the select signals to verify the program after the program is performed, and control operation of the program in response to an output signal of the verifying result signal generation section.

Abstract: A nonvolatile memory device comprises cell strings formed in a direction substantially perpendicular to a substrate and is configured to select memory cells in units corresponding to a string selection line. The device selects a page to be programmed among pages sharing a common word line, determines a level of a program voltage to be provided to the selected page according to a location of a string selection line corresponding to the selected page, and writes data in the selected page using the determined level of the program voltage.

Abstract: According to one embodiment, a nonvolatile semiconductor storage device includes a memory cell array where memory cells are arranged in a row direction and a column direction in a matrix shape; word lines which select the memory cell in the row direction; bit lines which select the memory cells in the column direction; a sense amplifier circuit which determines values stored in the memory cells based on states of the bit line; and a charge/discharge circuit which is formed in a well where the memory cell array is arranged and which charges or discharges the bit lines.

Abstract: A memory array includes a plurality of sense amplifiers and a first switch module. The plurality of sense amplifiers is connected respectively to a plurality of global bit lines. The plurality of sense amplifiers are configured to read data stored in a first block of memory cells of the memory array. The memory cells in the first block are located at intersections of a plurality of local bit lines and a first plurality of word lines. The first switch module is connected to a first group of the plurality of local bit lines and to a first group of the plurality of global bit lines. The first switch module is configured to selectively connect a subset of the first group of the plurality of local bit lines to the first group of the plurality of global bit lines.

Abstract: A memory system includes a plurality of memory devices having data terminals that are commonly connected to a memory controller. Each of the memory devices includes a data output circuit that outputs read data that is read from a memory cell array in response to a read command to the data terminal, and an output-timing adjustment circuit that adjusts an output timing of read data that is output from the data output circuit. The memory controller sets an adjustment amount of adjustment performed by an output-timing adjustment circuit such that delay times from when the read command is issued until when the read data is received match in the memory devices, by issuing a setting command to each of the memory devices.

Abstract: A buffer and control circuit for a synchronous memory controller includes first and second differential comparators and control logic. The first differential comparator is provided with positive and negative differential input signals and the second differential comparator is provided with offset positive and negative differential input signals. The first and second differential comparators generate output signals based on magnitudes of the positive and negative differential input signals and the offset positive and negative differential input signals. The control logic generates a reference strobe signal based on the output signals.

Abstract: A semiconductor memory according to one embodiment includes: a memory cell array including a plurality of memory cells storing data, a first buffer circuit for inputting/outputting data to and from the first memory cell array, a data transfer circuit connected with the first buffer circuit via the first data bus and configured to control data transfer, and a control circuit configured to control a first mode and a second mode. The data transfer circuit performs control such that a bus width of the first data bus differs between the first mode and the second mode.

Abstract: A data input buffer is changed from an inactive to an active state after the reception of instruction for a write operation effected on a memory unit. The input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by turning on a power switch to cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, it is rendered inactive in advance before the instruction is provided, whereby wasteful power consumption is reduced. In another aspect, power consumption is reduced by changing from the active to the inactive state in a time period from a write command issuing to a next command issuing.

Abstract: A semiconductor memory includes a memory array having memory cells coupled to wordlines and bitlines. Each wordline has a left end and an opposing right end. A first wordline in every two adjacent wordlines has its left end connected to a left row driver and its right end connected to a right clamp circuit, and a second wordline in every two adjacent wordlines has its right end connected to a right row driver and its left end connected to a left clamp circuit, such that when the right clamp circuits are activated, the right clamp circuits clamp the corresponding wordline ends to a predetermined potential, and when the left clamp circuits are activated, the left clamp circuits clamp the corresponding wordline ends to the predetermined potential.

Abstract: The present invention provides a row decoder of a semiconductor storage device that prevents an increase in a circuit area while maintaining a high operation speed. Namely, the row decoder of the semiconductor storage device includes a word line selection circuit that has voltage application MOS transistors for each of plural word lines, the voltage application MOS transistors applying a normal voltage to the word lines corresponding to memory cells selected among plural memory cells positioned at a portion where the plural word lines intersect plural bit lines in a predetermined normal operation, and applying a high voltage in a predetermined high voltage operation; and a level shift circuit that outputs the normal voltage or a ground voltage lower than the normal voltage in the normal operation, and that outputs the normal voltage or the high voltage in the high voltage operation, to the voltage application MOS transistor.

Abstract: A memory circuit may include a shift register ring including single-bit shift registers. The circuit may include a clock connected to the shift registers to shift bits within the shift register ring, and a counter connected to the clock and indicating positions of the bits in the shift register ring.

Abstract: An error of stored data is detected with high accuracy. Data (e.g., a remainder in a CRC) used for detecting an error is stored in a memory in which an error is unlikely to occur. Specifically, the following semiconductor device is used: a memory element including a plurality of transistors, a capacitor, and a data storage portion is provided in a matrix; the data storage portion includes one of a source and a drain of one of the plurality of transistors, a gate of another one of the plurality of transistors, and one electrode of the capacitor; a semiconductor layer including a channel of the transistor, the one of the source and the drain of which is connected to the data storage portion, has a band gap of 2.8 eV or more, or 3.2 eV or more; and the data storage portion stores data for detecting an error.

Abstract: A redundancy control circuit includes an address fuse circuit and a first circuit. The address fuse circuit includes a plurality of first fuses. Each of the first fuses is configured to be cut based on a result of comparing a number of bits of a defective input address having a first logic level with a number of bits of the defective input address having a second logic level. The address fuse circuit is configured to generate a first address using the first fuses based on a cutting operation that depends on the result of comparing. The first circuit is configured to output either the first address or a second address that is an inverted address of the first address as a repair address, wherein a logic level of each of bits of the repair address is the same as that of the defective input address.

Abstract: For selecting anti-fuses in a semiconductor memory device, a decoder block may be enabled to receive selection information for selecting the anti-fuses. The selection information is decoded in the decoder block to select at least one of the anti-fuses. Target operation is performed on the selected anti-fuses. The decoder block is disabled.

Abstract: In an exemplary aspect, the present invention provides a semiconductor memory device including sense amplifiers that drive bit lines to which memory cells are connected, and driver transistors that supply a power supply to the sense amplifiers, wherein the sense amplifiers are arranged in rows and constitutes a first sense-amplifier row in which transistors of a first conductive type are arranged and a second sense-amplifier row in which transistors of a second conductive type are arranged, and the driver transistors constitutes at least one transistor row including a first driver transistor of the first conductive type corresponding to the first sense-amplifier row and a second driver transistor of the second conductive type corresponding to the second sense-amplifier row between the first sense-amplifier row and the second sense-amplifier row.

Abstract: A first transistor is turned on based on a first control signal provided to a first terminal of the first transistor. A second transistor is turned on based on a second control signal delayed by a time delay from the first control signal. A second terminal of the first transistor is coupled with a second terminal of the second transistor. The second control signal is used to control a first input signal of a logic device. The logic device receives a second input signal inversed from the first control signal. An output signal of the logic device is used to control a first terminal of the second transistor.

Abstract: Provided are a memory control apparatus and a memory control method. In the memory control apparatus and memory control method, data are distributively stored in a plurality of banks in sequence, and the corresponding data are written to or read from the memory, based on row address information obtained by exchanging a portion of row information and bank information with each other. According to the invention, if a new row begins when the host or the processor accesses the memory, a host or a processor accesses another bank, and thus the block data can be read or written without a waiting cycle. In addition, the memory control apparatus and the memory control method can be implemented with low complexity available through simple address conversion in the memory control apparatus.

Abstract: A pre-decoder for providing a pulse signal to a dual power rail word line driver is provided. The pre-decoder includes a clock generator, an address latch and decoder, a level shifter and a processing unit. The clock generator generates a first signal according to a clock, wherein the first signal is powered by a first supply voltage. The address latch and decoder decodes an address to obtain a second signal according to the first signal. The level shifter generates a third signal according to the first signal, wherein the third signal is powered by a second supply voltage higher than the first supply voltage. The processing unit generates the pulse signal according to the second signal and the third signal, wherein the pulse signal is powered by the second supply voltage.

Abstract: A new address transition detection (ATD) circuit for use on an address bus having a plurality of address signal lines comprises a first circuit for each address signal line and a second circuit. The first circuit has a first input, a second input and an output. The first input is coupled to an address signal line. The second input is coupled to an ATD signal. The first circuit saves the current level of the first input in response to an ATD pulse on the ATD signal and generates a change signal at its output by comparing the current level and the saved level of the first input. The second circuit has an input and an output. The second circuit receives on its input the change signal from the first circuit. In response, the second circuit generates the ATD pulse on the ATD signal at its output.

Abstract: Methods and systems for channel skewing are described. One or more methods for channel skewing includes providing a number of groups of data signals to a memory component, each of the number of groups corresponding to a respective channel, and adjusting a phase of a group of data signals corresponding to at least one of the number of channels such that the group of data signals are skewed with respect to a group of data signals corresponding to at least one of the other respective channels.

Abstract: Embodiments of the present invention generally relate to a warm mix asphalt assembly and methods of operating the same. More specifically, embodiments of the present invention relate to warm mix asphalt assembly having requisite ultra-low nitrogen oxide emissions. In one embodiment of the present invention, a warm mix asphalt assembly comprises a warm mix asphalt skid, having a water input pipe, a water output pipe and a control apparatus; a burner assembly for drying aggregate, the burner assembly comprising a water line for receiving water from the warm mix asphalt skid; and an asphalt expander and drum assembly having a water line for receiving water from the warm mix asphalt skid.

Abstract: An apparatus for converting a dry material into a liquid concentrate includes a mixing vessel having an outlet opening, a dispenser for dispensing a predetermined weight of a dry material at a predetermined drop rate onto a predetermined drop location within the vessel, an inlet pipe connectable to a source of liquid for introducing a liquid into the vessel; a sensor for sensing the volume of liquid within the vessel; a pump for supplying a pressurized flow of recirculating liquid to the vessel; and a first, a second and a third agitating nozzle mounted within the vessel. Each agitating nozzle is operative to produce a jet of liquid oriented in a predetermined direction within the vessel. The nozzles are cooperable to generate within the vessel a moving body of liquid into which a dry material dispensed into the vessel is able to dissolve or to disperse.

Abstract: A paint can-clamping device applicable to a double-gyroscopic mixer is disclosed, including a lower supporting plate, left and right guide rails, an upper pressing plate and a locking mechanism. The locking mechanism includes an upper pressing plate-fixing frame, a locking piece and a locking piece spring. The upper pressing plate is connected to the upper pressing plate-fixing frame via a guide pole. A cam structure having a cam handle is mounted in the upper pressing plate-fixing frame, and is cooperated, via a cam pressing mechanism for pressing the locking piece downwardly, with the locking piece such that the locking piece moves away from the V-shaped groove of the guide rail to be in unlocking state, thereby achieving a linear movement of the upper pressing plate along the guide rails.

Abstract: Apparatus and methods are described for use in mixing of fluids or mixing ingredients into fluids by means of a static mixer assembly (i.e. without requiring moving mechanical parts, where fluid flow is used to achieve mixing). The static mixer assembly is a cylindrical tube with three pairs of fins extending inward from the inner wall of the tube. The central fins form a prow pointing upstream, with two pairs of flanking fins arranged to prevent unhindered fluid flow parallel to the central axis of the tube a peripheral region, whilst allowing unobstructed flow in a central region and extending to a peripheral region near the inner wall opposite the prow. The fins force fluid outwards along the inner walls from the prow towards the unobstructed peripheral region opposite the prow and additionally fluid spills over the inner edges of the fins into the central region. The resulting flow pattern provides excellent mixing with a low ratio of pressure drop to volumetric flow rate across the assembly.

Abstract: The present invention is directed to an apparatus for mixing gaseous mixture components. The present invention likewise relates to a correspondingly applied method and to the use of an apparatus according to the invention for mixing components of the exhaust gas of internal combustion engines with a reducing agent and to a correspondingly designed reactor.

Abstract: The invention is an electric sweep type seismic vibrator source of the type used in seismic prospecting for hydrocarbons. The source uses an engine and generator combination to create electric power to drive a frame of linear electric motors that direct a rod or piston to contact the ground in a recurring fashion. Preferably, a foot is arranged on the bottom end of the rod or piston for contact with the ground and by engaging the grid of motors to push down against the ground in a rapid progression, acoustic energy is created and delivered into the ground for geophones to sense and record.

Abstract: Disclosed are methods and systems for depth control of a sensor streamer. An example embodiment comprises a method for depth control of a sensor streamer. The example method may comprise towing the sensor streamer in a body of water; measuring noise levels of one or more signals generated on the sensor streamer; and adjusting depth of the sensor streamer at one or more spaced apart locations in response to the measured noise levels.

Abstract: A method is proposed for acquiring seismic data relative to an area of the subsoil, wherein at least one seismic source is moved and seismic waves are emitted in successive shooting positions of the source so as to illuminate said area of the subsoil, and the signals resulting from this emissions are picked up using a set of cables having a substantially zero buoyancy and provided with receivers. The cables have a substantially zero speed or a speed substantially slower than the source in the terrestrial reference frame. And said successive shot positions are determined as a function of the position of the receivers relative to the terrestrial reference frame to optimize at least one quality criterion relating to the set of seismic signals acquired by the receivers in respect of said area. Such a method enables improved seismic data acquisition.

Abstract: The present invention relates to streamer cables. One embodiment of the present invention relates to a method for preparing a streamer cable. The method may comprise retrofitting the streamer cable with a solid void-filler material, where the streamer cable was configured as a liquid-filled streamer cable. The retrofitting may comprise introducing a void-filler material into the streamer cable when the void-filler material is in a liquid state and curing or otherwise solidifying the void-filler material to a solid state. In another embodiment, the present invention relates to a streamer cable comprising an outer skin and-at least one sensor positioned within the outer skin. The streamer cable may also comprise a solid void-filler material positioned between the outer skin and the at least one sensor, wherein the solid void-filler material is coupled to the at least one sensor.

Abstract: The description relates to a seismic imaging technology technique for modeling a subsurface structure through waveform inversion in the Laplace domain. The seismic imaging system comprises a scaled gradient calculating unit calculating a scaled gradient, a modeling parameter updating unit updating the model parameters using the scaled gradient direction, and an iteration control unit controlling the scaled gradient calculating unit and the modeling parameter updating unit to repeat processing iteratively until a stopping criteria is met.

Abstract: A method for managing a multi-vessel seismic system including a first vessel, having a recording system and towing a streamer integrating seismic sensors, and a second vessel, including at least one seismic source performing shots. The second vessel sends to the first vessel a plurality of series of shot predictions. For each shot, the second vessels activates the seismic source according to the predictions and sends to the first vessel shot data relating to the shot. The first vessel activates the recording system. If the first vessel has not received the shot data relating to at least one performed shot, it sends a request to the second vessel and receives in response the missing shot data. For each performed shot and the related shot data, the system selects seismic data and combines the selected seismic data with the related shot data to obtain combined data allowing a seabed representation.

Abstract: One embodiment relates to a method for deghosting seismic data from a marine seismic survey. The seismic data from the marine seismic survey is obtained, where the marine seismic survey was performed using multiple sub-sources towed at two or more different depths and fired at distinct time-delays. The seismic data is sorted into common receiver gathers, and the common receiver gathers are transformed from horizontal source coordinates to horizontal wavenumbers. For each selected frequency, a matrix operator is constructed, and an inversion procedure is applied to a system of equations based on the matrix operator to generate source-deghosted seismic data. Other embodiments, aspects and features are also disclosed.

Abstract: An inspection system includes a plurality of acoustic beamformers, where each of the plurality of acoustic beamformers including a plurality of acoustic transmitter elements. The system also includes at least one controller configured for causing each of the plurality of acoustic beamformers to generate an acoustic beam directed to a point in a volume of interest during a first time. Based on a reflected wave intensity detected at a plurality of acoustic receiver elements, an image of the volume of interest can be generated.

Abstract: The invention is an electric seismic vibrator source of the type used in seismic prospecting for hydrocarbons that creates a quasi-impulsive burst of seismic energy onto the ground and into the earth. The source uses an engine and generator combination to create electric power for all systems on the source such as driving a frame of linear electric motors that direct a rod or piston to contact the ground. All of the linear electric motors are driven against the ground in a high power pulse that delivers a band-limited spectrum of seismic energy over a very brief period of time that would like a “pop” and be measured in milliseconds. A quasi-impulsive seismic pulse would create a wave field that resembles the seismic data acquired using dynamite or other explosive seismic systems without the ultrahigh frequencies of a true explosive pulse. The quick burst or several quick bursts may further speed up the survey by minimizing the time that a vibe spends on a source point.

Abstract: The invention is an electric sweep type seismic vibrator source of the type used in seismic prospecting for hydrocarbons. The source uses an engine and generator combination to create electric power for all systems on the source such as driving a frame of linear electric motors that direct a rod or piston to contact the ground in a recurring fashion along with driving the source from location to location through a survey area. Preferably a foot is arranged on the bottom end of the rod or piston for contact with the ground and by engaging the grid of motors to push down against the ground in a rapid progression, acoustic energy is created and delivered into the ground for geophones to sense and record.

Abstract: A seismic wave source and sensing system coupled to the surface of an elastic wave propagation medium has a seismic wave source transducer having a preferred axis of vibration oriented horizontally on the surface of the elastic wave propagation medium. A seismic wave sensing transducer has a preferred axis of vibration response oriented horizontally on the surface of said elastic wave propagation medium such that said sensing transducer is capable of detecting dynamic particle motions and displacements of SH waves. An arrangement of the source and sensing transducers is provided on the surface of the elastic wave propagation medium. A recording system capable of acquiring and storing reflected SH wave signals detected by the sensing transducer, wherein the recorded signals represent reflections from contrasting physical properties within the elastic wave propagation medium to provide preferential detection of elongate subsurface targets such as utility pipes, conduits, and other similar object.

Abstract: Systems and methods include seismic data stacking derived from a set of image volumes. Stacking includes finding a sub-set of seismic image volumes (and in some implementations their respective stacking weights) or multiple realizations of sub-set of seismic image volumes from a given set that are consistent and similar to each other. Some or all of the input seismic image volumes can be stacked together as they would be with a conventional stack. However, the signal-to-noise ratio can be enhanced by only stacking those volumes that contain consistent and relevant information. Optimal stacking can utilize an algorithm that can be implemented in a moving window fashion.

Abstract: In an ultrasonic detection system utilizing multiple ultrasound transducers capable of both transmitting and receiving detection signals, the transducers are selectively operated to achieve immunity to ringdown delays or to optimize the detection of distant objects. For example, in one embodiment, object detection is performed within the field of a particular transducer channel by suppressing rather than activating that transducer; instead, the adjacent transducers on either side of the selected channel are driven simultaneously, and the selected channel's transducer is used only to receive.

Abstract: An ultrasonic wave transceiving device is provided. The device includes a transmitter for transmitting at least one kind of first detection data ultrasonic signal and a plurality of kinds of second detection data ultrasonic signals, a receiver for receiving echo signals of the first and second detection data ultrasonic signals, and first and second information generators for generating first and second information based on the echo signal of the first and second detection data ultrasonic signals, respectively. The transmitter transmits the first and second detection data ultrasonic signals which transmission period of the first detection data ultrasonic signal intervenes between transmission periods of the second detection data ultrasonic signals in time axis. The second information generator generates the second information by using the echo signals of the second detection data ultrasonic signals.

Abstract: A method for increasing a bearing accuracy of a receiver assembly includes providing a receiver assembly which receives sound waves to determine reception signals. The reception signals determine direction signals of a reception direction. Frequency lines of a frequency of a frequency range comprising an amplitude value are attributed to a reception direction based the direction signals. A directional function is formed for each frequency. Each directional function is transformed into a spectral range to obtain a first spectral function comprising first spectral function arguments. The first spectral function are filled with other spectral function arguments between middle spectral function arguments of the first spectral function arguments to obtain filled first spectral arguments. The other spectral function arguments have a respective value of zero or a range of zero. Each of the filled first spectral functions are transformed back from the spectral range to an interpolated first directional function.

Abstract: An ultrasound transducer array according to an embodiment includes a substrate, a plurality of groove-like recesses arranged at a predetermined interval on one surface of the substrate, a cell region arranged between the recesses on the one surface side of the substrate, a flexible film configured to cover the substrate and the cell region and having fragility lower than fragility of the substrate, and a dividing groove having a width smaller than a width of the recess and reaching from the other surface of the substrate to the flexible film in the recess.

Abstract: A bottom hole assembly is configured with a drill bit section connected to a pulse generation section. The pulse generation section includes a relatively long external housing, the particular housing length being selected for the particular drilling location. The long external housing is positioned closely adjacent to the borehole sidewalls to thereby create a high speed flow course between the external walls of the housing and the borehole sidewalls. The long external housing includes a valve cartridge assembly and optionally a shock sub decoupler. While in operation, the valve cartridge assembly continuously cycles and uses downhole pressure to thereby generate seismic signal pulses that propagate to geophones or other similar sensors on the surface. The amount of bypass allowed through the valve assembly is selectable in combination with the long external housing length and width to achieve the desired pulse characteristics.

Abstract: The invention is an electric power accumulator used with an electric sweep type seismic vibrator source of the type used in seismic prospecting for hydrocarbons. The source uses an engine and generator combination to create electric power to drive a frame of linear electric motors that direct a rod or piston to contact the ground in a recurring fashion. The source may also be designed to use electric power to drive the source from location to location through a survey area. A large electric power accumulator is provided to store electric power when the generator is able to produce excess power and the accumulator may deliver power along with the generator to drive the rods and deliver acoustic energy. With a large electric power accumulator, such as a battery or capacitor, the engine and generator combination may be engineered to be somewhat smaller, less costly and more efficient than a system where the engine and generator were sized to provide the electric power at times of maximum electric draw.

Abstract: The invention is an electric sweep type seismic vibrator source of the type used in seismic prospecting for hydrocarbons. The source uses an engine and generator combination to create electric power for all systems on the source such as driving a frame of linear electric motors that direct a rod or piston to contact the ground in a recurring fashion along with driving the source from location to location through a survey area. The seismic source further includes an active isolation system that provides for significant weight on the ground through the rods of the linear electric motors, but protects the vehicle body and the remainder of the systems on the seismic source to be insulated from the harshest vibration related to the acoustic energy being applied to the ground.