Abstract: Provided is a semiconductor device equipped with: a plurality of switching elements (T1, T2) that are connected in series; a first capacitance (Cs1) having one electrode connected to an end of the plurality of switching elements (T1, T2) and another electrode being connected to a first capacitance wiring line (CSL1); a second capacitance (Cs2) with one electrode connected to a node that connects two adjacent switching elements (T1, T2) among the plurality of switching elements, and another electrode being connected to a second capacitance wiring line (CSL2); and a light-shielding film that block light from being incident on at least one of the plurality of switching elements (T1, T2).

Abstract: A thin-film semiconductor device) having two thin-film transistors, wherein one of the thin-film transistors includes: a first gate electrode; a first gate insulating film; a first semiconductor film; an intrinsic semiconductor layer; a first contact layer of n-type in contact with and above a portion of the intrinsic semiconductor layer; a first source electrode; and a first drain electrode, and the other of the thin-film transistors includes: a second gate electrode; a second gate insulating film; a second semiconductor film; an intrinsic semiconductor layer; a second contact layer of p-type in contact with portions of sides of the semiconductor film and the intrinsic semiconductor layer; a second source electrode; and a second drain electrode.

Abstract: A thin film semiconductor device formed as integrated circuits on an insulating substrate with bottom gate type thin film transistors stacked with gate electrodes, a gate insulating film and a semiconductor thin film in the order from below upward. The gate electrodes comprise metallic materials with thickness less than 100 nm. The gate insulating film has a thickness thicker than the gate electrodes. The semiconductor thin film comprises polycrystalline silicon crystallized by a laser beam. By reducing thickness of metallic gate electrodes, thermal capacity becomes small and difference in thermal condition on the metallic gate electrodes and on the insulating substrate made of glass or the like becomes small. This invention relates to the task of uniforming and optimizing recrystallization by a laser anneal treatment provided for the semiconductor thin film which works as an active layer of the bottom gate type thin film transistors.

Abstract: A Schottky barrier diode (SBD) is disclosed, which includes: a gallium nitride (GaN) layer, formed on a substrate; an aluminum gallium nitride (AlGaN), formed on the GaN layer; an insulation layer, formed on the AlGaN layer; an anode conducive layer, formed on the insulation layer, wherein Schottky contact is formed between a part of the anode conductive layer and the AlGaN layer or between a part of the anode conductive layer and the GaN layer, and another part of the anode conductive layer is separated from the AlGaN layer by the insulation layer; and a cathode conductive layer, formed on the AlGaN layer, wherein an ohmic contact is formed between the cathode conductive layer and the GaN layer or between the cathode conductive layer and the AlGaN layer, and wherein the anode conductive layer is not directly connected to the cathode conductive layer.

Abstract: According to one embodiment, a semiconductor light emitting device includes a metal substrate, a first semiconductor layer, a first semiconductor layer, a second semiconductor layer, a light emitting layer, a first intermediate layer and a second intermediate layer. The substrate has a coefficient of thermal expansion not more than 10×10?6 m/K. The first and second semiconductor layer include a nitride semiconductor. The second semiconductor layer is provided between the substrate and the first semiconductor layer. The emitting layer is provided between the first semiconductor layer and the second semiconductor layer. The first intermediate layer is provided between the substrate and the second semiconductor layer. The second intermediate layer is provided between the first intermediate layer and the second semiconductor layer. a surface roughness of a first surface of the substrate contacting the first intermediate layer is less than a thickness of the first intermediate layer.

Abstract: In embodiments of the invention, a semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region is grown on a substrate. The substrate is a non-III-nitride material. The substrate has an in-plane lattice constant asubstrate. At least one III-nitride layer in the semiconductor structure has a bulk lattice constant alayer and [(|asubstrate?alayer|)/asubstrate]100% is no more than 1%. A surface of the substrate opposite the surface on which the semiconductor structure is grown is textured.

Abstract: A photoelectric conversion element of an embodiment is a photoelectric conversion element which performs photoelectric conversion by receiving illumination light having n light emission peaks having a peak energy Ap (eV) (where 1?p?n and 2?n) of 1.59?Ap?3.26 and a full width at half maximum Fp (eV) (where 1?p?n and 2?n), wherein the photoelectric conversion element includes m photoelectric conversion layers having a band gap energy Bq (eV) (where 1?q?m and 2?m?n), and the m photoelectric conversion layers each satisfy the relationship of Ap?Fp<Bq?Ap with respect to any one of the n light emission peaks.

Abstract: According to one embodiment, a semiconductor light-emitting device includes: a first conductivity type first semiconductor layer containing a nitride semiconductor crystal and having a tensile stress in a (0001) surface; a second conductivity type second semiconductor layer containing a nitride semiconductor crystal and having a tensile stress in the (0001) surface; a light emitting layer provided between the first semiconductor layer and the second semiconductor layer, containing a nitride semiconductor crystal, and having an average lattice constant larger than the lattice constant of the first semiconductor layer; and a first stress application layer provided on a side opposite to the light emitting layer of the first semiconductor layer and applying a compressive stress to the first semiconductor layer.

Abstract: A semiconductor light emitting device includes a first and second conductive semiconductor layers including an n-type dopant on active layer; a third and fourth conductive semiconductor layers including a p-type dopant under the active layer; wherein the first to fourth conductive semiconductor layers are formed of an AlGaN-based semiconductor, wherein the active layer includes a plurality of quantum barrier layers and a plurality of quantum well layers, wherein the plurality of quantum well layers include an InGaN semiconductor layer, wherein the plurality of quantum barrier layers include an AlGaN-based semiconductor layer, wherein at least two of the plurality barrier layers have a thickness of about 50 ? to about 300 ?, respectively, wherein a cycle of the quantum barrier layer and the quantum well layer includes a cycle of 2 to 10, wherein the second conductive semiconductor layer has a thickness thinner than a thickness of the third conductive semiconductor layer.

Abstract: A nitride semiconductor light-emitting device includes a nitride semiconductor light-emitting chip including an active layer for outputting polarized light, the active layer having a non-polar plane or a semi-polar plane as a growth plane; and a light-transmissive cover for transmitting light from the active layer. The light-transmissive cover includes a first light-transmissive member located in an area, among areas to the side of the nitride semiconductor light-emitting chip, and in a direction perpendicular to a polarization direction of the polarized light, and a second light-transmissive member located in an area above the nitride semiconductor light-emitting chip. The first light-transmissive member has a higher diffuse transmittance than the second light-transmissive member.

Abstract: Semiconductor light emitting devices, such as light emitting diodes, include a substrate, an epitaxial region on the substrate that includes a light emitting region such as a light emitting diode region, and a multilayer conductive stack including a current spreading layer, on the epitaxial region. A barrier layer is provided on the current spreading layer and extending on a sidewall of the current spreading layer. The multilayer conductive stack can also include an ohmic layer between the reflector and the epitaxial region. The barrier layer further extends on a sidewall of the ohmic layer. The barrier layer can also extend onto the epitaxial region outside the multilayer conductive stack. The barrier layer can be fabricated as a series of alternating first and second sublayers.

Abstract: A method for manufacturing a semiconductor stacked body, and a semiconductor element including the semiconductor stacked body includes a semiconductor stacked body, including a Ga203 substrate having, as a principal plane, a plane on which oxygen atoms are arranged in a hexagonal lattice, an AIN buffer layer formed on the Ga203 substrate, and a nitride semiconductor layer formed on the AIN buffer layer.

Abstract: A light-emitting device of an embodiment of the present application comprises optoelectronic units; a transparent structure having cavities configured to accommodate at least one of the optoelectronic units; and a conductive element connecting at least two of the optoelectronic units.

Abstract: This disclosure discloses a light-emitting display module display. The light-emitting display module comprises: a board; and a plurality of light-emitting diode modules arranged in an array configuration on the board; wherein one of the light-emitting diode modules comprises a plurality of encapsulated light-emitting units spaced apart from each other; and one of the encapsulated light-emitting units comprises a plurality of optoelectronic units, a first supporting, and a fence; and wherein the plurality of optoelectronic units are covered by the first supporting structure, and the fence surrounds the first supporting structure and the plurality of optoelectronic units.

Abstract: An array substrate comprises a substrate, a gate electrode, a source electrode and a drain electrode, the source electrode and the drain electrode being provided in different areas on the substrate and the vertical projections of the source electrode and the drain electrode on the substrate having an overlapping area; a semiconductor layer formed between the source electrode and the drain electrode, a vertical projection of the semiconductor layer on the substrate having overlapping areas with the vertical projections of the source electrode and the drain electrode on the substrate; a first insulating layer formed on the substrate while below the gate electrode and covering the source electrode or the drain electrode; a pixel electrode, a gate line, and a data line. A manufacturing method for the array substrate is also disclosed.

Abstract: A semiconductor light-emitting device includes: a semiconductor chip having a growth surface that is a nonpolar or semipolar plane, and emitting polarized light; and a reflector having a reflective surface. At least part of light in a plane L90 is reflected off the reflective surface in a direction of a normal line to the growth surface, and an amount of light reflected off the reflective surface in the plane L90 in the direction of the normal line is larger than that of light reflected off the reflective surface on a plane L45 in the direction of the normal line, where the plane L90 represents a plane including the normal line and oriented at 90° to a polarization direction of the polarized light, and the plane L45 represents a plane including the normal line, and oriented at 45° to the polarization direction of the polarized light.

Abstract: An LED display panel includes: a semiconductor wafer having a top surface; a plurality of LED elements disposed over the top surface of the semiconductor wafer, each of the LED elements having an electrode contact; and a plurality of driving circuits formed in the semiconductor wafer. Each of the driving circuits has an electrode-connecting contact that is disposed on the top surface of the semiconductor wafer and that is bonded to the electrode contact of a respective one of the LED elements.

Abstract: A light blocking member including a metal particle and a ceramic material and a display device including the same.

Abstract: A method of fabricating a light-emitting device comprising steps of: providing a substrate, an active layer, and a first semiconductor layer between the substrate and the active layer; removing part of the active layer; and forming a rough structure in the first semiconductor layer while keeping the active layer attached to the substrate.

Abstract: Some embodiments in the present disclosure generally relate to fluorescent structures such as fluorescent glass, fluorescent substrates, and/or light emitting devices, which can include a gradient of fluorescent molecules across the structure, substrate, and/or light emitting device. In some embodiments, the fluorescent glass, fluorescent substrates, and/or light emitting devices can be porous and include at least one fluorescent molecule within the one or more pore. In some embodiments, this can allow for the creation of a gradient fluorescent material throughout the material.

Abstract: Using compression molding to form lenses over LED arrays on a metal core printed circuit board leaves a flash layer of silicone covering the contact pads that are later required to connect the arrays to power. A method for removing the flash layer involves blasting particles of sodium bicarbonate at the flash layer. A nozzle is positioned within thirty millimeters of the top surface of the flash layer. The stream of air that exits from the nozzle is directed towards the top surface at an angle between five and thirty degrees away from normal to the top surface. The particles of sodium bicarbonate are added to the stream of air and then collide into the top surface of the silicone flash layer until the flash layer laterally above the contact pads is removed. The edge of silicone around the cleaned contact pad thereafter contains a trace amount of sodium bicarbonate.

Abstract: This application discloses a light-emitting device with narrow dominant wavelength distribution and a method of making the same. The light-emitting device with narrow dominant wavelength distribution at least includes a substrate, a plurality of light-emitting stacked layers on the substrate, and a plurality of wavelength transforming layers on the light-emitting stacked layers, wherein the light-emitting stacked layer emits a first light with a first dominant wavelength variation; the wavelength transforming layer absorbs the first light and converts the first light into the second light with a second dominant wavelength variation; and the first dominant wavelength variation is larger than the second dominant wavelength variation.

Abstract: A method for manufacturing a light emitting device that comprises a light emitting element and a phosphor layer to absorb at least a part of light emitted from the light emitting element to emit a light having a different wavelength from that of the absorbed light comprises a first resin layer forming step of forming a first resin layer with a first resin in which viscosity is adjusted to a first viscosity on a light emitting face of the light emitting element to define a predetermined shape of the phosphor layer; a second resin layer forming step of forming a second resin layer with a second resin containing a phosphor in which viscosity is adjusted to a second viscosity lower than the first viscosity on the first resin layer before curing the first resin layer; and a curing step of curing the first resin layer and the second resin layer.

Abstract: A technique of producing a control component for a reflective display device, comprising: forming an array of electronic switching devices; forming over said array of electronic switching devices an insulator region defining a controlled surface topography; and forming on the patterned surface of the insulator region by a conformal deposition technique a substantially planar array of reflective pixel conductors each independently controllable via a respective one of the array of electronic switching devices, wherein each pixel conductor exhibits specular reflection at a range of reflection angles relative to the plane of the array of pixel conductors for a given incident angle relative to the plane of the array of pixel conductors.

Abstract: A light-emitting device comprises a semiconductor light-emitting stacked layer having a first connecting surface, wherein the semiconductor light-emitting stacked layer comprises a first alignment pattern on the first connecting surface, and a substrate under the semiconductor light-emitting stacked layer, wherein the substrate has a second connecting surface being operable for connecting with the first connecting surface, wherein the substrate comprises a second alignment pattern on the second connecting surface, and the second alignment pattern is corresponding to the first alignment pattern.

Abstract: A display device includes a display panel, a driving circuit, and a connection terminal. The display panel includes a display area and a non-display area surrounding the display area and an electrode terminal disposed in the non-display area and extended in a direction. The driving circuit includes a signal terminal extended in the same direction as the electrode terminal and disposed adjacent to the electrode terminal. The connection terminal is disposed on the electrode terminal and the signal terminal to electrically connect the electrode terminal and the signal terminal.

Abstract: A semiconductor light emitting device includes a first conductive semiconductor layer, an active layer, a second conductive semiconductor layer, a first internal electrode, a second internal electrode, an insulating part, and first and second pad electrodes. The active layer is disposed on a first portion of the first conductive semiconductor layer, and has the second conductive layer disposed thereon. The first internal electrode is disposed on a second portion of the first conductive semiconductor layer separate from the first portion. The second internal electrode is disposed on the second conductive semiconductor layer. The insulating part is disposed between the first and second internal electrodes, and the first and second pad electrodes are disposed on the insulating part to connect to a respective one of the first and second internal electrodes.

Abstract: A light emitting device includes a light emitting structure including a first conductive semiconductor layer, an active layer under the first conductive semiconductor layer, and a second conductive semiconductor layer adjacent the active layer. A first electrode is electrically coupled to the first conductive semiconductor layer, and a second electrode is electrically coupled to the second conductive semiconductor layer. A channel layer is provided at a peripheral portion of a lower portion of the light emitting structure, and a conductive support member is provided adjacent to the second electrode. A first connection part is electrically coupled to the first electrode and the conductive support member, and a second connection part is electrically coupled to the second electrode.

Abstract: A light emitting diode includes a first semiconductor layer, an active layer, and a second semiconductor layer sequentially stacked on a substrate, and a first electrode connected to the first semiconductor layer. The first electrode includes an edge electrode including first and second edge portions opposite to each other, and a line electrode including first and second line portions respectively extending from the first and second edge portions. The edge electrode has a closed loop-shape. A distance between the first line portion and the second edge portion is equal to or less than a quarter of a length of the first line portion. A distance between the second line portion and the first edge portion is equal to or less than a quarter of a length of the second line portion.

Abstract: The present invention relates to a composition based on a polyamide matrix having a high thermal conductivity and comprising specific proportions of alumina and of graphite and also a flame-retardant system. This composition may in particular be used for producing components for lighting devices comprising light-emitting diodes.

Abstract: An LED lamp comprises an LED light source (1), a cup-shaped radiator (2) and a power supply (3), electrodes (1a) and a heat sink (1b) are provided at the back side of the LED light source (1). The LED light source (1) is provided at the inner side of the bottom of the cup-shaped radiator (2), electrodes (7) are provided at the bottom of the cup-shaped radiator (2). The power supply (3) is provided at the outer side of the bottom of the cup-shaped radiator (2). The electrodes (1a) of the LED light source (1) and the power supply (3) are directly connected with two ends of the electrodes (7) of the cup-shaped radiator (2) respectively. A manufacture method of the LED lamp is also provided. The heat-conduction efficiency of the LED lamp is high, and the heat-dissipation structure of the whole lamp is effectively improved. And heat is dissipated by radiating, and therefore the stability in the indoor illumination environment is high. The manufacture process has high automation degree.

Abstract: The present invention relates to a technique of semiconductor devices, and provides a semiconductor device, which uses two controllable current sources to control the electron current and the hole current of the voltage-sustaining region of a thyristor under conduction state, making the sum of current between anode and cathode close to saturation under high voltage, thus avoiding the current crowding effect in local region and increasing the reliability of the device. Besides, it further provides a method of implementing the two current sources in the device and a method to improve the switching speed.

Abstract: Disclosed herein is a trench gate type power semiconductor device including: a semiconductor substrate; a drift layer formed on the semiconductor substrate; a well layer formed on the drift layer; trenches formed to arrive at the drift layer while penetrating through the well layer in a thickness direction; first insulating films formed from bottom surfaces of the trenches up to a predetermined height; first electrodes formed at a height lower than that of the first insulating films in the trenches; interlayer dielectrics formed up to the same height as that of the first insulating films in the trenches; and a second electrode formed on the well layer, a portion of the first surface corresponding to the trenches being protruded into the trenches to contact the interlayer dielectrics.

Abstract: Disclosed herein are a semiconductor device and a method for manufacturing the same, the semiconductor device including: trench gate electrodes formed in a semiconductor substrate; a gate insulating film covering an upper surface of the semiconductor substrate and lateral surfaces and lower surfaces of the trench gate electrodes; a base region formed between the trench gate electrodes; an emitter region formed between the trench gate electrodes and on the base region; interlayer insulating films formed on the trench gate electrodes and spaced apart from each other; an emitter metal layer formed on the interlayer insulating films and between the interlayer insulating films.

Abstract: Transistor devices can be fabricated with an integrated diode using a self-alignment. The device includes a doped semiconductor substrate having one or more electrically insulated gate electrodes formed in trenches in the substrate. One or more body regions are formed in a top portion of the substrate proximate each gate trench. One or more source regions are formed in a self-aligned fashion in a top portion of the body regions proximate each gate trench. One or more thick insulator portions are formed over the gate electrodes on a top surface of the substrate with spaces between adjacent thick insulator portions. A metal is formed on top of the substrate over the thick insulator portions. The metal forms a self-aligned contact to the substrate through the spaces between the thick insulator portions. An integrated diode is formed under the self-aligned contact.

Abstract: Disclosed is a technique capable of reducing loss at the time of switching in a diode. A diode disclosed in the present specification includes a cathode electrode, a cathode region made of a first conductivity type semiconductor, a drift region made of a low concentration first conductivity type semiconductor, an anode region made of a second conductivity type semiconductor, an anode electrode made of metal, a barrier region formed between the drift region and the anode region and made of a first conductivity type semiconductor having a concentration higher than that of the drift region, and a pillar region formed so as to connect the barrier region to the anode electrode and made of a first conductivity type semiconductor having a concentration higher than that of the barrier region. The pillar region and the anode are connected through a Schottky junction.

Abstract: A layered semiconductor substrate has a monocrystalline first layer based on silicon, having a first thickness and a first lattice constant a1 determined by a first dopant element and a first dopant concentration, and in direct contact therewith, a monocrystalline second layer based on silicon, having a second thickness and a second lattice constant a2, determined by a second dopant element and a second dopant concentration, and a monocrystalline third layer comprising a group III nitride, the second layer located between the first layer and the third layer, wherein a2>a1, wherein the crystal lattice of the first layer and the second layer are lattice-matched, and wherein the bow of the layered semiconductor substrate is in the range from ?50 ?m to 50 ?m.

Abstract: An electronic component includes a high voltage switching transistor encased in a package. The high voltage switching transistor comprises a source electrode, a gate electrode, and a drain electrode all on a first side of the high voltage switching transistor. The source electrode is electrically connected to a conducting structural portion of the package. Assemblies using the abovementioned transistor with another transistor can be formed, where the source of one transistor can be electrically connected to a conducting structural portion of a package containing the transistor and a drain of the second transistor is electrically connected to the second conductive structural portion of a package that houses the second transistor. Alternatively, the source of the second transistor is electrically isolated from its conductive structural portion, and the drain of the second transistor is electrically isolated from its conductive structural portion.

Abstract: According to example embodiments, a semiconductor device may include a high electron mobility transistor (HEMT) on a first region of a substrate, and a diode on a second region of the substrate. The HEMT may be electrically connected to the diode. The HEMT and the diode may be formed on an upper surface of the substrate such as to be spaced apart from each other in a horizontal direction. The HEMT may include a semiconductor layer. The diode may be formed on another portion of the substrate on which the semiconductor layer is not formed. The HEMT and the diode may be cascode-connected to each other.

Abstract: The present invention relates to a substrate (5) comprising a Si-base (1) and an InAs-layer (4) provided on said Si-base where said InAs-layer (4) has a thickness between 100 and 500 nanometers and root-mean-square roughness of the upper surface of said InAs-layer (4) is below 1 nanometer. The invention further relates to a method for forming said substrate. The invention also relates to growing InAs-nanowires (7) as well as a GaSb-layer (17) on said substrate (5).

Abstract: Disclosed herein is a solid-state imaging device including: an opto-electrical conversion section provided inside a semiconductor substrate to receive incident light coming from one surface of the semiconductor substrate; a wiring layer provided on the other surface of the semiconductor substrate; and a light absorption layer provided between the other surface of the semiconductor substrate and the wiring layer to absorb transmitted light passing through the opto-electrical conversion section as part of the incident light.

Abstract: An image sensor includes a first substrate including a driving element, a first insulation layer on the first substrate and on the driving element, a second substrate including a photoelectric conversion element, and a second insulation layer on the second substrate and on the photoelectric conversion element. A surface of the second insulation layer is on an upper surface of the first insulation layer. The image sensor includes a conductive connector penetrating the second insulation layer and a portion of the first insulation layer. Methods of forming image sensors are also disclosed.

Abstract: An embodiment of the disclosure discloses an in-cell touch panel having advantages such as a simple structure and a low cost. The in-cell touch panel comprises: a first substrate and a second substrate arranged oppositely, wherein a plurality of gate lines arranged horizontally are formed on the first substrate; the in-cell touch panel further comprises: a plurality of touch driving lines arranged horizontally; a plurality of touch sensing lines arranged vertically; and a plurality of touch scanning TFTs, wherein each touch scanning TFT has a gate connected to one gate line, a source connected to a touch driving circuit, and a drain connected to one touch driving line, the one gate line is only connected to the gate of one touch scanning TFT; wherein, the number of the gate lines?the number of the touch scanning TFTs?the number of the touch driving lines.

Abstract: A semiconductor device and a method for fabricating the semiconductor device are disclosed. A gate stack is formed over a substrate. A spacer is formed adjoining a sidewall of the gate stack. A recess is formed between the spacer and the substrate. Then, a strained feature is formed in the recess. The disclosed method provides an improved method by providing a space between the spacer and the substrate for forming the strained feature, therefor, to enhance carrier mobility and upgrade the device performance.

Abstract: A semiconductor device includes an active area defined by a device isolation layer and including a plurality of source/drain regions, a gate structure disposed on the active area and extending in a first direction, a stress layer contacting a side surface of each of the plurality of source/drain regions and a plurality of source/drain contacts disposed in the active area and connected to the plurality of source/drain regions.

Abstract: A process fabricates a fin field-effect-transistor by implanting a dopant into an exposed portion of a semiconductor substrate within a cavity. The cavity is formed in a dielectric layer on the semiconductor substrate. The cavity exposes the portion of the semiconductor substrate within the cavity. A semiconductor layer is epitaxially grown within the cavity atop the dopant implanted exposed portion of the semiconductor substrate. A height of the cavity defines a height of the epitaxially grown semiconductor.

Abstract: A semiconductor device including a silicon substrate including a first region and a second region; a gate electrode above the first region and the second region; an insulation film extending from the gate electrode to the second region to cover part of the gate electrode and part of the second region; a source region and a drain region formed in the silicon substrate, silicide formed on the source region, on the drain region, and on the gate electrode; an interlayer insulation film formed above the gate electrode and the insulation film; a first electrically conductive via formed in the interlayer insulation film, a second electrically conductive via formed in the interlayer insulation, and a third electrically conductive via formed in the interlayer insulation and electrically connecting to the gate electrode; and at least one electrically conductive member formed on the insulation film in the interlayer insulation film.

Abstract: Disclosed is a semiconductor device including: a titanium nitride film formed over a semiconductor substrate and a tungsten film formed over the titanium nitride film. The titanium nitride film contains carbon and the tungsten film contains boron. A tungsten hexafluoride gas and a diborane gas are used in formation of the tungsten film.

Abstract: Disclosed herein is a device that includes: first to fourth conductive lines embedded in a semiconductor substrate; a first semiconductor pillar located between the first and second conductive lines; a second semiconductor pillar located between the second and third conductive lines; a third semiconductor pillar located between the third and fourth conductive lines; a first storage element connected to an upper portion of the first semiconductor pillar; a second storage element connected to an upper portion of the third semiconductor pillar; and a bit line embedded in the semiconductor substrate connected to lower portions of the first to third semiconductor pillars. At least one of the first and second conductive lines and at least one of the third and fourth conductive lines being supplied with a potential so as to form channels in the first and third semiconductor pillars.

Abstract: A multi-gate structure is used and a width (d1) of a high concentration impurity region sandwiched by two channel forming regions in a channel length direction is set to be shorter than a width (d2) of low concentration impurity regions in the channel length direction. Thus, a resistance of the entire semiconductor layer of a TFT which is in an on state is reduced to increase an on current. In addition, a carrier life time due to photoexcitation produced in the high concentration impurity region can be shortened to reduce light sensitivity.