Abstract: The present disclosure provides manufacturing techniques and semiconductor devices in which performance of P-channel transistors may be enhanced on the basis of a stress mechanism that involves the deposition of a dielectric bi-layer system. Contrary to conventional strategies, an additional pre-treatment may be performed prior to the deposition of an adhesion layer in a plasma-free process atmosphere, thereby enabling a reduced thickness of the adhesion layer and a higher internal stress level of the subsequent top layer.

Abstract: An electronic apparatus includes a main board, a semiconductor package, an upper conductive EMI shield member, and a lower conductive EMI shield member. The main board includes a first ground pad. The semiconductor package is spaced apart from and electrically connected to the main board. The upper conductive EMI shield member covers a top surface and a sidewall of the semiconductor package. The lower conductive EMI shield member surrounds a space between the main board and the semiconductor package, and is electrically connected to the upper conductive EMI shield member and the first ground pad.

Abstract: In a preferred embodiment, a wiring board with embedded device and electromagnetic shielding includes a shielding frame, a semiconductor device, a stiffener, a first build-up circuitry and a second build-up circuitry with a shielding lid. The first and second build-up circuitries cover the semiconductor device, the shielding frame and the stiffener in the opposite vertical directions. The shielding frame and the shielding lid are electrically connected to at least one ground contact pad of the semiconductor device by the first build-up circuitry and can respectively serve as effective horizontal and vertical electromagnetic shields for the semiconductor devices within the aperture of the stiffener.

Abstract: A shielding structure for transmission lines comprises first and second comb-like structures defined in a first metallization layer on an integrated circuit, the teeth of each comb-like structure extending toward the other comb-like structure; a first plurality of electrically conducting vias extending upward from the first comb-like structure; a second plurality of electrically conducting vias extending upward from the second comb-like structure; first and second planar structures in a second metallization layer above the first metallization layer; a third plurality of electrically conducting vias extending downward from the first planar structure toward the first plurality of electrically conducting vias; and a fourth plurality of electrically conducting vias extending downward from the second planar structure toward the second plurality of electrically conducting vias.

Abstract: In a preferred embodiment, a wiring board with embedded device and electromagnetic shielding includes a semiconductor device, a core layer, a shielding lid, shielding slots and build-up circuitry. The build-up circuitry covers the semiconductor device and the core layer. The shielding slots and the shielding lid are electrically connected to at least one ground contact pad of the semiconductor device by the build-up circuitry and can respectively serve as effective horizontal and vertical electromagnetic shields for the semiconductor devices.

Abstract: In one embodiment, a semiconductor die is formed to have sloped sidewalls. A conductor is formed on the sloped sidewalls.

Abstract: A semiconductor device has a connection structure in which a power semiconductor chip is mounted on an insulating substrate having conductor patterns bonded to front and rear surfaces thereof, and the insulating substrate is connected to a heat-dissipating base member to dissipate heat generated from the power semiconductor chip to outside. The conductor pattern on the rear surface bonded to the heat-dissipating base member has a bonding portion having a rectangular shape and a predetermined curvature radius in vicinity of corners.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing an array of leads having a jumper lead and a covered contact; coupling an insulated bonding wire between the jumper lead and the covered contact; attaching an integrated circuit die over the covered contact; and coupling a bond wire between the integrated circuit die and the jumper lead including coupling the integrated circuit die to the covered contact through the insulated bonding wire.

Abstract: A metal leadframe strip (500) for semiconductor devices comprising a plurality of sites (510) for assembling semiconductor chips, the sites alternating with zones (520) for connecting the leadframe to molding compound runners; the sites (510) having mechanically rough and optically matte surfaces (511, 512); the zones (520) having at least portions with mechanically flattened and optically shiny metal surfaces (521, 522); and the flattened surface portions transitioning into the rough surface portions by a step.

Abstract: An electronic switching device array encapsulated in an encapsulating structure; wherein said array is exposed to one or more gas pockets between said array and said encapsulating structure.

Abstract: A semiconductor device includes a base substrate made of silicon, a cap substrate and a leading electrode having a metal part. The base substrate has base semiconductor regions being insulated and separated from each other at a predetermined portion of a surface layer thereof. The cap substrate is bonded to the predetermined portion of the surface layer of the base substrate. The leading electrode has a first end connected to one of the plurality of base semiconductor regions of the base substrate Wand extends through the cap substrate such that a second end of the leading electrode is located adjacent to a surface of the cap substrate for allowing an electrical connection with an external part, the surface being opposite to a bonding surface at which the base substrate and the cap substrate are bonded. The leading electrode defines a groove between an outer surface thereof and the cap substrate.

Abstract: A semiconductor device package is formed of DBC in which thinned MOSgated and/or diode die are soldered to the bottom of an etched depression in the upper conductive layer. A via in the insulation layer of the DBC is filled with a conductive material to form a resistive shunt. Plural packages may be formed in a DBC card and may be separated individually or in clusters. The individual packages are mounted in various arrays on a support DBC board and heat sink. Integrated circuits may be mounted on the assembly and connected to the die for control of the die conduction.

Abstract: An integrated circuit package is presented. In an embodiment, the integrated circuit package has a package substrate, an integrated circuit die attached to the package substrate, and a package level heat dissipation device, such as an integrated heat spreader, attached to the package substrate encapsulating the integrated circuit die. The package level heat dissipation device has a top side with a ridge formed on top of a perimeter of the top side, and a bottom side that couples to the integrated circuit die.

Abstract: An integrated circuit includes a main body, a number of connection tabs molded on the main body, and a number of pins respectively connected to the connection tabs. The connection tabs and the pins are made of metal. The connection tabs are electrically connected to a logic circuit in the main body.

Abstract: A semiconductor package includes a passivation layer overlying a semiconductor substrate, a bump overlying the passivation layer, and a molding compound layer overlying the passivation layer and covering a lower portion of the bump. A sidewall of the passivation layer is covered by the molding compound layer.

Abstract: Structure and methods for forming a semiconductor structure. The semiconductor structure includes a plurality of layers comprising at least one copper interconnect layer. The copper interconnect layer provides an electrical conduit between one of physically adjacent layers in the semiconductor structure and an integrated circuit in the semiconductor structure and an electronic device. A plurality of studs is positioned within the at least one copper interconnect layer. The studs are spaced apart by a distance less than or equal to a Blech length of the at least one copper interconnect layer. The Blech length is a length below which damage due to electromigration of metal atoms within the at least one copper interconnect layer does not occur. The plurality of studs comprises copper atom diffusion barriers.

Abstract: A Multi-Chip Module is presented herein that comprises a package substrate, at least two integrated circuit devices, each of which is electrically coupled to the package substrate, and an interposer. Formed in the interposer are electrical connections which are predominantly horizontal interconnects. The first interposer is arranged to electrically couple the two integrated circuit devices to each other. Methods for manufacturing a Multi-Chip Module are also presented herein.

Abstract: The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance.

Abstract: A conductive bump includes a step member formed to form a step on a portion of a connection pad; and a conductive member formed on the connection pad and the step member and having an inclined surface which is inclined with respect to the connection pad.

Abstract: A solder on trace device includes a conductive trace on a semiconductor substrate surface. The conductive trace has a sidewall and a bonding surface. The solder on trace device also includes a passivation layer on at least one end of the conductive trace. The solder on trace device further includes a pre-solder material on the sidewall and the bonding surface of the conductive trace.

Abstract: A semiconductor device has a first interconnect structure. A first semiconductor die has an active surface oriented towards and mounted to a first surface of the first interconnect structure. A first encapsulant is deposited over the first interconnect structure and first semiconductor die. A second semiconductor die has an active surface oriented towards and mounted to a second surface of the first interconnect structure opposite the first surface. A plurality of first conductive pillars is formed over the second surface of the first interconnect structure and around the second semiconductor die. A second encapsulant is deposited over the second semiconductor die and around the plurality of first conductive pillars. A second interconnect structure including a conductive layer and bumps are formed over the second encapsulant and electrically connect to the plurality of first conductive pillars and the first and second semiconductor die.

Abstract: A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and has a coupling part between parts with different widths, a pad being formed above the wiring and in a position overlapping the coupling part, a bump being formed on the pad, a buffer layer being formed in a position between the coupling part and the pad so as to cover the entire coupling part, and inorganic insulating layers being formed between the wiring and the buffer layer and between the buffer layer and the pad, respectively.

Abstract: A semiconductor device assembly includes a substrate having an area of the surface treated to form a surface roughness. A die is mounted on the substrate by a plurality of coupling members. An underfill substantially fills a gap disposed between the substrate and the die, wherein a fillet width of the underfill is substantially limited to the area of surface roughness.

Abstract: An integrated circuit device including a substrate, a first internal bonding pad, a second internal bonding pad, an external bonding pad and a bonding wire is provided. A first circuit and a second circuit are embedded in the substrate. The first internal bonding pad is disposed on a surface of the substrate and electrically coupled to the first circuit. The second internal bonding pad is disposed on the surface of the substrate and electrically coupled to the second circuit. The second internal bonding pad is electrically coupled to the first internal bonding pad via the bonding wire. The external bonding pad is electrically coupled to the first internal bonding pad.

Abstract: An interconnect assembly that operates in environments well exceeding 200° C. without degradation and/or failure. The interconnect assembly of the present invention eliminates the incompatible metal interfaces of the prior art and relies on aluminum first-metal wire to electrically connect to first-metal pads on a chip and a second-metal wire to electrically connect to second-metal plated contacts on a package. Both wire types are then electrically connected together utilizing a high temperature transition pad disposed between the chip and contacts on the package, therefore eliminating incompatible metal interfaces of the prior art.

Abstract: A semiconductor device includes a semiconductor substrate having two surfaces. First side faces second side and includes recesses, and a plurality of through silicon vias (TSV), which penetrate through the semiconductor substrate, are exposed by the recesses. Even when the TSVs have different heights from each other or the degree of back-grinding is changed, due to a process parameters, yield of the semiconductor device is improved by reducing failure caused when a TSV is not exposed.

Abstract: A semiconductor device and a method for fabricating the same are disclosed, which can prevent migration of copper (Cu) ion when forming a Through Silicon Via (TSV). The semiconductor device includes a through silicon via (TSV) formed to pass through a semiconductor substrate; an oxide film located at a lower sidewall of the TSV; and a first prevention film formed to cover an upper portion of the TSV, an upper sidewall of the TSV, and an upper surface of the oxide film.

Abstract: A semiconductor device includes a first insulating layer on a substrate; a first contact hole passing through the first insulating layer and exposing an upper surface of the substrate; a first barrier metal layer disposed on a sidewall and at a bottom of the first contact hole and a first metal plug disposed on the first barrier metal layer and in the first contact hole. A recess region is between the first insulating layer and the first metal plug. A gap-fill layer fills the recess region; and a second insulating layer is on the gap-fill layer. A second contact hole passes through the second insulating layer and exposes the upper surface of the first metal plug. A second barrier metal layer is on a sidewall and at the bottom of the second contact hole; and a second metal plug is on the second barrier metal layer.

Abstract: A semiconductor device and method are disclosed. The semiconductor device includes a substrate having a first region and a second region and an insulating layer arranged on the substrate. A first conductive layer is arranged in or on insulating layer in the first region and a second conductive layer is arranged in or on the insulating layer in the second region. The first conductive layer comprises a first conductive material and the second conductive layer comprises a second conductive material wherein the first conductive material is different than the second conductive material. A metal layer is arranged on the first conductive layer.

Abstract: A chip contact pad and a method of making a chip contact pad are disclosed. An embodiment of the present invention includes forming a plurality of contact pads over a workpiece, each contact pad having lower sidewalls and upper sidewalls and reducing a lower width of each contact pad so that an upper width of each contact pad is larger than the lower width. The method further includes forming a photoresist over the plurality of contact pads and removing portions of the photoresist thereby forming sidewall spacers along the lower sidewalls.

Abstract: A mounted structure includes an electrode of a substrate, an electrode of a semiconductor element, and a mounted layers for bonding the electrode of the substrate and the electrode of the semiconductor element, and the mounted layers includes: a first intermetallic compound layer containing a CuSn-based intermetallic compound; a Bi layer; a second intermetallic compound layer containing a CuSn-based intermetallic compound; a Cu layer; and a third intermetallic compound layer containing a CuSn-based intermetallic compound, and the above layers are sequentially arranged from the electrode of the substrate toward the electrode of the semiconductor element to configure the mounted layers.

Abstract: Some embodiments include methods of forming conductive structures. An electrically conductive material may be deposited with a first deposition method. The first deposition method has a first deposition rate and forms a first portion of a conductive structure. A second portion of the conductive structure may be formed by depositing the electrically conductive material with a second deposition method having a second deposition rate. The second deposition rate may be different from the first deposition rate by at least about a factor of 3. In some embodiments, a region of the conductive structure is utilized as a transistor gate of a DRAM cell. Some embodiments include semiconductor constructions.

Abstract: The present invention relates to an interconnect substrate with an embedded device, a built-in stopper and dual build-up circuitries and a method of making the same. In accordance with one preferred embodiment of the present invention, the method includes: forming a stopper on a dielectric layer; mounting a semiconductor device on the dielectric layer using the stopper as a placement guide for the semiconductor device; attaching a stiffener to the dielectric layer; forming a first build-up circuitry and a second build-up circuitry that cover the semiconductor device, the stopper and the stiffener at both sides; and providing a plated through-hole that provides an electrical connection between the first and second build-up circuitries. Accordingly, the stopper can accurately confine the placement location of the semiconductor device and avoid the electrical connection failure between the semiconductor device and the build-up circuitry.

Abstract: A nonvolatile memory device including a substrate which includes a cell array region and a connection region, an electrode structure formed on the cell array region and the connection region and including a plurality of laminated electrodes, a first recess formed in the electrode structure on the connection region and disposed between the cell array region and a second recess formed in the electrode structure on the connection region, and a plurality of vertical wirings formed on the plurality of electrodes exposed by the first recess.

Abstract: A method (112) of forming a sensor panel (146) that includes an array (144) of sensor structures (22, 24) encapsulated in a mold material (148) and forming a controller panel (158) that includes an array (156) of controller dies (26) encapsulated in a mold material (160). The arrays (144, 156) are arranged so that locations of the sensor structures (22, 24) correspond with locations of the controller dies (26). The controller panel (158) is bonded (162) to the sensor panel (146) to form a stacked panel structure (164). After bonding, methodology (112) entails forming (178) conductive elements (84) on the controller dies (26), removing (174) material sections (126, 142, 168) from the controller panel 158 and the sensor panel (146) to expose bond pads (42, 58), forming (178) electrical interconnects (80), applying (182) packaging material (90), and singulating (196) the stacked panel structure (164) to produce sensor packages (20, 104).

Abstract: A system package includes an interposer, a control chip mounted onto the interposer, and first and second semiconductor chips mounted onto the interposer and electrically coupled to the control chip through the interposer. The first and second chips are configured to operate under the control of the control chip. The first semiconductor chip is positioned along one side of the control chip, and the second semiconductor chip is positioned along another side of the control chip.

Abstract: A semiconductor memory device includes a first chip and a second chip connected to the first chip physically and electrically, wherein the first chip and the second chip are coupled by through silicon vias (TSVs) formed in a first region, and the first chip and the second chip are coupled by alignment keys formed in second regions.

Abstract: The present invention relates to a thermally enhanced interconnect substrate and a method of making the same. In accordance with one preferred embodiment, the method includes: forming a stopper on a metal layer of a laminate substrate; removing a selected portion of the metal layer to form a paddle layer; mounting a semiconductor device on the paddle layer using the stopper as a placement guide for the semiconductor device; attaching a stiffener to the laminate substrate; forming first and second build-up circuitries that cover the semiconductor device, the paddle layer and the stiffener at both sides; and providing a plated through-hole that provides an electrical connection between the first and second build-up circuitries. Accordingly, the paddle layer can provide excellent heat spreading, and the stopper can accurately confine the placement location of the semiconductor device and avoid the electrical connection failure between the semiconductor device and the build-up circuitry.

Abstract: The present invention relates to a thermally enhanced semiconductor assembly and a method of making the same. In accordance with one preferred embodiment, the method includes: forming a stopper on a metal layer; mounting a semiconductor device on the metal layer using the stopper as a placement guide for the semiconductor device; attaching a stiffener to the metal layer; forming a build-up circuitry that covers the stopper, the semiconductor device and the stiffener; providing a plated through-hole that provides an electrical connection between the build-up circuitry and the metal layer; and removing selected portions of the metal layer to form a thermal pad and a terminal. Accordingly, the thermal pad can provide excellent heat spreading, and the stopper can accurately confine the placement location of the semiconductor device and avoid the electrical connection failure between the semiconductor device and the build-up circuitry.

Abstract: A semiconductor assembly includes a semiconductor device, a through-via interposer, a coreless substrate and a stiffener. The semiconductor device is flip mounted on the interposer, and the interposer is affixed on the coreless substrate by adhesive and extends into an aperture of a stiffener which provides mechanical support for the coreless substrate. The electrically connection between the interposer and the coreless substrate includes bond wire and conductive micro-via. The coreless substrate can provide fan-out routing for the interposer.

Abstract: Semiconductor device including through via structure and redistribution structures is provided. The semiconductor device may include internal circuits on a first side of a substrate, a through via structure vertically penetrating the substrate to be electrically connected to one of the internal circuits, a redistribution structure on a second side of the substrate and electrically connected to the through via structure, and an insulating layer between the second side of the substrate and the redistribution structure. The redistribution structure may include a redistribution barrier layer and a redistribution metal layer, and the redistribution barrier layer may extend on a bottom surface of the redistribution metal layer and may partially surround a side of the redistribution metal layer.

Abstract: A method of fabricating semiconductor structures comprising sub-resolution alignment marks is disclosed. The method comprises forming a dielectric material on a substrate and forming at least one sub-resolution alignment mark extending partially into the dielectric material. At least one opening is formed in the dielectric material. Semiconductor structures comprising the sub-resolution alignment marks are also disclosed.

Abstract: A microelectronic assembly is provided in which first and second electrically conductive pads exposed at front surfaces of first and second microelectronic elements, respectively, are juxtaposed, each of the microelectronic elements embodying active semiconductor devices. An electrically conductive element may extend within a first opening extending from a rear surface of the first microelectronic element towards the front surface thereof, within a second opening extending from the first opening towards the front surface of the first microelectronic element, and within a third opening extending through at least one of the first and second pads to contact the first and second pads. Interior surfaces of the first and second openings may extend in first and second directions relative to the front surface of the first microelectronic element, respectively, to define a substantial angle.

Abstract: In a preferred embodiment, a semiconductor assembly board with back-to-back embedded devices and built-in stoppers includes an intermediate layer, a first stopper, a first semiconductor device, a first core layer, a second stopper, a second semiconductor device, a second core layer, a first build-up circuitry, a second build-up circuitry and a plated through hole. The first and second semiconductor devices are mounted on opposite surfaces of the intermediate layer using the first and second stoppers as placement guides that are laterally aligned with peripheral edges of the first and second semiconductor devices. The first and second core layers laterally cover the first and second semiconductor devices. The first and second build-up circuitries cover the semiconductor devices and the core layers in the opposite vertical directions and provide signal routing for the first and second semiconductor devices.

Abstract: Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.

Abstract: A PoP (package-on-package) package includes a bottom package with a substrate encapsulated in an encapsulant with a die coupled to the top of the substrate. At least a portion of the die is exposed above the encapsulant on the bottom package substrate. A top package includes a substrate with encapsulant on both the frontside and the backside of the substrate. The backside of the top package substrate is coupled to the topside of the bottom package substrate with at least part of the die being located in a recess in the encapsulant on the backside of the top package substrate.

Abstract: A method of making contact pad sidewall spacer and pad sidewall spacers are disclosed. An embodiment includes forming a plurality of contact pads on a substrate, each contact pad having sidewalls, forming a first photoresist over the substrate, and removing the first photoresist from the substrate thereby forming sidewall spacers along the sidewalls of the plurality of the contact pads.

Abstract: A microelectronic package having an encapsulated substrate comprising a plurality of microelectronic devices encapsulated within an encapsulation material, wherein the encapsulated structure may have an active surface proximate the active surfaces of the plurality of microelectronic devices, and wherein at least one of the plurality of microelectronic devices may have a height greater than another of the plurality of microelectronic devices (e.g. non-coplanar), The microelectronic package further includes a bumpless build-up layer structure formed proximate the encapsulated structure active surface. The microelectronic package may also have an active surface microelectronic device positioned proximate the encapsulated structure active surface and in electrical contact with at least one of the plurality of microelectronic devices of the encapsulated substrate.

Abstract: There are provided a package substrate, a manufacturing method thereof, and a mold therefor. The method of manufacturing a package substrate includes: preparing a chip component and a substrate; mounting the chip component on a main surface of the substrate; preparing a mold having a cavity and protrusions formed on a ceiling surface thereof; disposing the substrate on a bottom surface of the mold such that the chip component is positioned within the cavity; and forming a resin sealing body that collectively hermetically seals the chip component and the main surface of the substrate by injecting a pressurized liquid resin into the cavity.

Abstract: A diffusor for diffusing a gas into a liquid including a membrane, a supporting structure supporting the membrane and a holder arranged to connect the supporting structure to a gas supply conduit, at least a part of the membrane being perforated. The membrane defines an inner chamber, and at least a part of the supporting structure is arranged in the inner chamber of the membrane, the supporting structure including at least one channel extending from an inlet opening that is in, direct or indirect, fluid communication with the gas supply conduit to an outlet opening that is in fluid communication with the inner chamber of the membrane.