Abstract: A transformer core apparatus includes a body of highly magnetically permeable material, a permanent magnet arranged in a safe state position for saturating the body with a permanent magnetic field, and means for removing the permanent magnetic field from the body.

Abstract: An arrangement for monitoring a condition of a direct current voltage circuit including first and second supply poles for forming an operating voltage. A first fuse is connected to the first supply pole, and has a supply pole and an output pole. A second fuse is connected to the second supply pole, and has a supply pole and an output pole. The arrangement can form one or several reference voltages (UREFa,UREFb,UREFc), can form a first measurement voltage (U1a,U1b,U1c,U1d) between the output pole of the first fuse and the supply pole of the second fuse, and can form a second measurement voltage (U1a,U1b,U1c,U1d) between the output pole of the second fuse and the supply pole of the first or the second fuse. One or several reference voltages and measurement voltages can be compared to estimate a condition of the first and second fuse, and a comparison result can be indicated.

Abstract: A diagnostic/prognostics system for failure detection in an electrical insulation system is provided. The system includes at least two current transformers designed to detect high frequency component signals from the insulation system. The system also includes a data acquisition module coupled to the at least two current transformers, wherein the data acquisition module receives the high frequency component signals and analyzes the received high frequency component signals to identify one or more faulty components in the electrical insulation system.

Abstract: Disclosed is a device under test (DUT) tester using a redriver. The DUT tester more effectively tests the DUT, which is a predetermined semiconductor device, by applying an electrical signal to the DUT and measuring the electrical signal. The DUT tester includes a DUT test unit, a printed circuit board (PCB) provided therein with connectors for the connection with the DUT test unit, one DUT or more horizontally arranged on the PCB, and redrivers horizontally provided under the PCB and one-to-one matched with one DUT or more to compensate for the distortion of the signal integrity of test signals caused according to the variation of the transmission distance.

Abstract: A capacitive sensor includes a transmit electrode configured to provide an alternating electric field to a sensor; one or more receive electrodes for detecting variations in the alternating electric field; and an adaptive frequency adjustment unit configured to adjust an operating frequency of the alternating electric field responsive to detection of a noise measure, such as noise power.

Abstract: A passive intermodulation test device includes a first signal generator that generates a first signal and a second signal generator that generates a second signal. A combiner combines the first signal and the second signal to generate a combined signal. A duplexer receives a test signal based, at least in part, on the combined signal and filters the first signal and the second signal from the test signal to generate an intermodulation signal. A variable low-noise amplifier amplifies the intermodulation signal in accordance with a variable gain based at least in part on a selected power level. A receiver, upon receipt of the intermodulation signal, measures intermodulation generated by a device under test.

Abstract: This invention relates to methods and apparatus for measuring physical properties using microwave cavity sensors. In operation, a number of microwave cavity sensors are interrogated by a remote wireless unit in order to determine the current resonant frequency for the sensor. The current values for various parameters measured by the sensors, such as temperature, stress/stain, or the like, are determined by comparing the current resonant frequency to a first resonant frequency of the sensor, and thus, detect any change in the value of the selected parameter. In particular, the present invention is directed toward extending the range over which such measurements may be performed, using these types of sensors.

Abstract: A system for measuring electrical charge, comprising a capacitance detector (110) connected to a charge integrator (120) being an operational amplifier with a capacitance feedback (130), in which the input stage (121) of the charge integrator (120) comprises a pair of symmetrically connected JFET-type transistors (T1; T2), having gates connected to the input of the charge integrator (120).

Abstract: The method and device for analyzing position are disclosed. By analyzing sensing information with at least one zero-crossing, each position can be analyzed. The number of analyzed positions may be different from the number of zero-crossings. When the number of analyzed positions is different from the number of zero-crossing, the number of analyzed positions is more than one.

Abstract: In one embodiment, a touch sensor includes multiple first electrodes on a first surface. The first electrodes include a first shape. The touch sensor includes multiple second electrodes on a second surface. The second electrodes include a second shape. The touch sensor includes multiple third electrodes on the first surface that include a third shape that encompasses the second shape and are positioned on the first surface opposite the second electrodes. The touch sensor includes multiple fourth electrodes on the second surface that include a fourth shape that encompasses the first shape and are positioned on the second surface opposite the first electrodes.

Abstract: A dual-electrode occupant detection system configured to determine an occupant presence on a seat assembly. The system includes two electrodes that each generates an electric field in response to an applied excitation signal. The two electrode signals arising therefrom can be measured individually and/or combined to detect more reliably an occupant. Such a configuration advantageously avoids the added expense and complication of an electrode arrangement that relies on an underlying shield layer to reduce electrode signal degradation caused by a seat heater element.

Abstract: A sensor includes a variable capacitor, a fixed capacitor, an inductor, a switch that electrically connects the variable capacitor with the inductor or the fixed capacitor with the inductor, an oscillator that generates a periodic signal, and a controller connected to the switch, the oscillator, and the inductor. The controller operates the switch, identifies a frequency of a first oscillation of the variable capacitor and the inductor based on the periodic signal from the oscillator, identifies a frequency of a second oscillation of the fixed capacitor and the inductor based on the periodic signal from the oscillator, and identifies a capacitance of the variable capacitor based on a ratio of the frequency of the first oscillation to the frequency of the second oscillation.

Abstract: An apparatus and system for measuring levels of two or more materials maintained within a storage tank using a combination of both a capacitance sensor and a time domain reflectometry (“TDR”) waveguide sensor is disclosed. The apparatus includes a combined circuit for the capacitance sensor and TDR sensor that creates a separation between the return signal from the capacitance sensor and the TDR sensor. The need for the return signal separation is due to the generation of false reflection signals from the capacitance circuitry. In a preferred embodiment, the separation in time is created by moving the capacitance false reflections further in time than the true signal returns. An alternative preferred embodiment would delay the true TDR signals passed the capacitance false reflections. Another alternative preferred embodiment would provide a substantially matched impedance of the capacitance circuit to the TDR circuit, to substantially eliminate the false reflections.

Abstract: A compensating circuit which has a programmable capacitance array for measuring AC voltage is disclosed in the present invention. The compensating circuit includes a pair of first leads for linking to an AC circuit; a variable capacitor, electrically linked to the first leads, for providing different capacitance value according to a programmable capacitance array; and a control unit, electrically linked to the first leads, for changing the capacitance value of the variable capacitor as one capacitance of the programmable capacitance array according to an external instruction. Since the capacitance of the compensating circuit is changeable, and AC voltage meter designed with the compensating circuit is able to measure voltage in wider range of frequency.

Abstract: The invention relates to a lithography system. The lithography system has a projection lens system and a capacitive sensing system. The projection lens system is provided with a final projection lens. The capacitive sensing system is arranged for making a measurement related to a distance between the final projection lens and a target. The capacitive sensing system includes at least one capacitive sensor. Additional, the capacitive sensing system is provided with a flexible printed circuit structure and at least one integrated flex print connector. The at least one sensor is located in the flexible printed circuit structure. The flexible printed circuit structure has a flexible base provided with conductive electrodes for the at least one sensor and conductive tracks. The conductive tracks extend from the electrodes along the at least one integrated flex print connector.

Abstract: A test apparatus includes a plurality of rails, a plurality of test zones and a movable test chamber. The test zones are located between the rails. The movable test chamber includes a passageway, at least one heat source and at least one pair of rolling balls. The heat source is used to heat the passageway. The pair of rolling balls is movably contained in two rails, so as to facilitate movement of the passageway to different test zones.

Abstract: The present disclosure relates to a test head for electrical testing of a test specimen, in particular a wafer, having at least two guide plates, which are spaced apart by means of at least one spacer and have guide holes distributed over the surfaces thereof, in which test contact pins for physical contact with the test specimen are guided in a sliding manner. Provision is made for the spacer to be formed by a multiplicity of point supports arranged in a manner distributed over the surfaces of the guide plates and secured on the guide plates.

Abstract: A testing apparatus for electronic components comprises a mounting block and a plurality of contact strips arranged on the mounting block. The contact strips are configured such that electrical leads of an electronic component are operative to press against and bend the contact strips in a biasing direction to ensure good contact between the electrical leads and the contact strips during testing of the electronic component. Further, a preload block located on the mounting block is operative to contact and apply a pre-stress force onto the contact strips in the biasing direction prior to contact between the electrical leads and the contact strips.

Abstract: A multi-chip semiconductor apparatus includes a plurality of semiconductor chips stacked and packaged therein, wherein each of the semiconductor chips includes: a through-silicon via (TSV) formed through the semiconductor chip; a probe pad exposed to an outside of the semiconductor chip so as to enable a probing test; a bump pad exposed to the outside of the semiconductor chip and electrically connected to the TSV; and a conductive layer electrically connecting the probe pad and the bump pad inside the semiconductor chip.

Abstract: The present disclosure relates to a diagnosis framework to shorten yield learning cycles of technology node manufacturing processes from the high defect density stage to technology maturity. A plurality of defect under test (DUT) structures are designed to capture potential manufacturing issues associated with defect formation. A test structure is formed by arranging the DUT structures within a DUT carrier unit, which has been yield-hardened though heuristic yield analysis such that a defect density of the DUT carrier unit is essentially zero. Possible outcomes of an application of test patterns and various failure scenarios associated with defects formed within the DUT structures within the DUT carrier unit are simulated and stored in a look-up table (LUT). The LUT may then be referenced to determine a location of a defect within the test structure without the need for iterative analysis to correctly select defect candidates for physical failure analysis (PFA).

Abstract: A photovoltaic device includes a substrate extending between opposite edges, a plurality of photovoltaic cells electrically coupled with each other in series, wherein the plurality of photovoltaic cells includes at least one current-limiting photovoltaic cell, and at least one corrective optic lens positioned over the at least one current-limiting photovoltaic cell. The at least one corrective optic lens is configured to focus light into the at least one current-limiting photovoltaic cell so that current passing through the current-limiting photovoltaic cell is boosted. A monitoring system may include at least one light source aligned with at least one of the plurality of photovoltaic cells. The light source(s) may be configured to emit light into the at least one of the plurality of photovoltaic cells to determine if the power output of the photovoltaic device remains constant.

Abstract: A method for detecting a semiconductor device property is provided. First, a semiconductor device is provided. Thereafter, a detecting current is applied and the semiconductor device is heated, and temperatures and voltages of the semiconductor device are measured, so as to establish a relationship between the temperatures and the voltages of the semiconductor device. Accordingly, a temperature sensitive parameter (TSP) is calculated. An apparatus for detecting a semiconductor device property is also provided.

Abstract: A test device for testing a semiconductor device including a TSV may comprise a ring oscillator including a plurality of inverters, a switch selectively connecting an output node of an inverter of the plurality of inverters and the TSV, and a controller controlling the switch.

Abstract: A method for discovering demagnetisation faults of a permanent magnet synchronous generator, such as a wind power generator. The method is performed during operation of the synchronous generator and includes measuring the vibration of the stator, performing a frequency analysis of the vibration, and deducing whether the generator suffers from demagnetization of a permanent magnet, from the vibration analysis. Moreover, geometric eccentricity faults and electric short circuit faults may also be detected from the vibration.

Abstract: The disclosure relates generally to sequential state elements (SSEs), triple-mode redundant state machines (TMRSMs), and methods and systems for testing triple-mode redundant pipeline stages (TMRPSs) within the TMRSMs using triple-mode redundant SSEs (TMRSSEs). The SSEs, TMRSMs, TMRPSs, and TMRSSEs may be formed as integrated circuits on a semiconductor substrate. Of particular focus in this disclosure are SSEs used to sample and hold bit states. Embodiments of the SSEs have a self-correcting mechanism to protect against radiation-induced soft errors. The SSE may be provided in a pipeline circuit of a TMRSM to receive and store a bit state of a bit signal generated by combinational circuits within the pipeline circuit. More specifically, the SSEs may be provided in a TMRSSE configured to perform self-correction. Also disclosed are methods for using the TMRSSE to test redundant pipeline stages of the TMRSM.

Abstract: Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.

Abstract: Systems and methods for clock generation and distribution are disclosed. Embodiments include arrangements of synchronization signals implemented using a mesh circuit. The mesh circuit is comprised of a plurality of null convention logic (NCL) gates organized into rings. Each ring shares at least one NCL gate with an adjacent ring. The rings are configured in such a way that each ring in the mesh operates synchronously with the other rings in the mesh.

Abstract: A method for increasing performance in a limited switch dynamic logic (LSDL) circuit includes precharging a dynamic node during a precharge phase of a first and second evaluation clock signal. The dynamic node is evaluated to a first logic value in response to one or more first input signals of a first evaluation tree during an evaluation phase of the first evaluation clock signal. The dynamic node is evaluated to a second logic value in response one or more second input signals of a second evaluation tree during an evaluation phase of the second evaluation clock signal. A signal of the LSDL circuit is outputted in response to the dynamic node according to an output latch clock signal.

Abstract: There is disclosed an integrated circuit comprising a management unit for managing the occurrence of predetermined events in the integrated circuit. The management unit comprises: a processing unit adapted to determine the occurrence of a predetermined event in the integrated circuit; a data storage unit adapted to store information regarding the determined event occurrence; an output interface adapted to output a signal based on the stored information regarding the determined event occurrence; and an output generating unit adapted to analyse the stored information and to generate a signal to be output by the output interface based on results of the analysis.

Abstract: An approach for a sampling circuit to reduce noise in signals (e.g., as received from photo diodes or the like) is provided. In one embodiment of the present invention, there is a sampling circuit comprising: an amplifier, which amplifies charge signals generated at photo diodes and converts them to voltage signals; the first sample and hold circuit, which samples the voltage signal and charges the first capacitor according to the first switching signal, and outputs the stored charge as a reset signal based on a readout signal; the second sample and hold circuit, which samples the signals and charges the second capacitor according to the second switching signal that is non-overlapping to the first switching signal, and outputs the stored charge as a reset signal based on the readout signal; a resistor that acts as a low-pass filter placed in between the first and the second capacitors' common nodes.

Abstract: An integrated circuit (IC) package includes electrical contacts disposed at a first surface of the IC package, an integrated circuit implementing an electrical signaling interface, and a connector assembly accessible at a second surface of the IC package. The connector assembly is to mechanically attach to another connector assembly and includes contact terminals electrically coupled to the electrical signaling interface. The connector assembly can be configured to provide friction coupling with the other connector assembly to permit the other connector assembly to be removably attached. A system includes the IC package and an external transceiver module having a connector assembly mechanically attached to the connector assembly of the IC package. The electrical signaling interface conducts signaling with the external transceiver module in accordance with one signal format and the external transceiver module conducts signaling over a transmission medium in accordance with another signal format.

Abstract: A three-dimensional (3D) gate driver integrated circuit includes a high-side integrated circuit stacked on a low-side integrated circuit where the high-side integrated circuit and the low-side integrated circuit are interconnected using through-silicon vias (TSV). As thus formed, the high-side integrated circuit and the low-side integrated circuit can be formed without termination regions and without buried layers.

Abstract: According to one embodiment, an input buffer includes a comparator that compares an input signal with a reference voltage, an inverter that inverts an output signal of the comparator, and a drive adjusting circuit that adjusts a current driving force of the inverter.

Abstract: A switch-driving circuit suitable for driving a full-controlled power switch combination is disclosed. The switch-driving circuit includes a first pulse-width modulator, a high-voltage isolation pulse transformer module and a plurality of output modules. The high-voltage isolation pulse transformer module includes a magnetic core connected to multiple output modules in a one-to-many way, or includes multiple magnetic cores connected to multiple output modules in a one-to-one way. Each output module includes a second pulse-width modulator and a driving-power amplifier. The full-controlled power switch combination includes a plurality of full-controlled power switches. The driving-power amplifier is coupled between the second pulse-width modulator and one of the full-controlled power switches.

Abstract: An electronic device may include a first transistor having a normally-on characteristic; a second transistor connected to the first transistor and having a normally-off characteristic; a constant voltage application unit configured to apply a constant voltage to a gate of the first transistor; and a switching unit configured to apply a switching signal to the second transistor. The first transistor may be a high electron mobility transistor (HEMT). The second transistor may be a field-effect transistor (FET). The constant voltage application unit may include a diode connected to the gate of the first transistor; and a constant current source connected to the diode.

Abstract: A gate drive circuit includes: an input port for receiving a control signal; an output port; a capacitor connected to the output port; a modulation unit which generates (i) a first modulated signal indicating timing of a first logical value of the control signal and (ii) a second modulated signal indicating timing of at least a second logical value of the control signal; a first electromagnetic resonance coupler which wirelessly transmits the first modulated signal; a second electromagnetic resonance coupler which wirelessly transmits the second modulated signal; a first rectifier circuit which generates a first demodulated signal by demodulating the first modulated signal, and outputs the first demodulated signal to the output port; and a second rectifier circuit which generates a second demodulated signal by demodulating the second modulated signal, and outputs the second demodulated signal to the output port.

Abstract: There are provided a frequency generation apparatus and a frequency generation method. The frequency generation apparatus includes a current generation unit varying an amount of current with respect to a temperature change; a capacitor in which charges are charged by the current generation unit; a discharge circuit unit comparing a charging voltage of the capacitor with a previously set first reference voltage and discharging the capacitor; and an output signal generation unit comparing the charging voltage of the capacitor with a previously set second reference voltage and generating an output signal, wherein the current generation unit varies the amount of current so as to maintain a constant frequency.

Abstract: An electrical waveform generating circuit has a programmable current source-driver. A digital switched current source is coupled to the programmable current source-driver and controlled by waveforms stored in the programmable current source-driver. A plurality of MOSFETs is coupled to the programmable current source driver. A first coupled inductor is connected to the plurality of high voltage MOSFETs. A transducer is coupled to the first coupled inductor.

Abstract: A power on reset circuit is capable of changing logic level of reset signal at different threshold voltages.

Abstract: The present invention relates to a bidirectional semiconductor switch (M1, M2) with extremely low control power consumption and a bootstrap circuit which allows reliable start of operation of the switch and the hosting device after unlimited duration of mains interruptions. Intelligent control options are provided by operating from a small energy storage and no extra means are required to recover from a depleted energy storage condition. The absence of audible noise and mechanical wear also enables more frequent recharging cycles and allows smaller and thus cheaper energy storage components.

Abstract: A phase-locked loop (PLL) for clock delay adjustment and a method thereof are disclosed. The method includes the following steps. A reference clock signal and a clock signal are generated. The reference clock signal is fed through an N-divider to generate an output clock signal having a frequency 1/N of the reference clock signal. In a phase frequency detector, a control signal is generated in accordance with a phase difference and a frequency difference between the output clock signal and a feedback signal generated by a voltage controlled oscillator coupled to the phase frequency detector. The control signal is then fed through a charge pump and a loop filter to generate a voltage control signal according to the control signal. Moreover, in an adjustable delay element, a blended delay signal is generated according to a clock signal and the voltage control signal.

Abstract: A voltage controlled oscillator module including a VCO unit and a gain adjustment unit is provided. The VCO unit is configured to generate a frequency signal based on a control voltage. The gain adjustment unit is coupled to the VCO unit and configured to receive a first adjustment voltage, a second adjustment voltage, and a reference voltage and accordingly adjusts the control voltage to adjust a frequency value of the frequency signal. The gain adjustment unit includes an adjustment circuit unit and a reference circuit unit. A first voltage-frequency curve of the frequency value of the frequency signal and a voltage value of the first adjustment voltage changes in response to a structure characteristic of the adjustment circuit unit. Furthermore, a frequency generating system and a method for adjusting a signal frequency of the VCO module are provided.

Abstract: According to embodiments, dual path loop filter circuits are described which have, for example, a single charge pump. The current flow in the DPLF circuit is architected to source, during an injection time period, a first current to the loop filter, sink, also during the injection time period, a second current from the loop filter, wherein the first current has a magnitude of ?*I and the second current has a magnitude of ?*I, and sink, during a linearization time period, a third current from the loop filter, wherein the third current has a magnitude of (???)*I.

Abstract: Systems and methods for synchronization of clock signals are disclosed. In a feedback system such as a delay-lock loop circuit, delays to be applied can be determined adaptively based on a phase difference between a reference signal and a clock signal being delayed. Such adaptive decisions can be made during each feedback cycle, thereby making it possible to achieve a phase lock faster and more efficiently. In some embodiments, such adaptive functionality can be incorporated into existing circuits with minimal impact.

Abstract: A signal transmission circuit includes a pre-driver and a driver. The pre-driver is configured to generate a first drive signal in response to a first delay signal and a first selection signal and to generate a second drive signal in response to a second delay signal, a second selection signal, and a pulse signal. The driver is configured to drive a transmission signal in response to the first and second drive signals. The first delay signal is enabled at a second time which is later than a first time when an input signal is received, the second delay signal is enabled at a third time which is later than the second time, and the pulse signal is enabled at a fourth time which is delayed by a predetermined delay period from the first time.

Abstract: The present disclosure includes systems and methods for sharing bias current. In one embodiment, shared bias current passes through a first level device to one or more second level devices along a bias current path. Multiple active devices may share bias current along a bias current path and process signal along the same or different signal paths. In one embodiment, bias current from one device is split among multiple devices. In another embodiment, bias current is combined from multiple devices into a device. Embodiments may include an interstage circuit along a signal path that improves stability of the circuit.

Abstract: According to one embodiment, a first CMOS inverter receives an input signal corresponding to a first power supply voltage, and is driven by a second power supply voltage which is smaller than the first power supply voltage; a second CMOS inverter is connected to a rear stage of the first CMOS inverter, and is driven by the second power supply voltage; a first driving adjustment circuit adjusts a current driving force of a low level output of the first CMOS inverter; and a second driving adjustment circuit adjusts a current driving force of a low level output of the second CMOS inverter.

Abstract: An up-conversion mixer includes a mixer cell having at least one output node configured to generate an output. The up-conversion mixer further includes a first cascaded transconductance input stage coupled to the mixer cell, the first cascaded transconductance input stage configured to receive an input signal and to reduce a third order harmonic of the output. The up-conversion mixer further includes a second cascaded transconductance input stage coupled to the mixer cell, the second cascaded transconductance input stage configured to receive the input signal and to reduce a third order harmonic of the output.

Abstract: A semiconductor device includes a plurality of oscillation signal generation units configured to output a plurality of oscillation signals whose cycles are adjusted according to a PN ratio, which is a size ratio of a PMOS transistor to an NMOS transistor, and a selection unit configured to selectively output the oscillation signals outputted from the plurality of oscillation signal generation units in response to a test mode signal.

Abstract: Embodiments provide a switching device including one or more field-effect transistors (FETs) and bias circuitry. The one or more FETs may transition between an off state and an on state to facilitate switching of a transmission signal. The one or more FETs may include a drain terminal, a source terminal, a gate terminal, and a body. The biasing circuitry may bias the drain terminal and the source terminal to a first DC voltage in the on state and a second DC voltage in the off state. The first and second DC voltages may be non-negative. The biasing circuitry may be further configured to bias the gate terminal to the first DC voltage in the off state and the second DC voltage in the on state.