Patents Issued in March 4, 2014
  • Patent number: 8663990
    Abstract: A subject of the present invention is to provide a measurement method using an internal standard substance in an electrophoresis where an analyte is a protein or a compound. The present invention relates to a measurement method for an analyte by an electrophoresis, characterized in that a peak of the analyte is identified by using as an internal standard substance (1) a combination of a compound I having 3 or more anion groups in a molecule and a compound II where 1 to 3 groups of the anion groups of said compound I have been substituted by cation groups, or (2) a combination of a compound III having 3 or more cation groups in a molecule and a compound IV where 1 to 3 groups of the cation groups of said compound III have been substituted by cation groups.
    Type: Grant
    Filed: April 27, 2010
    Date of Patent: March 4, 2014
    Assignee: Wako Pure Chemical Industries, Ltd.
    Inventors: Naoyuki Yamamoto, Tatsuo Kurosawa
  • Patent number: 8663991
    Abstract: An automated system is provided for performing slide processing operations on slides bearing biological samples. In one embodiment, the disclosed system includes a slide tray holding a plurality of slides in a substantially horizontal position and a workstation that receives the slide tray. In a particular embodiment, a workstation delivers a reagent to slide surfaces without substantial transfer of reagent (and reagent borne contaminants such as dislodged cells) from one slide to another. A method for automated processing of slides also is provided.
    Type: Grant
    Filed: July 13, 2005
    Date of Patent: March 4, 2014
    Assignee: Ventana Medical Systems, Inc.
    Inventors: Kurt Reinhardt, Charles D. Lemme, Glen Ward, William L. Richards, Wayne Showalter, Brandon Ambler, Austin Ashby, Chris Borchert, Devon C. Campbell, Kimberly Christensen, Matthew Freeman, Andrew Ghusson, Rick Griebel, Kendall B. Hendrick, Miroslav Holubec, Parula Mehta, Vince Rizzo
  • Patent number: 8663992
    Abstract: Process for thermally stabilizing a polymer containing residues of a Sn(II), Sb(III), Pb(II), Bi(III), Fe(II), Ti(II), Ti(III), Mn(II), Mn(III), or Ge(II)-containing catalyst by treating the polymer at a temperature above its melting temperature with a peroxide selected from the group consisting of ketone peroxides, hydroperoxides, peracids, hydrogen peroxide, and mixtures thereof, wherein said peroxide is used in an amount less than 0.2 wt % based on the weight of the polymer and wherein the molar ratio of peroxy functionalities from said peroxide (p) to metal (M) ranges from 1 to 100; said metal (M) being selected from the group consisting of Sn(II), Sb(III), Pb(II), Bi(III), Fe(II), Ti(II), Ti(III), Mn(II), Mn(III), and Ge(II). The invention further relates to a method for determining the metal residue content of a polymer.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: March 4, 2014
    Assignee: Akzo Nobel N.V.
    Inventors: Andreas Herman Hogt, Wilhelm Klaas Frijlink
  • Patent number: 8663993
    Abstract: A dye binding method for protein analysis is disclosed. The method includes the steps of preparing an initial reference dye solution of unknown concentration from an initial reference dye concentrate and creating an electronic signal based upon the absorbance of the initial reference dye solution. Thereafter, an electronic signal is created based upon the absorbance of a dye filtrate solution prepared from the initial reference dye solution and an initial protein sample. The absorbance signals from the reference dye solution and the dye filtrate solution are sent to a processor that compares the respective absorbances and calculates the protein content of the protein sample based upon the difference between the absorbances.
    Type: Grant
    Filed: March 11, 2010
    Date of Patent: March 4, 2014
    Assignee: CEM Corporation
    Inventors: Michael J Collins, Sr., Joseph J Lambert, Timothy A Zawatsky, David L Herman
  • Patent number: 8663994
    Abstract: Analysis of compositions that include saccharides having mannosamine residues, such as the capsular saccharide of N. meningitidis serogroup A, is facilitated by a method comprising the steps of: (i) hydrolysing polysaccharide in the sample, to give a hydrolysate; (ii) subjecting the hydrolysate to liquid chromatography; and (iii) detecting any mannosamine-6-phosphate separated in step (ii).
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: March 4, 2014
    Assignee: Novartis AG
    Inventor: Sandro D'Ascenzi
  • Patent number: 8663995
    Abstract: There are provided a method for analyzing an aqueous ammonium carbamate solution whereby the composition of an unreacted-gas absorber outlet liquid can be specified in real time, and a method for operating an unreacted gas absorber by use of the same.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: March 4, 2014
    Assignee: Toyo Engineering Corporation
    Inventors: Eiji Sakata, Kenji Yoshimoto, Shuhei Nakamura
  • Patent number: 8663996
    Abstract: A system for measuring the oxygen concentration of a gas includes a catalytic reactor, first and second temperature sensors and a control unit. The catalytic reactor includes a combustion catalyst that supports the catalytic combustion of hydrocarbon fuel vapor in a gas stream. The first temperature sensor is located upstream of the catalytic reactor for sensing an upstream temperature of the gas stream, and the second temperature sensor is located downstream of the catalytic reactor for sensing a downstream temperature of the gas stream. The control unit compares the upstream temperature and the downstream temperature to determine the oxygen concentration of the gas stream.
    Type: Grant
    Filed: April 26, 2010
    Date of Patent: March 4, 2014
    Assignee: Hamilton Sundstrand Corporation
    Inventor: William Beeson
  • Patent number: 8663997
    Abstract: The invention relates to a gas detection system (1) for detecting gases, vapors and biological pathogens, having at least one receptor (4) arranged on a line (5) connecting the ambient air (7) to an air storage unit, wherein the gas detection system (1) is designed as a “breathing” system containing clean CO2-carrying and moisture-saturated air in the air storage unit (2), wherein the operating temperature of the gas detection system (1) is the room temperature. Additionally, a method is proposed for detecting gases, vapors and biological pathogens using the inventive gas detection system. This avoids the shortcomings of the known solutions of the prior art, and an improved and more cost-effective solution for detecting trace gases is made available.
    Type: Grant
    Filed: May 13, 2009
    Date of Patent: March 4, 2014
    Assignee: EADS Deutschland GmbH
    Inventors: Gerhard Müller, Andreas Helwig
  • Patent number: 8663998
    Abstract: According to embodiments of the present application, a color changeable dye can comprise a redox indicator, a reduction reaction initiator, an electron donor, an oxygen scavenger, an indicator barrier agent, a thickening agent and an agent to facilitate mixing. The color changeable dye is a first color in the presence of oxygen, capable of changing to a second color upon reduction in a substantially oxygen free environment, and capable of changing back to the first color after exposure to oxygen for a period of time corresponding to the intended use time of a disposable or limited use product. Methods of making and using the color changeable dye and apparatuses incorporating such dye are also disclosed.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: March 4, 2014
    Inventors: Gregory Lee Heacock, Dion Arledge Rivera
  • Patent number: 8663999
    Abstract: The present disclosure provides nuclear magnetic resonance (NMR) methods for characterizing mixtures of N-linked glycans. Without limitation, methods of the present disclosure may be useful in characterizing monosaccharide composition, branching, fucosylation, sulfation, phosphorylation, sialylation linkages, presence of impurities and/or efficiency of a labeling procedure (e.g., labeling with a fluorophore such as 2-AB). In certain embodiments, the methods can be used quantitatively. In certain embodiments, the methods can be combined with enzymatic digestion to further characterize glycan mixtures.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: March 4, 2014
    Assignee: Momenta Pharmaceuticals, Inc.
    Inventors: Ian Christopher Parsons, Jonathan Lansing, Daniela Becatti, Scott Bailey, Carlos J. Bosques
  • Patent number: 8664000
    Abstract: Electrospray ionization techniques are used to generate reagents that ionize analytes for mass spectrometric analysis by charge transfer. Such techniques may be performed under ambient conditions. Suitable precursors for such reagents include ionizable nonpolar solvents, such as toluene or xylenes, polar solvents, such as water or alchohols, inert gases, such as helium or nitrogen, or combinations thereof. Environmental conditions in the ionization chamber of the mass spectrograph can be manipulated to generate a selected ion of an analyte in preference to other ions.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: March 4, 2014
    Assignee: The Trustees of the Stevens Institute of Technology
    Inventors: Zhihua Yang, Athula Buddhagosha Attygalle
  • Patent number: 8664001
    Abstract: An immunochemical filter device which has filter material attached to a support member (such as a cap) which is, in turn, attachable to a sample collection vessel. The filter material includes a labeled binding reagent that is released from the filter material into solution by migration of a liquid sample solution through the filter material. The mixture of the sample solution and the labeled specific binding reagent is transferred to an analyzer device for performance of a method for determining the presence or absence of an analyte in a sample solution.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: March 4, 2014
    Assignee: Ani Biotech Oy
    Inventors: Aimo Niskanen, Mika Saramaki
  • Patent number: 8664002
    Abstract: A method of collecting target regions from a target object is described. The method in one embodiment comprises mounting a negatively-charged membrane on a first side of a substrate, mounting a target object on the membrane, positioning a collection material adjacent to the target object, and passing a laser beam from a second side of the substrate, through the substrate, the membrane, and the target object, to dissect target regions from the prepared tissue section, whereby the dissected target regions adhere to the collection material. In another embodiment, the present invention is a system for collecting target regions from a target object. In one embodiment, the system comprises a substrate having a first side and a second side, a negatively-charged membrane adhered to the first side of the substrate, and a collection material mountable adjacent to the membrane.
    Type: Grant
    Filed: May 19, 2006
    Date of Patent: March 4, 2014
    Assignee: Motic China Group Co., Ltd.
    Inventor: Richard Yeung
  • Patent number: 8664003
    Abstract: A chip useful for treating cells and the like which has a mechanism and a structure wherein the size of a hole pattern is arbitrarily changed so that cells can easily move in and get out from the hole in scattering or collecting cells but can hardly get out from the hole during washing or antigen-stimulation. The chip comprises a crosslinked product of a temperature-responsive polymer as a constituting member and being provided with a film having a hole pattern on the surface of a baseboard. A method of producing the chip comprises applying a composition containing a crosslinkable temperature-responsive polymer on the surface of a baseboard to thereby form a coating film, crosslinking the coating film to thereby form the crosslinked product as described above and then forming a hole pattern on the coating film of the crosslinked product.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: March 4, 2014
    Assignees: Toyama Prefecture, Nissan Chemical Industries, Ltd.
    Inventors: Eiichi Tamiya, Yoshiyuki Yokoyama, Satoshi Fujiki, Katsumi Tanino, Atsushi Muraguchi, Hiroyuki Kishi, Yoshiharu Tokimitsu, Shohei Yamamura
  • Patent number: 8664004
    Abstract: The present invention relates to the monitoring of contaminant concentrations in manufacturing processes that employ fluid purification devices. The invention provides a sensitive method for analyzing contaminant concentrations in a process fluid stream using purification material to adsorb contaminants contained therein over an entire process.
    Type: Grant
    Filed: February 20, 2004
    Date of Patent: March 4, 2014
    Assignee: Entegris, Inc.
    Inventors: Jeffrey J. Spiegelman, Daniel Alvarez, Jr., Allan Tram
  • Patent number: 8664005
    Abstract: A method of introducing solution into the wells of a multiwell plate comprised of a substrate having multiple wells on at least one principal surface thereof. The wells are imparted dimensions, shapes, and surface configurations such that when said multiwell plate is positioned in stationary fashion with the openings of said wells facing upward, said solution does not enter said wells even when the openings of said wells are covered by said solution, and the solution is positioned on said principal surface of said multiwell plate having wells and a centrifugal force oriented from the well opening toward the bottom is applied to introduce said solution into said wells. Provided is a method for conveniently filling vessels (wells) with a solution such as a reaction solution, even when the vessels (wells) number in excess of 1,000, and even when the dimension, shape, and surface configuration of the vessels (wells) do not permit fluid to flow into the vessels (wells).
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: March 4, 2014
    Assignee: National University Corporation Saitama University
    Inventors: Koichi Nishigaki, Takahiro Tayama, Yasunorl Kinoshita, Hidekazu Uchida
  • Patent number: 8664006
    Abstract: A nozzle system for use in a flow cytometer for analyzing particles in a fluid stream and a method of orienting particles in a flow cytometer. The nozzle system may include a nozzle having a longitudinal axis, an interior surface defining a fluid flow path for orienting particles in the nozzle, and a downstream orifice through which a fluid stream exits. The nozzle system may also include a conduit positioned to introduce a core stream containing particles at a location offset from the longitudinal axis and a baffle downstream of the conduit to deflect the fluid stream. The method may include the steps of causing a sheath fluid to flow through the nozzle, introducing a core fluid stream into the sheath fluid at a location offset to the longitudinal axis of the nozzle, and deflecting the core fluid stream with a baffle.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: March 4, 2014
    Assignee: Inguran, LLC
    Inventors: Gary Durack, Jeffrey D. Wallace, Gary P. Vandre, Lon A. Westfall, Jeremy T. Hatcher, Niraj V. Nayak
  • Patent number: 8664007
    Abstract: The invention concerns a method for determining antigen-specific antibodies of a particular immunoglobulin class in a sample by means of an immunoassay in an array format in which various binding partners Bnx are bound on different discrete areas on a support where Bnx in each case contain the various antigens that are able to specifically bind to the antibodies to be detected, by incubating the support with the sample and a binding partner B2 which carries a label and subsequently detecting the label on the respective discrete areas wherein B2 specifically binds antibodies of a certain immunoglobulin class that have been bound in an antigen-specific manner.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: March 4, 2014
    Assignee: Roche Diagnostics Operations, Inc.
    Inventors: Ursula Klause, Helmut Lenz, Christine Markert-Hahn
  • Patent number: 8664008
    Abstract: An embodiment of the invention relates to a device for detecting an analyte in a sample. The device comprises a fluidic network and an integrated circuitry component. The fluidic network comprises a sample zone, a cleaning zone and a detection zone. The fluidic network contains a magnetic particle and/or a signal particle. A sample containing an analyte is introduced, and the analyte interacts with the magnetic particle and/or the signal particle through affinity agents. A microcoil array or a mechanically movable permanent magnet is functionally coupled to the fluidic network, which are activatable to generate a magnetic field within a portion of the fluidic network, and move the magnetic particle from the sample zone to the detection zone. A detection element is present which detects optical or electrical signals from the signal particle, thus indicating the presence of the analyte.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: March 4, 2014
    Assignee: Intel Corporation
    Inventors: David J. Liu, Kai Wu, Xing Su
  • Patent number: 8664009
    Abstract: The invention provides methods and compositions for labeling dithiol-containing analytes.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: March 4, 2014
    Assignee: SRI International
    Inventors: Laura Ellen Downs Beaulieu, Mary J. Tanga
  • Patent number: 8664010
    Abstract: An MTJ element is formed in a wiring layer located in a lower tier and yet application of heat to the MTJ element is suppressed. A first insulating layer is formed over a substrate. Subsequently, the MTJ element is formed over the first insulating layer. After that a first wiring is formed over the MTJ element. Thereafter, a second insulating layer is formed over the first wiring. Then a second wiring is formed in the superficial layer of the second insulating layer. The second wiring is heat treated by photoirradiation. A shield conductor is formed at the step of forming the second wiring.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: March 4, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Yoshihisa Matsubara
  • Patent number: 8664011
    Abstract: An upper electrode of a ferroelectric capacitor has a first layer formed of a first oxide expressed by a chemical formula AOx1 (A: metal, O: oxygen) using a stoichiometric composition parameter x1, and expressed by a chemical formula AOx2 using a actual composition parameter x2, and a second layer formed of a second oxide, formed on the first layer, expressed by a chemical formula BOy1 (B: metal) using a stoichiometric composition parameter y1 and expressed by a chemical formula BOy2 using a actual composition parameter y2, which includes at least one of stone-wall crystal and column crystal.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: March 4, 2014
    Assignee: Fujitsu Limited
    Inventor: Wensheng Wang
  • Patent number: 8664012
    Abstract: A method of forming a semiconductor device. A substrate having first and second materials is provided, wherein the second material is occluded by the first material. The substrate is etched using a first non-plasma etch process that etches the first material at a higher rate relative to a rate of etching the second material. The first non-plasma etch process exposes the second material that is overlying at least a portion of the first material. The second material is then etched using a plasma containing a reactive gas, which exposes the at least a portion of the first material. The first material including the at least a portion of the first material that was exposed by etching the second material are etched using a second non-plasma etch process.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: March 4, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Richard H. Gaylord, Blaze J. Messer, Kaushik A. Kumar
  • Patent number: 8664013
    Abstract: In a continuous processing system, a controller of a heat treatment apparatus calculates a weight of each layer from input target film thicknesses of a phosphorous-doped polysilicon film (D-poly film) and an amorphous silicon film (a-Si film), and calculates activation energy of stacked films based on the calculated weight and activation energy. The controller prepares a stacked film model based on the calculated activation energy and a relationship of a temperature of each zone and film thicknesses of the D-poly film and the a-Si film, and calculates an optimum temperature of each zone by using the prepared stacked film model. The controller controls power controllers of heaters to set a temperature in a reaction tube to be the calculated temperature of each zone and forms stacked films on a semiconductor wafer by controlling a pressure adjusting unit, flow rate adjusting units, etc.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 4, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Yuichi Takenaga, Yukio Tojo
  • Patent number: 8664014
    Abstract: Electrical testing of metal oxide semiconductor (MOS) high-k capacitor structures is used to evaluate photoresist strip or cleaning chemicals using a combinatorial workflow. The electrical testing can be able to identify the damages on the high-k dielectrics, permitting a selection of photoresist strip chemicals to optimize the process conditions in the fabrication of semiconductor devices. The high productivity combinatorial technique can provide a compatibility evaluation of photoresist strip chemicals with high-k devices.
    Type: Grant
    Filed: November 17, 2011
    Date of Patent: March 4, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Bei Li, Sean Barstow, Anh Duong, Zhendong Hong, Ashley Lacey
  • Patent number: 8664015
    Abstract: A method of manufacturing a solar cell including providing a semiconductor substrate having a first conductivity type; performing a first deposition process that includes forming a first doping material layer having a second conductivity type different from the first conductivity type; performing a drive-in process that includes heating the substrate having the first doping material layer thereon; performing a second deposition process after performing the drive-in process and including forming a second doping material layer on the first doping material layer, wherein the second doping material layer has the second conductivity type; locally heating portions of the substrate, the first doping material layer, and the second doping material layer with a laser to form a contact layer at a first surface of the substrate; and forming a first electrode on the contact layer and a second electrode on a second surface of the substrate opposite to the first surface.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: March 4, 2014
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Sang-Jin Park, Min-Chul Song, Sung-Chan Park, Dong-Seop Kim, Won-Gyun Kim, Sang-Won Seo
  • Patent number: 8664016
    Abstract: Provided are an organic light emitting diode and a method of manufacturing the same. The organic light emitting diode adjusts an optical resonance thickness and prevents spectrum distortions without use of an auxiliary layer. The organic light emitting diode includes a first electrode that is optically reflective; a second electrode that is optically transmissible and faces the first electrode; an organic emission layer interposed between the first electrode and the second electrode, the organic emission layer including: a first emission layer including a mixed layer that contains a host material and a dopant material, and a second emission layer comprising only the host material; and a carrier injection transport layer interposed between the organic emission layer and the first electrode or between the organic emission layer and the second electrode.
    Type: Grant
    Filed: January 13, 2010
    Date of Patent: March 4, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Min-Seung Chun, Mi-Kyung Kim, Dong-Heon Kim, Jung-Ha Son, Jae-Hyun Kwak, Kyung-Hoon Choi, Mie-Hwan Park, Young-Ho Park, Young-Suck Choi, Tae-Shick Kim, Choon-Woo Im, Kwan-Hee Lee
  • Patent number: 8664017
    Abstract: Provided is a method of manufacturing an organic light emitting device capable of suppressing a patterning defect caused by a residue of a release layer, the method including: a first organic compound layer formation step; a first protective layer formation step; a second protective layer formation step; a second protective layer processing step; a first protective layer processing step; a first organic compound layer processing step; a second organic compound layer formation step; and a lift-off step in which the pattern of the second protective layer obtained in the second protective layer processing step is formed also in a second region.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: March 4, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masahiro Fushimi, Junya Tamaki, Manabu Otsuka, Takuro Yamazaki
  • Patent number: 8664018
    Abstract: The disclosure provides a manufacturing method for an LED package. A first luminescent conversion layer comprising one first luminescent conversion element is located on an LED chip, wherein the first luminescent conversion element is precipitated via centrifugation around the LED chip without sheltering the LED chip. Thereafter, a second luminescent conversion layer is located on the first luminescent conversion layer. The second luminescent layer has a second luminescent conversion element which has an excited efficiency lower that that of the first luminescent conversion element.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: March 4, 2014
    Assignee: Advanced Optoelectronic Technology, Inc.
    Inventors: Hsin-Chiang Lin, Wen-Liang Tseng, Chieh-Ling Chang
  • Patent number: 8664019
    Abstract: A vertical group III-nitride light emitting device and a manufacturing method thereof are provided. The light emitting device comprises: a conductive substrate; a p-type clad layer stacked on the conductive substrate; an active layer stacked on the p-type clad layer; an n-doped AlxGayIn1-x-yN layer stacked on the active layer; an undoped GaN layer stacked on the n-doped layer; and an n-electrode formed on the undoped GaN layer. The undoped GaN layer has a rough pattern formed on a top surface thereof.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: March 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae Hoon Lee, Yong Chun Kim, Hyung Ky Back, Moon Heon Kong, Dong Woo Kim
  • Patent number: 8664020
    Abstract: Disclosed is a semiconductor light emitting device, and a method of manufacturing the same. The semiconductor light emitting device includes a first conductivity type semiconductor layer, an active layer disposed on the top of the first conductivity type semiconductor layer, and a second conductivity type semiconductor layer disposed on the top of the active layer and comprising light extraction patterns in the top thereof, the light extraction patterns each having a columnar portion and a hemispherical top portion.
    Type: Grant
    Filed: November 18, 2009
    Date of Patent: March 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae Sung Jang, Su Yeol Lee, Jong Gun Woo
  • Patent number: 8664021
    Abstract: An organic light-emitting display device includes a plurality of first and second electrodes which are spaced apart from each other on a substrate, a plurality of light-emitting layers between the first and second electrodes, a flexible thin encapsulation film on the second electrodes, and a color filter on the flexible thin encapsulation film.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: March 4, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sun-kook Kim, In-seo Kee, Sang-yoon Lee
  • Patent number: 8664022
    Abstract: A submount for a light emitting diode and a method for fabricating the same are provided. The method includes the following steps: (a) providing a silicon substrate; (b) forming a mask layer on the silicon substrate to expose a part of the silicon substrate; (c) forming a first silicon oxide layer in the part of the silicon substrate which is exposed; and (d) removing the mask layer and the first silicon oxide layer, so as to form a recess in the silicon substrate.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: March 4, 2014
    Assignee: Episil Technologies Inc.
    Inventors: Le-Sheng Yeh, Cheng-I Chien
  • Patent number: 8664023
    Abstract: A vapor deposition method of the present invention includes the steps of (i) preparing a mask unit including a shadow mask (81) and a vapor deposition source (85) fixed in position relative to each other, (ii) while moving at least one of the mask unit and the film formation substrate (200) relative to the other, depositing a vapor deposition flow, emitted from the vapor deposition source (85), onto a vapor deposition region (210), and (iii) adjusting the position of a second shutter (111) so that the second shutter (111) blocks a vapor deposition flow traveling toward the vapor deposition unnecessary region (210).
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: March 4, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tohru Sonoda, Shinichi Kawato, Satoshi Inoue, Satoshi Hashimoto
  • Patent number: 8664024
    Abstract: A pixel structure and a fabrication method thereof are provided. A scan line, a gate, an oxide conductor layer, a metal conductor layer, an oxide semiconductor layer, and an insulation layer between the gate and the metal conductor layer are formed on a substrate. The oxide conductor layer includes a pixel electrode and a first auxiliary pattern partially overlapped with where the gate is. The first auxiliary pattern includes a first metal contact portion and a first semiconductor contact portion. The metal conductor layer includes a data line, a source connected to the data line, and a drain separated from the source. The drain contacts the first metal contact portion, exposes the first semiconductor contact portion between the source and the drain, and is electrically connected to the pixel electrode. The oxide semiconductor layer is connected between the source and the drain and contacts the first semiconductor contact portion.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: March 4, 2014
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventor: Hsi-Ming Chang
  • Patent number: 8664025
    Abstract: The width of scribe lines may be reduced in semiconductor devices by applying a process technique in which trenches may be formed first from the rear side on the basis of a required width of the corresponding trenches, while subsequently it may be cut into the substrate from the front side on the basis of a reduced thickness of the corresponding saw blades, thereby also enabling a reduction of the scribe line width. Furthermore, contamination of the front side, i.e., of the metallization system, may be reduced, for instance, by performing an optional intermediate cleaning process.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: March 4, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Daniel Richter, Frank Kuechenmeister
  • Patent number: 8664026
    Abstract: A method for fabricating a semiconductor lighting chip includes steps of providing a substrate with an epitaxial layer thereon. The epitaxial layer comprises a first semiconductor layer, an active layer and a second semiconductor layer successively grown on the substrate. The epitaxial layer has dislocation defects traversing the first semiconductor layer, the active layer and the second semiconductor layer. The epitaxial layer is then subjected to an etching process which remove parts of the second semiconductor layer and the active layer along the dislocation defects to form recesses recessing from the second semiconductor layer to the active layer. Thereafter a first electrode and a second electrode are formed on the first semiconductor layer and the second semiconductor layer, respectively.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: March 4, 2014
    Assignee: Advanced Optoelectronic Technology, Inc.
    Inventors: Po-Min Tu, Shih-Cheng Huang
  • Patent number: 8664027
    Abstract: A method of LED manufacturing is disclosed. A coating is applied to a mesa. This coating may have different thicknesses on the sidewalls of the mesa compared to the top of the mesa. Ion implantation into the mesa will form implanted regions in the sidewalls in one embodiment. These implanted regions may be used for LED isolation or passivation.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: March 4, 2014
    Assignee: Varian Semiconductor Associates, Inc.
    Inventors: San Yu, Atul Gupta
  • Patent number: 8664028
    Abstract: (a) On a growth substrate, a void-containing layer that is made of a group III nitride compound semiconductor and contains voids is formed. (b) On the void-containing layer, an n-type layer that is made of an n-type group III nitride compound semiconductor and serves to close the voids is formed. (c) On the n-type layer, an active layer made of a group III nitride compound semiconductor is formed. (d) On the active layer, a p-type layer made of a p-type group III nitride compound semiconductor is formed. (e) A support substrate is bonded above the p-type layer. (f) The growth substrate is peeled off at the boundary where the voids are produced. In the above step (a) or (b), the supply of at least part of the materials that form the layer is decreased, while heating, before the voids are closed.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: March 4, 2014
    Assignee: Stanley Electric Co., Ltd.
    Inventors: Yasuyuki Shibata, Ji-Hao Liang
  • Patent number: 8664029
    Abstract: A process for fabricating a capacitance type tri-axial accelerometer comprises of preparing a wafer having an upper layer, an intermediate layer and a lower layer, etching the lower layer of the wafer to form an isolated proof mass having a core and four segments extending from the core, etching the upper layer of the wafer to form a suspension and four separating plates, etching away a portion of the intermediate layer located between the four segments of the proof mass and the plates of the upper layer, and disposing an electrical conducting means to pass through the intermediate layer from the suspension to the core of the proof mass.
    Type: Grant
    Filed: October 19, 2009
    Date of Patent: March 4, 2014
    Assignee: Domintech Co., Ltd.
    Inventor: Ming-Ching Wu
  • Patent number: 8664030
    Abstract: An interconnected arrangement of photovoltaic cells is achieved using laminating current collector electrodes. The electrodes comprise a pattern of conductive material extending over a first surface of sheetlike substrate material. The first surface comprises material having adhesive affinity for a selected conductive surface. Application of the electrode to the selected conductive surface brings the first surface of the sheetlike substrate into adhesive contact with the conductive surface and simultaneously brings the conductive surface into firm contact with the conductive material extending over first surface of the sheetlike substrate. Use of the laminating current collector electrodes allows facile and continuous production of expansive area interconnected photovoltaic arrays.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: March 4, 2014
    Inventors: Daniel Luch, Daniel Randolph Luch
  • Patent number: 8664031
    Abstract: A semiconductor device manufacturing method including a process of forming a silicon oxide film by thermally oxidizing silicon in the atmosphere of oxygen gas or in the atmosphere of mixed gas of oxygen and hydrogen at a temperature of 800° C. or more in the state in which at least the silicon surface serving as a light-receiving portion of a photodiode is exposed, and a process of depositing a silicon nitride film on the silicon oxide film. At least the silicon oxide film and the silicon nitride film are finally left on the surface of the photodiode as an antireflection film.
    Type: Grant
    Filed: November 17, 2008
    Date of Patent: March 4, 2014
    Assignee: Sony Corporation
    Inventor: Tomotaka Fujisawa
  • Patent number: 8664032
    Abstract: It is an object to provide a CCD solid-state image sensor, in which an area of a read channel is reduced and a rate of a surface area of a light receiving portion (photodiode) to an area of one pixel is increased.
    Type: Grant
    Filed: May 5, 2011
    Date of Patent: March 4, 2014
    Assignee: Unisantis Electronics Singapore Pte Ltd.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 8664033
    Abstract: A gallium-containing alloy is formed on the light-receiving surface of a CIGS absorber layer, and, in conjunction with a subsequent selenization or anneal process, is converted to a gallium-rich region at the light-receiving surface of the CIGS absorber layer. A second gallium-rich region is formed at the back contact surface of the CIGS absorber layer during selenization, so that the CIGS absorber layer has a double-graded gallium concentration that increases toward the light-receiving surface and toward the back contact surface of the CIGS absorber layer. The double-graded gallium concentration advantageously produces a double-graded bandgap profile for the CIGS absorber layer.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: March 4, 2014
    Assignee: Intermolecular, Inc.
    Inventor: Haifan Liang
  • Patent number: 8664034
    Abstract: A method for manufacturing a solar cell (100) includes the steps of: a step of cleaning an exposed region (R2) on a rear surface of an n-type crystalline silicon substrate (10n), wherein the step is carried out subsequent to a step of patterning an i-type amorphous semiconductor layer (11i) and a p-type amorphous semiconductor layer (11p) and prior to a step of forming an i-type amorphous semiconductor layer (12i).
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: March 4, 2014
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tsuyoshi Takahama, Masayoshi Ono, Hiroyuki Mori, Youhei Murakami
  • Patent number: 8664035
    Abstract: An object is to reduce variations in programming behavior from memory element to memory element. Furthermore, an object is to obtain a semiconductor device with excellent writing characteristics and in which the memory element is mounted. The memory element includes a first conductive layer, a metal oxide layer, a semiconductor layer, an organic compound layer, and a second conductive layer, where the metal oxide layer, the semiconductor layer, and the organic compound layer are interposed between the first conductive layer and the second conductive layer; the metal oxide layer is provided in contact with the first conductive layer; and the semiconductor layer is provided in contact with the metal oxide layer. By use of this kind of structure, variations in programming behavior from memory element to memory element are reduced.
    Type: Grant
    Filed: July 13, 2007
    Date of Patent: March 4, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Mikio Yukawa, Nozomu Sugisawa
  • Patent number: 8664036
    Abstract: An oxide semiconductor layer with excellent crystallinity is formed to enable manufacture of transistors with excellent electrical characteristics for practical application of a large display device, a high-performance semiconductor device, etc. By first heat treatment, a first oxide semiconductor layer is crystallized. A second oxide semiconductor layer is formed over the first oxide semiconductor layer. By second heat treatment, an oxide semiconductor layer including a crystal region having the c-axis oriented substantially perpendicular to a surface is efficiently formed and oxygen vacancies are efficiently filled. An oxide insulating layer is formed over and in contact with the oxide semiconductor layer. By third heat treatment, oxygen is supplied again to the oxide semiconductor layer. A nitride insulating layer containing hydrogen is formed over the oxide insulating layer.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: March 4, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hotaka Maruyama, Yoshiaki Oikawa, Katsuaki Tochibayashi
  • Patent number: 8664037
    Abstract: Disclosed are a method for forming a metal oxide pattern and a method of manufacturing a thin film transistor using the patterned metal oxide. The method for forming a metal oxide pattern includes: preparing an ink composition including at least one metal oxide precursor or metal oxide nanoparticle, and a solvent; ejecting the ink composition on a substrate to form a pattern on the substrate; and photosintering the formed pattern. Herein, the metal oxide precursor is ionic.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: March 4, 2014
    Assignee: Korea Institute of Science and Technology
    Inventors: Yong-Won Song, Jae-Min Hong, Jung Ah Lim, Hak-Sung Kim, Seong-Ji Kwon
  • Patent number: 8664038
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a package paddle and a terminal adjacent to the package paddle; mounting a stack paddle over the package paddle with the stack paddle at a non-center offset with the package paddle; mounting a stack integrated circuit over the stack paddle; and encapsulating the stack integrated circuit and the stack paddle.
    Type: Grant
    Filed: December 4, 2008
    Date of Patent: March 4, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Arnel Senosa Trasporto, Lionel Chien Hui Tay, Jose Alvin Caparas
  • Patent number: 8664039
    Abstract: Methods and apparatus for alignment in a flip chip bonding. A method includes attaching an integrated circuit having connector terminals to a bonding arm, the bonding arm having a chuck for attaching the integrated circuit at the backside surface, the bonding arm having a plurality of CCD imagers mounted thereon; receiving a substrate having pads corresponding to the connector terminals; using the bonding arm, positioning the integrated circuit proximal to the substrate; aligning the integrated circuit connector terminals with the pads on the substrate using the CCD imagers on the bonding arm; positioning the connector terminals in contact with the pads on the substrate; and performing a solder reflow to attach the integrated circuit to the substrate. An apparatus includes a bonding arm with a chuck for carrying a component and CCD imagers mounted on the arm for alignment.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: March 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Chung Sung, Yu-Chih Liu, Wei-Ting Lin, Chien-Hsiun Lee