Abstract: A method includes forming a first buildup dielectric layer on a wafer. The wafer includes electronic components delineated from one another by singulation streets. A singulation street exposure light trap layer is formed on the singulation streets. A second buildup dielectric layer is applied and patterned by being selectively exposed to an exposure light. The singulation street exposure light trap layer traps and diffuses the exposure light thus preventing the exposure light from being reflected to the portion of the second buildup dielectric layer above the singulation streets. In this manner, complete removal of the second buildup dielectric layer above the singulation streets is insured.

Abstract: A method for removing a metallic nanotube, which is formed on a substrate in a first direction, includes forming a plurality of conductors in a second direction crossing the first direction, electrically contacting the plurality of conductors with metallic nanotube, respectively, forming at least two voltage-applying electrodes on the conductors, each of which electrically contacting at least one of the conductors, and applying voltages to at least some of the conductors through the voltage-applying electrodes, respectively. Among the conductors to which the voltages are respectively applied, every two adjacent conductors have an electrical potential difference created therebetween, so as to burn out the metallic nanotube.

Abstract: A silicon wafer after being subjected to mirror polishing but before being subjected to form an epitaxial layer thereon is subjected to an ozone gas treatment that oxidizes a surface of the silicon wafer by use of ozone gas, a hydrofluoric acid gas treatment that dissolves and removes the oxidized surface of the silicon wafer by use of hydrofluoric acid gas, and a washing treatment that removes foreign substances remaining on the surface of the silicon wafer, whereby PIDs (Polishing Induced Defects) generated by the mirror polishing are forcedly oxidized, dissolved and removed. By performing epitaxial treatment thereafter, PID-induced convex defects can be prevented from generating on the surface of the epitaxial wafer.

Abstract: Disclosed herein are various methods of forming a silicon seed layer and layers of silicon and silicon-containing material therefrom. In one example, the method includes forming a layer of silicon dioxide above a structure, converting at least a portion of the layer of silicon dioxide into a silicon-salt layer and converting at least a portion of the silicon-salt layer to a layer of silicon.

Abstract: The present invention relates to the growing of nitride semiconductors, applicable for a multitude of semiconductor devices such as diodes, LEDs and transistors. According to the method of the invention nitride semiconductor nanowires are grown utilizing a CVD based selective area growth technique. A nitrogen source and a metal-organic source are present during the nanowire growth step and at least the nitrogen source flow rate is continuous during the nanowire growth step. The V/III-ratio utilized in the inventive method is significantly lower than the V/III-ratios commonly associated with the growth of nitride based semiconductor.

Abstract: Direct growth of black Ge on low-temperature substrates, including plastics and rubber is reported. The material is based on highly dense, crystalline/amorphous core/shell Ge nanoneedle arrays with ultrasharp tips (˜4 nm) enabled by the Ni catalyzed vapor-solid-solid growth process. Ge nanoneedle arrays exhibit remarkable optical properties. Specifically, minimal optical reflectance (<1%) is observed, even for high angles of incidence (˜75°) and for relatively short nanoneedle lengths (˜1 ?m). Furthermore, the material exhibits high optical absorption efficiency with an effective band gap of ˜1 eV. The reported black Ge can have important practical implications for efficient photovoltaic and photodetector applications on nonconventional substrates.

Abstract: The invention provides a method for producing a flexible barrier sheet (200) comprising a barrier layer (103) and metallic elements (104), said method comprising: a) providing a metallic layer (102) applied on a polymeric support layer (101), the metallic layer having a first surface (105) facing the polymeric support layer and a second surface (106) facing away from said polymeric support layer; b) providing metallic elements on the second surface of the metallic layer; c) providing a barrier layer covering said second surface of the metallic layer and said metallic elements, the barrier layer having a first surface facing the metallic layer and a second surface facing away from the metallic layer; d) releasing the polymeric support layer from the metallic layer; and e) removing the metallic layer from the metallic elements and the barrier layer.

Abstract: An object is to provide a technique by which a semiconductor device including a high-performance and high-reliable transistor is manufactured. A protective conductive film which protects an oxide semiconductor layer when a wiring layer is formed from a conductive layer is formed between the oxide semiconductor layer and the conductive layer, and an etching process having two steps is performed. In a first etching step, an etching is performed under conditions that the protective conductive film is less etched than the conductive layer and the etching selectivity of the conductive layer to the protective conductive film is high. In a second etching step, etching is performed under conditions that the protective conductive film is more easily etched than the oxide semiconductor layer and the etching selectivity of the protective conductive film to the oxide semiconductor layer is high.

Abstract: A plasma processing apparatus includes a process chamber, a platen for supporting a workpiece, a source configured to generate a plasma in the process chamber, and an insulating modifier. The insulating modifier has a gap, and a gap plane, where the gap plane is defined by portions of the insulating modifier closest to the sheath and proximate the gap. A gap angle is defined as the angle between the gap plane and a plane defined by the front surface of the workpiece. Additionally, a method of having ions strike a workpiece is disclosed, where the range of incident angles of the ions striking the workpiece includes a center angle and an angular distribution, and where the use of the insulating modifier creates a center angle that is not perpendicular to the workpiece.

Abstract: The present invention discloses a MEMS device with particles blocking function, and a method for making the MEMS device. The MEMS device comprises: a substrate on which is formed a MEMS device region; and a particles blocking layer deposited on the substrate.

Abstract: A first facet of each of a plurality of pyramids on a surface of a workpiece is doped to a first dose while a second facet and a third facet of each of the plurality of pyramids is simultaneously doped to a second dose different than the first dose. The first facets may enable low resistance contacts and the second and third facets may enable higher current generation and an improved blue response. Ion implantation may be used to perform the doping.

Abstract: A first insulating interlayer is formed on a substrate including first and second regions. The first insulating interlayer has top surface, a height of which is greater in the first region than in the second region. A first planarization stop layer and a second insulating interlayer are formed. The second insulating interlayer is planarized until the first planarization stop layer is exposed. The first planarization stop layer and the first and second insulating interlayers in the second region are removed to expose the substrate. A lower mold structure including first insulation layer patterns, first sacrificial layer patterns and a second planarization stop layer pattern is formed. The first insulation layer patterns and the first sacrificial layer patterns are alternately and repeatedly formed on the substrate, and a second planarization stop layer pattern is formed on the first insulation layer pattern.

Abstract: A semiconducting device with a dual sidewall spacer and method of forming are provided. The method includes: depositing a first spacer layer over a patterned structure, the first spacer layer having a seam propagating through a thickness of the first spacer layer near an interface region of a surface of the substrate and a sidewall of the patterned structure, etching the first spacer layer to form a residual spacer at the interface region, where the residual spacer coats less than the entirety of the sidewall of the patterned structure, depositing a second spacer layer on the residual spacer and on the sidewall of the patterned structure not coated by the residual spacer, the second spacer layer being seam-free on the seam of the residual spacer, and etching the second spacer layer to form a second spacer coating the residual spacer and coating the sidewall of the patterned structure not coated by the residual spacer.

Abstract: Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein a reduced threshold voltage (Vt) may be achieved in HK/MG transistor elements that are manufactured based on replacement gate electrode integrations. One illustrative method disclosed herein includes forming a first metal gate electrode material layer above a gate dielectric material layer having a dielectric constant of approximately 10 or greater. The method further includes exposing the first metal gate electrode material layer to an oxygen diffusion process, forming a second metal gate electrode material layer above the first metal gate electrode material layer, and adjusting an oxygen concentration gradient and a nitrogen concentration gradient in at least the first metal gate electrode material layer and the gate dielectric material layer.

Abstract: A method of producing a microelectronic device with transistors wherein a strain layer is formed on a series of transistors and the strain exerted on at least one given transistor of said series is released by removing a sacrificial layer situated between said given transistor and said strain layer.

Abstract: A method for processing a wafer with a wafer bevel that surrounds a central region is provided. The wafer is placed in a bevel plasma processing chamber. A protective layer is deposited on the wafer bevel without depositing the protective layer over the central region. The wafer is removed from the bevel plasma processing chamber. The wafer is further processed.

Abstract: A method of manufacturing a semiconductor device, wherein a first substrate where first electrode pads are formed and a second substrate where second electrode pads are formed are stacked and the first electrode pads and the corresponding second electrode pads are electrically connected thereby forming the semiconductor device is disclosed. The method includes steps of performing a first hydrophilic treatment with respect to the first electrode pads; supplying liquid to a surface where the first electrode pads are formed in the first substrate; and placing the second substrate on the first substrate to which the liquid is supplied so that the surface where the first electrode pads are formed opposes a surface where the second electrode pads are formed, thereby aligning the first electrode pads and the second electrode pads by the liquid that gathers in the first electrode pads that have been subject to the first hydrophilic treatment.

Abstract: Disclosed are an application method, device and program which enable the constant retention of a fillet shape, without altering the shape due to the speed differences associated with changes in the direction of the nozzle or differences in the degree of penetration when bumps are arranged non-uniformly. In a liquid material application method a desired application pattern is created, liquid material is discharged from a nozzle whilst the nozzle and a workpiece are moved relative to one another, and the gap between a substrate and the workpiece, the workpiece being placed above the substrate by means of at least three bumps, is filled up with liquid material by capillary action. If bumps are arranged non-uniformly, the supply quantity per unit area of the application pattern is set so that a greater quantity is supplied to application areas next to areas where the integration density of bumps is high, than is supplied to application areas next to areas where the integration density of bumps is low.

Abstract: A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.

Abstract: A method of forming a carbon-rich silicon carbide-like dielectric film having a carbon concentration of greater than, or equal to, about 30 atomic % C and a dielectric constant of less than, or equal to, about 4.5 is provided. The dielectric film may optionally include nitrogen. When nitrogen is present, the carbon-rich silicon carbide-like dielectric film has a concentration nitrogen that is less than, or equal, to about 5 atomic % nitrogen.

Abstract: A method of forming a semiconductor device includes, but is not limited to, the following processes. A first interlayer insulating film is formed. A hole is formed in the first interlayer insulating film. A second interlayer insulating film is formed, which buries the hole and covers the first interlayer insulating film. An interconnect groove is formed by selectively etching the second interlayer insulating film to leave the second interlayer insulating film in the hole. The second interlayer insulating film in the hole is removed.

Abstract: There is provided a method of manufacturing a semiconductor device. In the method, a gate insulation layer including a high-k dielectric material is formed on a substrate. An etch stop layer is formed on the gate insulation layer. A metal layer is formed on the etch stop layer. A hard mask including amorphous silicon is formed on the metal layer. The metal layer is patterned using the hard mask as an etching mask to form a metal layer pattern.

Abstract: Semiconductor devices comprise at least one integrated circuit layer, at least one conductive trace and an insulative material adjacent at least a portion of the at least one conductive trace. At least one interconnect structure extends through a portion of the at least one conductive trace and a portion of the insulative material, the at least one interconnect structure comprising a transverse cross-sectional dimension through the at least one conductive trace which differs from a transverse cross-sectional dimension through the insulative material. Methods of forming semiconductor devices comprising at least one interconnect structure are also disclosed.

Abstract: A multilayer interconnect structure is formed by, providing a substrate having thereon a first dielectric for supporting a multi-layer interconnection having lower conductor MN, upper conductor MN+1, dielectric interlayer (DIL) and interconnecting via conductor VN+1/N. The lower conductor MN has a first upper surface located in a recess below a second upper surface of the first dielectric. The DIL is formed above the first and second surfaces. A cavity is etched through the DIL from a desired location of the upper conductor MN+1, exposing the first surface. The cavity is filled with a further electrical conductor to form the upper conductor MN+1 and the connecting via conductor VN+1/N making electrical contact with the first upper surface. A critical dimension between others of lower conductors MN and the via conductor VN+1/N is lengthened. Leakage current and electro-migration there-between are reduced.

Abstract: A method for fabricating an image sensor includes at least one of: (1) Forming a gate on a semiconductor substrate; (2) Forming spacers on both side walls of the gate and forming a dummy pattern on an upper portion of the semiconductor substrate; and (3) Forming a metal pad for an electrical connection on an upper portion of the dummy pattern. The method may include at least one of: (1) Forming an interlayer dielectric layer covering the entire semiconductor substrate, (2) Etching portions of the interlayer dielectric layer and the semiconductor substrate to form a super-contact hole; and (3) forming an insulation film on the entire surface of the interlayer dielectric layer. The method may include forming normal contact holes such that a portion of an upper portion of the gate and a partial region of the metal pad for an electrical connection are exposed and filling up the normal contact holes with a conductive material to form normal contacts.

Abstract: A passivation layer is formed on inlaid Cu for protection against oxidation and removal during subsequent removal of an overlying metal hardmask. Embodiments include treating an exposed upper surface of inlaid Cu with hydrofluoric acid and a copper complexing agent, such as benzene triazole, to form a passivation monolayer of a copper complex, etching to remove the metal hardmask, removing the passivation layer by heating to at least 300° C., and forming a barrier layer on the exposed upper surface of the inlaid Cu.

Abstract: Ions of silicon are implanted into source/drain regions in a semiconductor wafer to amorphize an ion implantation region in the semiconductor wafer. A nickel film is deposited on the amorphized ion implantation region. First irradiation from a flash lamp is performed on the semiconductor wafer with the nickel film deposited thereon to increase the temperature of a front surface of the semiconductor wafer from a preheating temperature to a target temperature for a time period in the range of 1 to 20 milliseconds. Subsequently, second irradiation from the flash lamp is performed to maintain the temperature of the front surface of the semiconductor wafer within a ±25° C. range around the target temperature for a time period in the range of 1 to 100 milliseconds. This causes nickel silicide to grow preferentially in a direction perpendicular to the semiconductor wafer.

Abstract: Provided is a semiconductor device manufacturing method enabling miniaturization by forming a hole in a vertical shape, capable of reducing the number of processes as compared to conventional methods, and capable of increasing productivity. The semiconductor device manufacturing method includes: forming a hole in a substrate; forming a polyimide film within the hole; anisotropically etching the substrate without using a mask covering a sidewall portion of the polyimide film within the hole and removing at least a part of a bottom portion of the polyimide film within the hole while the sidewall portion of the polyimide film remains within the hole; and filling the hole with a conductive metal.

Abstract: An object is to provide a semiconductor device having excellent characteristics, in which a channel layer includes an oxide semiconductor with high crystallinity. In addition, a semiconductor device including a base film with improved planarity is provided. CMP treatment is performed on the base film of the transistor and plasma treatment is performed thereon after the CMP treatment, whereby the base film can have a center line average roughness Ra75 of less than 0.1 nm. The oxide semiconductor layer with high crystallinity is formed over the base film having planarity, which is obtained by the combination of the plasma treatment and the CMP treatment, thereby improving the characteristics of the semiconductor device.

Abstract: A semiconductor device manufacturing method, comprising: providing a semiconductor substrate, on which a gate conductor layer as well as a source region and a drain region positioned on both sides of the gate conductor layer are provided, forming an etch stop layer on the semiconductor substrate, forming an LTO layer on the etch stop layer, chemical mechanical polishing the LTO layer, forming an SOG layer on the polished LTO layer, the etch stop layer, LTO layer and SOG layer forming a front metal insulating layer, back etching the SOG layer and etch stop layer of the front metal insulating layer to expose the gate conductor layer, and removing the gate conductor layer.

Abstract: In a semiconductor device manufacturing method, on a film to be processed, a mask material film is formed which has pattern openings for a plurality of contact patterns and connection openings for connecting adjacent pattern openings in such a manner that the connection between them is constricted in the middle. Then, a sidewall film is formed on the sidewalls of the individual openings in the mask material film, thereby not only making the diameter of the pattern openings smaller but also separating adjacent pattern openings. Then, the film to be processed is selectively etched with the mask material film and sidewall film as a mask, thereby making contact holes.

Abstract: The present invention discloses a method of fabricating a semiconductor device. In the present invention, after the formation of a photo-resist mask on a substrate, the photo-resist is subjected to a plasma pre-treatment, and then etch is conducted. With the plasma pre-treatment, a line width roughness of a linear pattern of the photo-resist can be improved, and thus much better linear patterns can be formed on the substrate during the subsequent etching steps.

Abstract: There is provided a method for manufacturing a nitride semiconductor substrate, comprising: etching and flattening a surface of a nitride semiconductor substrate disposed facing a surface plate, by using the surface plate having a surface composed of any one of Ni, Ti, Cr, W, and Mo or nitride of any one of them, disposing the surface of the surface plate and a flattening surface of a nitride semiconductor substrate proximately so as to be faced each other, and supplying gas containing at least hydrogen and ammonia between the surface of the surface plate and the surface of the nitride semiconductor substrate, wherein the surface plate and the nitride semiconductor substrate facing each other are set in a high temperature state of 900° C. or more.

Abstract: A method of etching or removing an organic hardmask overlying a low dielectric constant film in a lithographic process. The method includes providing a dielectric film having thereover an organic hardmask to be removed, the dielectric film having a dielectric constant no greater than about 4.0, introducing over the organic hardmask an ionizable gas comprising a mixture of hydrogen and an oxidizing gas, and applying energy to the mixture to create a plasma of the mixture. The method further includes contacting the organic hardmask with the plasma, with the organic hardmask being at a temperature in excess of 200° C., to remove the organic hardmask without substantially harming the underlying substrate.

Abstract: A method for performing a spacer etch process is described. The method includes conformally applying a spacer material over a gate structure on a substrate, and performing a spacer etch process sequence to partially remove the spacer material from a capping region of the gate structure and a substrate region on the substrate adjacent a base of the gate structure, while retaining a spacer sidewall positioned along a sidewall of the gate structure.

Abstract: A method of selective deposition on silicon substrates having regions of bare silicon and regions of oxide formed thereon. The method includes placing the substrate on a wafer support inside a processing chamber, introducing a carbon-containing gas into the reactor, applying a bias to the substrate, generating a plasma from the hydrocarbon gas, implanting carbon ions into the regions of oxide on the substrate by a plasma doping process, and depositing a carbon-containing film on the bare silicon regions.

Abstract: Aspects of the disclosure pertain to methods of depositing silicon oxide layers on substrates. In embodiments, silicon oxide layers are deposited by flowing a silicon-containing precursor having a Si—O bond, an oxygen-containing precursor and a second silicon-containing precursor, having both a Si—C bond and a Si—N bond, into a semiconductor processing chamber to form a conformal liner layer. Upon completion of the liner layer, a gap fill layer is formed by flowing a silicon-containing precursor having a Si—O bond, an oxygen-containing precursor into the semiconductor processing chamber. The presence of the conformal liner layer improves the ability of the gap fill layer to grow more smoothly, fill trenches and produce a reduced quantity and/or size of voids within the silicon oxide filler material.

Abstract: An elastic laminate for use as a tear resistant diaper side panel. The elastic laminate comprises an elastic substrate bonded to at least one layer of a tensioned spunbond nonwoven web comprising thermoplastic filaments comprising at least about 10% by weight polyethylene. The laminate is then incrementally stretched in the transverse direction to provide a service stretch greater than 100% and a strength ratio greater than 0.35. In one embodiment, the elastic substrate is bonded between the tensioned nonwoven webs by point bonding or hot melt adhesives.

Abstract: Disclosed is a multilayer fabric and a method of forming a multilayer fabric comprising one or more facing layers and one or more elastic layers adjacent to or sandwiched there between, the one or more facing layers comprising a polypropylene; and a propylene-?-olefin elastomer having and an MFR of less than 80 dg/min; wherein the facing layer is extensible and non-elastic and has a Handle-O-Meter value of less than 60 g and a 1% Secant Flexural Modulus of less than 1000 MPa. In certain embodiments, polyethylenes are absent from the facing layer(s).

Abstract: Crystallizable glasses, glass-ceramics, IXable glass-ceramics, and IX glass-ceramics are disclosed. The glass-ceramics exhibit ?-spodumene ss as the predominant crystalline phase. These glasses and glass-ceramics, in mole %, include: 62-75 Si O2; 10.5-17 Al2O3; 5-13 Li2O; 0-4 ZnO; 0-8 MgO; 2-5 TiO2; 0-4 B2O3; 0-5 Na2O; 0-4 K2O; 0-2 ZrO2; 0-7 P2O5; 0-0.3 Fe2O3; 0-2 MnOx; and 0.05-0.2 SnO2. Additionally, these glasses and glass-ceramics exhibit the following criteria: a. a ratio: [ Li 2 ? O + Na 2 ? O + K 2 ? O + MgO + ZnO ] [ Al 2 ? O 3 + B 2 ? O 3 ] between 0.7 to 1.5; b. a ratio: [ TiO 2 + SnO 2 ] [ SiO 2 + B 2 ? O 3 ] greater than 0.04. Furthermore, the glass-ceramics exhibit an opacity ?about 85% over the wavelength range of 400-700 nm for an about 0.

Abstract: Crystallizable glasses, glass-ceramics, IXable glass-ceramics, and IX glass-ceramics are disclosed. The glass-ceramics exhibit ?-spodumene ss as the predominant crystalline phase. These glasses and glass-ceramics, in mole %, include: 62-75 SiO2; 10.5-17 Al2O3; 5-13 Li3O; 0-4 ZnO; 0-8 MgO; 2-5 TiO2; 0-4 B2O3; 0-5 Na2O; 0-4 K2O; 0-2 ZrO2; 0-7 P2O5; 0-0.3 Fe2O3; 0-2 MnOx; and 0.05-0.2 SnO2. Additionally, these glasses and glass-ceramics exhibit the following criteria: a. a ratio: [ Li 2 ? O + Na 2 ? O + K 2 ? O + MgO + ZnO _ ] ? [ Al 2 ? O 3 + B 2 ? O 3 ] between 0.7 to 1.5; b. a ratio: [ TiO 2 + SnO 2 _ ] ? [ SiO 2 + B 2 ? O 3 ] greater than 0.04. Furthermore, the glass-ceramics exhibit an opacity ?about 85% over the wavelength range of 400-700 nm for an about 0.

Abstract: A high transmittance glass includes: SiO2 in the range of 65 to 75 weight percent; Na2O in the range of 10 to 20 weight percent; CaO in the range of 5 to 15 weight percent; MgO in the range of 0 to 5 weight percent; Al2O3 in the range of 0 to 5 weight percent; K2O in the range of 0 to 5 weight percent; MnO2 in the range of 0.035 to 0.6 weight percent; FeO in the range of 0.0010 to 0.0030 weight percent; and Fe2O3 (total iron) in the range of 0.001 to 0.03 weight percent. The glass has a redox ratio in the range of 0.1 to 0.4.

Abstract: An optical glass having optical constants of a refractive index (nd) of 1.78 or over, an Abbe number (?d) of 30 or below, and a partial dispersion ratio (?g, F) of 0.620 or below comprises SiO2 and Nb2O5 as essential components, wherein an amount of Nb2O5 in mass % is more than 40%. The optical glass further comprising, in mass % on oxide basis, less than 2% of K2O and one or more oxides selected from the group consisting of B2O3, TiO2, ZrO2, WO3, ZnO, SrO, Li2O and Na2O wherein a total amount of SiO2, B2O3, TiO2, ZrO2, Nb2O5, WO3, ZnO, SrO, Li2O and Na2O is more than 90% and TiO2/(ZrO2+Nb2O5) is less than 0.32.

Abstract: A crystallizing glass solder for high-temperature applications, containing, in % by weight on an oxide basis: 45% to 60% of BaO, 25% to 40% of SiO2, 5% to 15% of B2O3, 0 to <2% of Al2O3, and at least one alkaline earth metal oxide from the group consisting of MgO, CaO and SrO, wherein CaO is 0% to 5% and the sum of the alkaline earth metal oxides MgO, CaO and SrO is 0% to 20%, preferably 2% to 15%. The glass solder is preferably free from TeO2 and PbO. Preferred embodiments of the glass solder contain from 3 to 15 wt. % of Y2O3 and have low porosity and high stability with respect to a moist fuel gas environment.

Abstract: An article including a monolithic crucible body comprising silicon oxynitride (SixNyO, wherein x>0 and y>0), wherein the silicon oxynitride extends throughout the entire volume of the monolithic crucible body.

Abstract: A sintered body includes an indium oxide crystal, and an oxide solid-dissolved in the indium oxide crystal, the oxide being oxide of one or more metals selected from the group consisting of aluminum and scandium, the sintered body having an atomic ratio “(total of the one or more metals)/(total of the one or more metals and indium)×100)” of 0.001% or more and less than 45%.

Abstract: A regenerating method for activated alumina used in regenerating working fluid of hydrogen peroxide comprises the following steps: adding deactivated alumina discharged from a regenerating bed for working fluid of hydrogen peroxide into a reactor through the top of the reactor and settling by gravity, oxidizing atmosphere entering into the reactor from the bottom of the reactor and running upwardly, then discharging exit gas and regenerated alumina through the discharge port on the top and discharging device on the bottom of the reactor respectively. The method is economic, environment-protective, safe, low-costly. The regenerated alumina will not poison palladium catalyst.

Abstract: A regenerating method for activated alumina used in regenerating working fluid of hydrogen peroxide comprises the following steps: adding deactivated alumina discharged from a regenerating bed for working fluid of hydrogen peroxide with fire resistant alumina into a reactor through the top of the reactor and settling by gravity, oxidizing atmosphere entering into the reactor from the bottom of the reactor and running upwardly, discharging regenerated alumina and fire resistant alumina through the discharging device on the bottom of the reactor, discharging exit gas through the discharge port on the top of the reactor, the reaction temperature ranging from 360-800° C., the residence time of solid feed in the reactor ranging from 3-15 h. The method is economic, environment-protective, safe, and low-costly. The regenerated alumina will not poison palladium catalyst.

Abstract: A desulfurization method of a nitrogen oxide absorption catalyst when diesel is used may include determining how many times a regeneration of a diesel particulate filter (DPF) is completed, ending a DPF regeneration, if the number of times of the DPF regeneration reaches a predetermined value and entering into a desulfurization mode to desulfurize the DPF, ending the desulfurization mode after the desulfurization mode is performed for a predetermined time, and calculating a particulate matters (PM) amount that is trapped in the DPF after the desulfurization, compensating the trapped PM amount, and determining a time of the DPF regeneration. A desulfurization timing is determined based on the number of times that the DPF is regenerated to be able to simplify the desulfurization logic and also reduce the memory of ECU, when the LNT catalyst is poisoned by a small amount of sulfur included in exhaust gas.

Abstract: Process for supportation of a catalyst system comprising at least two different active catalyst components on a support wherein in an earlier supportation step a first active catalyst component is applied to the support at a first predetermined temperature and in a later supportation step a second active catalyst component is applied to the support at a temperature which is at least 20° C. lower than the first predetermined temperature.