Abstract: A method includes performing an etching step on a package. The package includes a package component, a connector on a top surface of the package component, a die bonded to the top surface of the package component, and a molding material molded over the top surface of the package component. The molding material covers the connector, wherein a portion of the molding material covering the connector is removed by the etching step, and the connector is exposed.

Abstract: A method and device for preventing the bridging of adjacent metal traces in a bump-on-trace structure. An embodiment comprises determining the coefficient of thermal expansion (CTE) and process parameters of the package components. The design parameters are then analyzed and the design parameters may be modified based on the CTE and process parameters of the package components.

Abstract: A method to construct configurable systems, the method including: providing a first configurable system including a first die and a second die, where the connections between the first die and the second die include through-silicon-via (“TSV”), where the first die is diced from a first wafer using first dice lines; providing a second configurable system including a third die and a fourth die, where the connections between the third die and the fourth die include through-silicon-via (“TSV”), where the third die is diced from a third wafer using third dice lines; and processing the first wafer and the third wafer utilizing at least 20 masks that are the same; where the first dice lines are substantially different than the third dice lines, and where the second die includes a configurable I/O to connect the first configurable system to external devices.

Abstract: A method of manufacturing a laminate electronic device is disclosed. One embodiment provides a carrier, the carrier defining a first main surface and a second main surface opposite to the first main surface. The carrier has a recess pattern formed in the first main surface. A first semiconductor chip is attached on one of the first and second main surface. A first insulating layer overlying the main surface of the carrier on which the first semiconductor chip is attached and the first semiconductor chip is formed. The carrier is then separated into a plurality of parts along the recess pattern.

Abstract: A fan-out wafer level package is provided with a semiconductor die embedded in a reconstituted wafer. A redistribution layer is positioned over the semiconductor die, and includes a land grid array on a face of the package. A copper heat spreader is formed in the redistribution layer over the die in a same layer as a plurality of electrical traces configured to couple circuit pads of the semiconductor die to respective contact lands of the land grid array. In operation, the heat spreader improves efficiency of heat transfer from the die to the circuit board.

Abstract: A process of manufacturing an LED lamp strip includes the steps of forming a plurality of through holes on an adhesive tape, mounting the adhesive tape to a top side of a scrollable lead frame, bonding a plurality of LED chips to the top side of the scrollable lead frame according to the positions of the through holes, packaging the LED chips respectively, and finally cutting the scrollable lead frame. In light of this, the LED lamp strip can be produced under the circumstances of low production cost and less production time.

Abstract: In a semiconductor device, a lead frame made of a copper alloy prevents exfoliation occurring near the surface of the lead frame. A copper oxide layer is formed on the base material made of a copper alloy by immersing the base material into a solution of a strong oxidizer. The copper oxide layer serves as an outermost layer and consists of a copper oxide other than a copper oxide in the form of needle crystals.

Abstract: A method of protecting an electronics package is discussed along with devices formed by the method. The method involves providing at least one electronic component that requires protecting from tampering and/or reverse engineering. Further, the method includes mixing into a liquid glass material at least one of high durability micro-particles or high-durability nano-particles, to form a coating material. Further still, the method includes depositing the coating material onto the electronic component and curing the coating material deposited.

Abstract: A semiconductor device with minimized current flow differences and method of fabricating same are disclosed. The method includes forming a semiconductor stack including a plurality of layers that include a first layer having a first conductivity type and a second layer having a first conductivity type, in which the second layer is on top of the first layer, forming a plurality of mesas in the semiconductor layer stack, and forming a plurality of gates in the semiconductor layer stack having a second conductivity type and situated partially at a periphery of the mesas, in which the plurality of gates are formed to minimize current flow differences between a current flowing from the first layer to the plurality of mesas at a first applied gate bias and a current flowing from the first layer to the plurality of mesas at a second applied gate bias when voltage is applied to the semiconductor device.

Abstract: The PN junction of a substrate diode in a sophisticated SOI device may be formed on the basis of an embedded in situ doped semiconductor material, thereby providing superior diode characteristics. For example, a silicon/germanium semiconductor material may be formed in a cavity in the substrate material, wherein the size and shape of the cavity may be selected so as to avoid undue interaction with metal silicide material.

Abstract: A structure and method to improve ETSOI MOSFET devices. A wafer is provided including regions with at least a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer. The regions are separated by a STI which extends at least partially into the second semiconductor layer and is partially filled with a dielectric. A gate structure is formed over the first semiconductor layer and during the wet cleans involved, the STI divot erodes until it is at a level below the oxide layer. Another dielectric layer is deposited over the device and a hole is etched to reach source and drain regions. The hole is not fully landed, extending at least partially into the STI, and an insulating material is deposited in said hole.

Abstract: An embodiment of the invention provides a manufacturing method of a thin-film transistor includes: providing a substrate; sequentially forming a gate electrode, a gate insulating layer, and an active layer on the substrate; forming an insulating metal oxide layer covering the active layer, wherein the insulating metal oxide layer including a metal oxide of a first metal; forming a metal layer covering the active layer, wherein the metal layer includes a second metal; forming a source electrode and a drain electrode on the metal layer with a trench separating therebetween; removing the metal layer exposed by the trench; and performing an annealing process to the metal layer and the insulating metal oxide layer, such that the metal layer reacts with the insulating metal oxide layer overlapping the metal layer to form a conducting composite metal oxide layer including the first metal and the second metal.

Abstract: A semiconductor device and manufacturing method for the same are disclosed. The method includes providing a substrate that has an insulator layer and a semiconductor layer overlying the insulator layer. The method further includes forming a hard mask layer pattern on the semiconductor layer and etching the semiconductor layer using the patterned hard mask layer to form portions having different thickness in the semiconductor layer. The method also includes performing an oxygen-based treatment on the semiconductor layer to form a supporting oxide layer. A portion of the semiconductor layer is buried in the supporting oxide layer.

Abstract: A device isolation region is made of a silicon oxide film embedded in a trench, an upper portion thereof is protruded from a semiconductor substrate, and a sidewall insulating film made of silicon nitride or silicon oxynitride is formed on a sidewall of a portion of the device isolation region which is protruded from the semiconductor substrate. A gate insulating film of a MISFET is made of an Hf-containing insulating film containing hafnium, oxygen and an element for threshold reduction as main components, and a gate electrode that is a metal gate electrode extends on an active region, the sidewall insulating film and the device isolation region. The element for threshold reduction is a rare earth or Mg when the MISFET is an n-channel MISFET, and the element for threshold reduction is Al, Ti or Ta when the MISFET is a p-channel MISFET.

Abstract: The invention relates to a method for forming a semiconductor structure, comprising: providing a semiconductor substrate which comprises a dummy gate formed thereon, a spacer surrounding the dummy gate, source and drain regions formed on two sides of the dummy gate, respectively, and a channel region formed in the semiconductor substrate and below the dummy gate; removing the dummy gate to form a gate opening; forming a stressed material layer in the gate opening; performing an annealing to the semiconductor substrate, the stressed material layer having tensile stress characteristics during the annealing; removing the stressed material layer in the gate opening; and forming a gate in the gate opening. By the above steps, the stress memorization technique can be applied to the pMOSFET.

Abstract: A fin field-effect transistor structure includes a substrate, a fin channel and a high-k metal gate. The high-k metal gate is formed on the substrate and the fin channel. A process of manufacturing the fin field-effect transistor structure includes the following steps. Firstly, a polysilicon pseudo gate structure is formed on the substrate and a surface of the fin channel. By using the polysilicon pseudo gate structure as a mask, a source/drain region is formed in the fin channel. After the polysilicon pseudo gate structure is removed, a high-k dielectric layer and a metal gate layer are successively formed. Afterwards, a planarization process is performed on the substrate having the metal gate layer until the first dielectric layer is exposed, so that a high-k metal gate is produced.

Abstract: When forming cavities in active regions of semiconductor devices in order to incorporate a strain\-inducing semiconductor material, superior uniformity may be achieved by using an implantation process so as to selectively modify the etch behavior of exposed portions of the active region. In this manner, the basic configuration of the cavities may be adjusted with a high degree of flexibility, while at the same time the dependence on pattern loading effect may be reduced. Consequently, a significantly reduced variability of transistor characteristics may be achieved.

Abstract: When forming high-k metal gate electrode structures in transistors of different conductivity type while also incorporating an embedded strain-inducing semiconductor alloy selectively in one type of transistor, superior process uniformity may be accomplished by selectively reducing the thickness of a dielectric cap material of a gate layer stack above the active region of transistors which do not receive the strain-inducing semiconductor alloy. In this case, superior confinement and thus integrity of sensitive gate materials may be accomplished in process strategies in which the sophisticated high-k metal gate electrode structures are formed in an early manufacturing stage, while, in a replacement gate approach, superior process uniformity is achieved upon exposing the surface of a placeholder electrode material.

Abstract: A method of fabricating an integrated circuit and an integrated circuit having silicon on a stress liner are disclosed. In one embodiment, the method comprises providing a semiconductor substrate comprising an embedded disposable layer, and removing at least a portion of the disposable layer to form a void within the substrate. This method further comprises depositing a material in that void to form a stress liner, and forming a transistor on an outside semiconductor layer of the substrate. This semiconductor layer separates the transistor from the stress liner. In one embodiment, the substrate includes isolation regions; and the removing includes forming recesses in the isolation regions, and removing at least a portion of the disposable layer via these recesses. In one embodiment, the depositing includes depositing a material in the void via the recesses. End caps may be formed in the recesses at ends of the stress liner.

Abstract: A method includes forming a shallow trench isolation (STI) region in a substrate; depositing a first material such that the first material overlaps the STI region and a portion of a top surface of the STI region is exposed; etching a recess in the STI region by a first etch, the recess having a bottom and sides; depositing a second material over the first material and on the sides and bottom of the recess in the STI region; and etching the first and second material by a second etch to form a floating gate of the device, wherein the floating gate extends into the recess.

Abstract: A semiconductor structure and a method of fabricating the same comprising the steps of providing a substrate, forming at least one fin structure on said substrate, forming a gate covering said fin structure, forming a plurality of epitaxial structures covering said fin structures, performing a gate pullback process to reduce the critical dimension (CD) of said gate and separate said gate and said epitaxial structures, forming lightly doped drains (LDD) in said fin structures, and forming a spacer on said gate and said fin structures.

Abstract: The present invention provides systems, methods and apparatus for manufacturing a memory cell. The invention includes forming a feature having sidewalls in a first dielectric material; forming a first conductive material on the sidewalls of the feature; depositing a layer of a second dielectric material on the conductive material; and exposing the second dielectric material to oxidizing species and ultraviolet light to oxidize the second dielectric material. Numerous additional aspects are disclosed.

Abstract: A method of manufacturing a flash memory cell includes providing a substrate having a first dielectric layer formed thereon, forming a control gate on the first dielectric layer, forming an oxide-nitride-oxide (ONO) spacer on sidewalls of the control gate, forming a second dielectric layer on the substrate at two sides of the ONO spacer, and forming a floating gate at outer sides of the ONO spacer on the second dielectric layer, respectively.

Abstract: A method for producing a semiconductor device includes the steps of forming a planar silicon layer, first and second pillar-shaped silicon layers on a silicon substrate; forming a gate insulating film, depositing a metal film and a polysilicon around the gate insulating film, conducting planarization, conducting etching to expose upper portions of the first and second pillar-shaped silicon layers, forming first and second insulating film sidewalls, and forming first and second gate electrodes and a gate line; forming n-type diffusion layers in upper and lower portions of the first pillar-shaped silicon layer, and forming p-type diffusion layers in upper and lower portions of the second pillar-shaped silicon layer; forming a third insulating film sidewall on side walls of the first and second insulating film sidewalls, the first and second gate electrodes, and the gate line; and forming a silicide.

Abstract: Example embodiments are directed to a method of forming a field effect transistor (FET) and a field effect transistor (FET) including a source/drain pair that is elevated with respect to the corresponding gate structure.

Abstract: A method for forming a transistor having insulated gate electrodes and insulated shield electrodes within trench regions includes forming dielectric stack overlying a substrate. The dielectric stack includes a first layer of one material overlying the substrate and a second layer of a different material overlying the first layer. Trench regions are formed adjacent to the dielectric stack. After the insulated shield electrodes are formed, the method includes removing the second layer and then forming the insulated gate electrodes. Portions of gate electrode material are removed to form first recessed regions, and spacers are formed within the first recessed regions. Enhancements regions are then formed in the gate electrode material self-aligned to the spacers.

Abstract: The present disclosure provides manufacturing techniques in which sophisticated high-k metal gate electrode structures may be formed in an early manufacturing stage on the basis of a selectively applied threshold voltage adjusting semiconductor alloy. In order to reduce the surface topography upon patterning the deposition mask while still allowing the usage of well-established epitaxial growth recipes developed for silicon dioxide-based hard mask materials, a silicon nitride base material may be used in combination with a surface treatment. In this manner, the surface of the silicon nitride material may exhibit a silicon dioxide-like behavior, while the patterning of the hard mask may be accomplished on the basis of highly selective etch techniques.

Abstract: An MOS transistor includes a doping profile that selectively increases the dopant concentration of the body region. The doping profile has a shallow portion that increases the dopant concentration of the body region just under the surface of the transistor under the gate, and a deep portion that increases the dopant concentration of the body region under the source and drain regions. The doping profile may be formed by implanting dopants through the gate, source region, and drain region. The dopants may be implanted in a high energy ion implant step through openings of a mask that is also used to perform another implant step. The dopants may also be implanted through openings of a dedicated mask.

Abstract: The drain and source regions may at least be partially formed by in situ doped epitaxially grown semiconductor materials for complementary transistors in sophisticated semiconductor devices designed for low power and high performance applications. To this end, cavities may be refilled with in situ doped semiconductor material, which in some illustrative embodiments also provides a desired strain in the channel regions of the complementary transistors.

Abstract: A semiconductor structure includes a gate structure, an epitaxial layer and a carbon-containing silicon germanium cap layer. The gate structure is located on a substrate. The epitaxial layer is located in the substrate beside the gate structure. The carbon-containing silicon germanium cap layer is located on the epitaxial layer. Otherwise, semiconductor processes for forming said semiconductor structure are also provided.

Abstract: A method for fabricating an integrated circuit device is disclosed. An exemplary method comprises performing a gate replacement process to form a gate structure, wherein the gate replacement process includes an annealing process; after the annealing process, removing portions of a dielectric material layer to form a contact opening, wherein a portion of the substrate is exposed; forming a silicide feature on the exposed portion of the substrate through the contact opening; and filling the contact opening to form a contact to the exposed portion of the substrate.

Abstract: A method of fabricating a castellated-gate MOSFET tetrode device capable of fully depleted operation is disclosed. The device is formed on a semiconductor substrate region having an upper portion with a top surface and a lower portion with a bottom surface. A source region and a drain region are formed by ion implantation into the semiconductor substrate region, with adjoined primary and secondary channel-forming regions also disposed therein between the source and drain regions, thereby forming an integrated cascode structure. A plurality of thin semiconductor channel elements are formed by etching a plurality of spaced gate slots to a first predetermined depth into the substrate. The formation of first, second, and additional gate structures are described in two possible embodiments which facilitate the formation of self-aligned source and drain regions.

Abstract: In sophisticated P-channel transistors, which may frequently suffer from a pronounced surface topography of the active regions with respect to the surrounding isolation regions, superior performance may be achieved by using a tilted implantation upon forming the deep drain and source regions, preferably with the tilt angle of 20 degrees or less, thereby substantially avoiding undue lateral dopant penetration into sensitive channel areas.

Abstract: A method for fabricating complimentary metal-oxide-semiconductor field-effect transistor is disclosed. The method includes the steps of: (A) forming a first gate structure and a second gate structure on a substrate; (B) performing a first co-implantation process to define a first type source/drain extension region depth profile in the substrate adjacent to two sides of the first gate structure; (C) forming a first source/drain extension region in the substrate adjacent to the first gate structure; (D) performing a second co-implantation process to define a first pocket region depth profile in the substrate adjacent to two sides of the second gate structure; (E) performing a first pocket implantation process to form a first pocket region adjacent to two sides of the second gate structure.

Abstract: A MOS transistor has a first stress layer formed over a silicon substrate on a first side of a channel region defined by a gate electrode, and a second stress layer formed over the silicon substrate on a second side of the channel region, the first and second stress layers accumulating a tensile stress or a compressive stress depending on a conductivity type of the MOS transistor. The first stress layer has a first extending part rising upward from the silicon substrate near the channel region along a first sidewall of the gate electrode but separated from the first sidewall of the gate electrode, and the second stress layer has a second extending part rising upward from the silicon substrate near the channel region along a second sidewall of the gate electrode but separated from the second sidewall of the gate electrode.

Abstract: A dual node dielectric trench capacitor includes a stack of layers formed in a trench. The stack of layers include, from bottom to top, a first conductive layer, a first node dielectric layer, a second conductive layer, a second node dielectric layer, and a third conductive layer. The dual node dielectric trench capacitor includes two back-to-back capacitors, which include a first capacitor and a second capacitor. The first capacitor includes the first conductive layer, the first node dielectric layer, the second conductive layer, and the second capacitor includes the second conductive layer, the second node dielectric layer, and the third conductive layer. The dual node dielectric trench capacitor can provide about twice the capacitance of a trench capacitor employing a single node dielectric layer having a comparable composition and thickness as the first and second node dielectric layers.

Abstract: A method of forming a capacitor structure comprises: forming a doped polysilicon layer on an underlying dielectric layer; forming a dielectric stack on the doped polysilicon layer; forming a contact hole in the dielectric stack to expose a surface region of the doped polysilicon layer; forming a conductive contact plug that fills the contact hole and is in contact with the exposed surface of the doped polysilicon layer; forming a plurality of trenches in the dielectric stack such that each trench exposes a corresponding surface region of the doped polysilicon layer; forming a conductive bottom capacitor plate on exposed surfaces of the of the dielectric stack and on exposed surfaces of the doped polysilicon layer; forming a capacitor dielectric layer on the bottom capacitor plate; and forming a conductive top capacitor plate on the capacitor dielectric layer.

Abstract: A method for forming a self-aligned overlay mark is disclosed. First, a first region, a second region and a main feature which is disposed between the first region and the second region all disposed on the substrate are provided. The first region defines a first edge and the second region defines a second edge. Second, a cut mask layer is formed to respectively cover the first region and the second region to expose the main feature. Next, the cut mask layer is determined if it is self-aligned with the second edge or the first edge, and creates a self-aligned overlay mark. Later, a main feature etching step is carried out to transfer the main feature into the substrate when the cut mask layer is determined to be self-aligned with the second edge or the first edge.

Abstract: An object is to provide a semiconductor device in which, through a simpler process, junction capacitance and power consumption can be reduced more than a conventional semiconductor device, and a manufacturing method thereof. An insulating film including an opening is formed over a base substrate and a part of a bond substrate is transferred to the base substrate, with the insulating film interposed therebetween, whereby a semiconductor film including a cavity between the semiconductor film and the base substrate is formed over the base substrate. Then, a semiconductor device including a semiconductor element such as a transistor is manufactured using the semiconductor film. The transistor includes a cavity between the base substrate and the semiconductor film used as an active layer. One cavity may be provided or a plurality of cavities may be provided.

Abstract: The disclosure relates to integrated circuit fabrication, and more particularly to a method for fabricating a semiconductor device. An exemplary method for fabricating the semiconductor device comprises providing a substrate; forming pad oxide layers over a frontside and a backside of the substrate; forming hardmask layers over the pad oxide layers on the frontside and the backside of the substrate; and thinning the hardmask layer over the pad oxide layer on the frontside of the substrate.

Abstract: A method for forming a vertical electrostatic discharge (ESD) protection device includes depositing a multi-layer n-type epitaxial layer on a substrate having p-type surface including first epitaxial depositing to form a first n-type epitaxial layer on the p-type surface, and second epitaxial depositing to form a second n-type epitaxial layer formed on the first n-type epitaxial layer. The first type epitaxial layer has a peak doping level which is at least double that of the second n-type epitaxial layer. A p+ layer is formed on the second n-type epitaxial layer. An etch step etches through the p+ layer and multi-layer n-type epitaxial layer to reach the substrate to form a trench. The trench is filled with a filler material to form a trench isolation region. A metal contact is formed on the p+ layer for providing contact to the p+ layer.

Abstract: A computer readable medium is provided that is encoded with a program comprising instructions for performing a method for fabricating a 3D integrated circuit structure. Provided are an interface wafer including a first wiring layer and through-silicon vias, and a first active circuitry layer wafer including active circuitry. The first active circuitry layer wafer is bonded to the interface wafer. Then, a first portion of the first active circuitry layer wafer is removed such that a second portion remains attached to the interface wafer. A stack structure including the interface wafer and the second portion of the first active circuitry layer wafer is bonded to a base wafer. Next, the interface wafer is thinned so as to form an interface layer, and metallizations coupled through the through-silicon vias in the interface layer to the first wiring layer are formed on the interface layer.

Abstract: The invention pertains to a combination of a substrate and a wafer, wherein the substrate and the wafer are arranged parallel to one another and bonded together with the aid of an adhesive layer situated between the substrate and the wafer, and wherein the adhesive is chosen such that its adhesive properties are neutralized or at least diminished when a predetermined temperature is exceeded. According to the invention, the adhesive layer is only applied annularly between the substrate and the wafer in the edge region of the wafer.

Abstract: InP epitaxial material is directly bonded onto a Silicon-On-Insulator (SOI) wafer having Vertical Outgassing Channels (VOCs) between the bonding surface and the insulator (buried oxide, or BOX) layer. H2O and other molecules near the bonding surface migrate to the closest VOC and are quenched in the buried oxide (BOX) layer quickly by combining with bridging oxygen ions and forming pairs of stable nonbridging hydroxyl groups (Si—OH). Various sizes and spacings of channels are envisioned for various devices.

Abstract: A method for making a thin-film element includes epitaxially growing a first crystalline layer on a second crystalline layer of a support where the second crystalline layer is a material different from the first crystalline layer, the first crystalline layer having a thickness less than a critical thickness. A dielectric layer is formed on a side of the first crystalline layer opposite to the support to form a donor structure. The donor structure is assembled with a receiver layer and the support is removed.

Abstract: A composite-substrate manufacturing method is provided with: a step of carrying out implantation of ions through a surface of a bulk substrate composed of the nitride compound semiconductor; a step of setting said surface of the bulk substrate against the second substrate, and bonding the bulk substrate and the second substrate together to obtain a bonded substrate; a step of elevating the temperature of the bonded substrate to a first temperature; a step of sustaining the first temperature for a fixed time; and a step of producing a composite substrate by severing the remaining portion of the bulk substrate from the bonded substrate; characterized in that a predetermined formula as for the first temperature, the thermal expansion coefficient of the first substrate, and the thermal expansion coefficient of the second substrate is satisfied.

Abstract: A method for manufacturing a semiconductor thin film device includes: forming a buffer layer on an Si (111) substrate and a single crystal semiconductor layer on the buffer layer; forming an island including the semiconductor layer, buffer layer, and a portion of the substrate; forming a coating layer on the island; etching the substrate along its Si (111) plane to release the island from the substrate, the coating layer serving as a mask; and bonding the released island to another substrate, a released surface of the released island contacting the another substrate. A semiconductor device includes a single crystal semiconductor layer other than Si, which has a semiconductor device formed on a front surface of an Si (111) layer lying in a (111) plane. The layer is bonded to another substrate with a back surface contacting the another substrate or a bonding layer formed on the another substrate.

Abstract: A method of manufacturing a semiconductor structure is disclosed, which includes providing a substrate comprising a bottom surface and a growth surface opposite to the bottom surface; forming a buffer layer comprising a first surface which is not a C-plane substantially parallel with the bottom surface on the growth surface; forming a semiconductor structure on the buffer layer; forming at least one cavity in the buffer layer; extending the cavity along a main extending direction; separating the substrate and the semiconductor structure; wherein the main extending direction is substantially not parallel with the normal direction of the first surface.

Abstract: Provided are a heat sink material made of an alloy or a composite material including two or more types of elements which has an end surface that makes possible formation of an edge portion on which at least a laser element is mounted, a manufacturing method for the same, and a semiconductor laser device including the heat sink material. A heat sink material (10) is made of an alloy or a composite material including two or more types of elements, and provided with a main surface having a relatively large area and a secondary surface having a relatively small area which crosses the main surface, and the secondary surface includes a surface on which a discharging process has been carried out using a discharge wire (200) that is placed approximately parallel to the main surface.

Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer having a backmetal layer by placing the semiconductor wafer onto a carrier tape with the backmetal layer adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the backmetal layer within the singulation lines, and fluid machining the semiconductor wafer to remove the backmetal layer from the singulation lines.