Abstract: According to an exemplary embodiment, a bondwireless power module includes a common output pad coupling an emitter/anode node of a high side device to a collector/cathode node of a low side device. The bondwireless power module also includes a high side conductive clip connecting a collector of the high side device to a cathode of the high side device, and causing current to traverse through the high side conductive clip to another high side conductive clip in another power module. The bondwireless power module further includes a low side conductive clip connecting an emitter of the low side device to an anode of the low side device, and causing current to traverse through the low side conductive clip to another low side conductive clip in the another power module. The bondwireless power module can be a motor drive inverter module.

Abstract: A power converter includes a plurality of semiconductor modules that have main body sections, each of the main body sections has a semiconductor element therein, and power terminals projected from the main body sections, and a plurality of bus bars that connect the power terminals of the semiconductor modules. At least one of the plurality of the bus bars are connecting bus bars which have a plurality of terminal connecting sections that connect the power terminals of the plurality of different semiconductor modules, and connecting sections that connect the terminal connecting sections. The entirety of each of the connecting bus bars is formed integrally. The terminal connecting sections and the connecting section of every connecting bus bar are provided alternately in the connecting bus bar, and disposed in substantially the same position in a projecting direction of the power terminals.

Abstract: A semiconductor package configured to attain a thin profile and low moisture sensitivity. Packages of this invention can include a semiconductor die mounted on a die attachment site of a leadframe and further connected with a plurality of elongate I/O leads arranged about the die attach pad and extending in said first direction. The leadframe having an “up-set” bonding pad arranged with a bonding support for supporting a plurality of wire bonds and a large mold flow aperture in the up-set bonding pad. The package encapsulated in a mold material that surrounds the bonding support and flows through the large mold flow aperture to establish well supported wire bonds such that the package has low moisture sensitivity.

Abstract: A power semiconductor device is provided in which reliability can be improved when the parallel number of semiconductor devices increases. When a bonding face on collector electrode is on an upper side, and a bonding face on emitter electrode is on a lower side, a collector electrode joint region as a joint region between a collector trace and a collector electrode on a chip mounted substrate and an emitter electrode joint region as a joint region between an emitter trace and an emitter electrode are located at a same position in an up-and-down direction and are adjacent in a right-and-left direction at an interval of 2 mm or more and 4 mm or less.

Abstract: To minimize the warpage of an organic substrate that supports at least one electrical hardware component (e.g., a system-in-package module), a bottom surface of a lid is attached to a top surface of the electrical hardware component. The lid includes a leg that extends from the bottom surface of the lid towards a top surface of the substrate. A portion of the leg closest to the substrate may move relative to the substrate. As the lid warps, the lid does not also cause distortion of the substrate. The leg may be a flange that extends at least a portion of the width or at least a portion of the length of the lid, may be a post located at the perimeter of the lid, or may be any other portion extending from above the electrical component towards the substrate.

Abstract: A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.

Abstract: A semiconductor package is provided, including a laminate substrate with an aperture sized to receive a semiconductor die. Through-holes in the substrate are filled with a thermally conductive adhesive. A first heat spreader is attached to the by the adhesive, and a semiconductor die is positioned in the aperture with a back face in thermal contact with the heat spreader. Wire bonds couple the die to electrical traces on the substrate. A second heat spreader is attached by the adhesive to the substrate over the die, directly opposite the first heat spreader. A portion of the second heat spreader is encapsulated in molding compound. Openings in the second heat spreader admits molding compound to fill the space around the die between the heat spreaders. Heat is transmitted from the die to the first spreader, and thence, via the through-holes and conductive paste, to the second heat spreader.

Abstract: A semiconductor device includes: a semiconductor substrate; a heat sink mounted on an upper surface of the semiconductor substrate; wirings formed on a lower surface of the semiconductor substrate; and the like. The heat sink is mounted on the upper surface of the semiconductor substrate, and a planar size thereof is approximately the same as that of the semiconductor substrate. Moreover, the heat sink has a thickness of 500 ?m to 2 mm, and may be formed to be thicker than the semiconductor substrate. By using the heat sink to reinforce the substrate, a thickness of the semiconductor substrate can be reduced to, for example, about 50 ?m. As a result, a thickness of the entire semiconductor device can be reduced.

Abstract: A multi-chip module (MCM) structure comprises more than one semiconductor chip lying in a horizontal plane, the MCM having individual chip contact patches on the chips and a flexible heat sink having lateral compliance and extending in a plane in the MCM and secured in a heat exchange relation to the chips through the contact patches. The MCM has a mismatch between the coefficient of thermal expansion of the heat sink and the MCM and also has chip tilt and chip height mismatches. The flexible heat sink with lateral compliance minimizes or eliminates shear stress and shear strain developed in the horizontal direction at the interface between the heat sink and the chip contact patches by allowing for horizontal expansion and contraction of the heat sink relative to the MCM without moving the individual chip contact patches in a horizontal direction.

Abstract: Micro-plasma is generated at the tip of a micro-spring by applying a positive voltage to the spring's anchor portion and a negative voltage to an electrode maintained a fixed gap distance from the spring's tip portion. By generating a sufficiently large voltage potential (i.e., as determined by Peek's Law), current crowding at the tip portion of the micro-spring creates an electrical field that sufficiently ionizes neutral molecules in a portion of the air-filled region surrounding the tip portion to generate a micro-plasma event. Ionic wind air currents are generated by producing multiple micro-plasma events using micro-springs disposed in a pattern to produce a pressure differential that causes air movement over the micro-springs. Ionic wind cooling is produced by generating such ionic wind air currents, for example, in the gap region between an IC die and a base substrate disposed in a flip-chip arrangement.

Abstract: An integrated circuit structure includes a semiconductor substrate; a conductive via (TSV) passing through the semiconductor substrate; and a copper-containing post overlying the semiconductor substrate and electrically connected to the conductive via.

Abstract: A semiconductor device includes an interlayer insulating film containing Si, O, C, and H, an under-bump metal film disposed over the interlayer insulating film and containing Ni, and a bump electrode disposed over the under-bump metal film. In the interlayer insulating film, a ratio of a peak height of Si—CH3 near a wave number 1270 cm?1 to a peak height of Si—O near a wave number 1030 cm?1 obtained by Fourier-transform infrared spectroscopy (FTIR) is 0.15 or greater and 0.27 or less. A ratio of a peak height of Si—CH2—Si near a wave number 1360 cm?1 to the peak height of Si—CH3 near the wave number 1270 cm?1 is 0.031 or greater.

Abstract: A semiconductor device includes a substrate and a first sintered silver layer on the substrate. The semiconductor device includes a first semiconductor chip and a first diffusion soldered layer coupling the first semiconductor chip to the first sintered silver layer.

Abstract: A circuit substrate having a mounting surface on which a semiconductor chip is mounted and at least one connection pad formed on the mounting surface is connected to a support plate having at least one mounting portion with a diameter larger than a diameter of the connection pad, through a truncated-cone-shaped solder layer which is formed from at least one solder ball on the basis of a difference between the diameter of the mounting portion and the diameter of the connection pad.

Abstract: A wiring structure for a semiconductor device includes a multilayer metallization having a total thickness of at least 5 ?m and an interlayer disposed in the multilayer metallization with a first side of the interlayer adjoining one layer of the multilayer metallization and a second opposing side of the interlayer adjoining a different layer of the multilayer metallization. The interlayer includes at least one of W, WTi, Ta, TaN, TiW, and TiN or other suitable compound metal or a metal silicide such as WSi, MoSi, TiSi, and TaSi.

Abstract: One aspect of the present invention is a method of making an electronic device. According to one embodiment, the method comprises depositing a cap layer containing at least one dopant onto a gapfill metal and annealing so that the at least one dopant migrates to grain boundaries and/or interfaces of the gapfill metal. Another aspect of the present invention is an electronic device.

Abstract: A structure for an integrated circuit with reduced contact resistance is disclosed. The structure includes a substrate, a cap layer deposited on the substrate, a dielectric layer deposited on the cap layer, and a trench embedded in the dielectric layer. The trench includes an atomic layer deposition (ALD) TaN or a chemical vapor deposition (CVD) TaN deposited on a side wall of the trench, a physical vapor deposition (PVD) Ta or a combination of the PVD Ta and a PVD TaN deposited on the ALD TaN or CVD TaN, and a Cu deposited on the PVD Ta or the combination of the PVD Ta and the PVD TaN deposited on the ALD TaN or the CVD TaN. The structure further includes a via integrated into the trench at bottom of the filled trench.

Abstract: A substrate having, on a base material, a barrier film for preventing copper diffusion containing one or more metal elements selected from tungsten, molybdenum and niobium, a metal element having a catalytic function in electroless plating such as platinum, gold, silver and palladium, and nitrogen contained in the form of a nitride of the aforementioned one or more metal elements selected from tungsten, molybdenum and niobium. The barrier film for preventing copper diffusion is manufactured by sputtering in a nitrogen atmosphere using a target containing one or more metal elements selected from tungsten, molybdenum and niobium and the aforementioned metal element having a catalytic function in electroless plating.

Abstract: A conductive structure includes a contact plug extending through an insulating layer on a substrate, and first and second conductive lines extending alongside one another on the insulating layer. The first conductive line extends on the contact plug. A connecting line on the insulating layer extends between and electrically connects the first and second conductive lines. Related integrated circuit devices and fabrication methods are also discussed.

Abstract: An interconnecting mechanism is provide, which includes paired first sub-interconnecting mechanisms and paired second sub-interconnecting mechanisms. The first pair of sub-interconnecting mechanisms includes first and second axially symmetrical spiral conductive elements. The second pair of sub-interconnecting mechanisms includes third and fourth axially symmetrical spiral conductive elements. Configuring the pairs of sub-interconnecting mechanisms in a differential transmission structure having a spiral shape is used to avert sounds and noise signals between different chips or substrates caused by a miniaturizing fabrication process or an increased wiring density.

Abstract: This invention relates to a packaging structure and method for manufacturing the packaging structure. The packaging structure comprises a substrate film, a plurality of chips, a compound resin layer and a support layer. The substrate film is formed with circuits having a plurality of terminals exposed from a solder mask. The chips, each of which has a plurality of pads, under bump metals (UBMs) formed on the pads, and composite bumps disposed onto the UBMs, are bonded onto the substrate film to form the first tape. The second tape comprises the support layer and the compound resin layer formed on the support layer. The first tape and the second tape are both in reel-form and are expanded towards a pair of rollers to be heated and pressurized for encapsulating the chips.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, an integrated circuit includes a standard cell having a first boundary, a second boundary opposite the first boundary, a third boundary interconnecting the first and second boundaries, and a fourth boundary opposite the third boundary and interconnecting the first and second boundaries. The standard cell further includes parallel active areas extending from the first boundary to the second boundary. Also, the standard cell has parallel gate strips extending from the third boundary to the fourth boundary and over the active areas. A cut mask overlies the gate strips. An interconnect is positioned overlying the cut mask and forms an electrical connection with a selected gate strip.

Abstract: A method of making contact pad sidewall spacer and pad sidewall spacers are disclosed. An embodiment includes forming a plurality of contact pads on a substrate, each contact pad having sidewalls, forming a first photoresist over the substrate, and removing the first photoresist from the substrate thereby forming sidewall spacers along the sidewalls of the plurality of the contact pads.

Abstract: To provide a semiconductor device comprising a first layer that is provided on a semiconductor substrate and includes a first wiring pattern planarized by CMP and a plurality of first dummy patterns made of a same material as the first wiring pattern and a second layer that is provided above the semiconductor substrate and includes a second wiring pattern planarized by CMP and a plurality of second dummy patterns made of a same material as the second wiring pattern. A central axis of each of the second dummy patterns coincides with that of a corresponding one of the first dummy patterns in a direction perpendicular to the semiconductor substrate.

Abstract: An interconnect element is provided. A monolithic dielectric element has a first exposed major surface, a plurality of first recesses extending inwardly from the first major surface, and a second exposed major surface remote from the first major surface, a plurality of second recesses extending inwardly from the second major surface. A plurality of first metal interconnect patterns are embedded in the plurality of first recesses and extend in one or more directions along the first major surface. A plurality of second metal interconnect patterns are embedded in the plurality of second recesses and extend in one or more directions along the second major surface. A plurality of non-hollow metal posts extend through the dielectric element between at least some of the plurality of first metal interconnect patterns and at least some of the plurality of second metal interconnect patterns.

Abstract: An apparatus includes a substrate having a land side having a plurality of contact pads and a die side opposite the land side. The apparatus includes a first die and a second die wherein the first die and second die are embedded within the substrate such that the second die is located between the first die and the land side of the substrate.

Abstract: A microelectronic assembly is provided which includes a first element consisting essentially of at least one of semiconductor or inorganic dielectric material having a surface facing and attached to a major surface of a microelectronic element at which a plurality of conductive pads are exposed, the microelectronic element having active semiconductor devices therein. A first opening extends from an exposed surface of the first element towards the surface attached to the microelectronic element, and a second opening extends from the first opening to a first one of the conductive pads, wherein where the first and second openings meet, interior surfaces of the first and second openings extend at different angles relative to the major surface of the microelectronic element. A conductive element extends within the first and second openings and contacts the at least one conductive pad.

Abstract: A semiconductor device includes: a first insulating film formed on a substrate; a pad embedded in the first insulating film; and a second insulating film that is formed on the first insulating film and has an opening exposing at least part of the pad. The pad includes a plurality of pad interconnects, and an interconnect link is provided to electrically connect adjacent interconnects among the plurality of pad interconnects. The width of the pad interconnects is smaller than the height of the pad interconnects and larger than the width of the interconnect link.

Abstract: A circuit arrangement and method utilize hybrid bonding techniques that combine wafer-wafer bonding processes with chip-chip and/or chip-wafer bonding processes to form a multi-layer semiconductor stack, e.g., by bonding together one or more sub-assemblies formed by wafer-wafer bonding together with other sub-assemblies and/or chips using chip-chip and/or chip-wafer bonding processes. By doing so, the advantages of wafer-wafer bonding techniques, such as higher interconnect densities, may be leveraged with the advantages of chip-chip and chip-wafer bonding techniques, such as mixing and matching chips with different sizes, aspect ratios, and functions.

Abstract: A method is provided for use with an IC device including a stack including a plurality of conductive layers interleaved with a plurality of dielectric layers, for forming interlayer connectors extending from a connector surface to respective conductive layers. The method forms landing areas on the plurality of conductive layers in the stack. The landing areas are without overlying conductive layers in the stack. The method forms etch stop layers over corresponding landing areas. The etch stop layers have thicknesses that correlate with depths of the corresponding landing areas. The method fills over the landing areas and the etch stop layers with a dielectric fill material. Using a patterned etching process, the method forms a plurality of vias extending through the dielectric fill material and the etch stop layers to the landing areas in the plurality of conductive layers.

Abstract: A semiconductor component having improved thermomechanical durability has in a semiconductor substrate at least one cell comprising a first main electrode zone, a second main electrode zone and a control electrode zone lying in between. For making contact with the main electrode zone, at least one metallization layer composed of copper or a copper alloy is provided which is connected to at least one bonding electrode which likewise comprises copper or a copper alloy.

Abstract: A semiconductor device comprises conductive buses and conductive bridges. A respective conductive bridge is conductively coupled to at least two portions of at least one of the conductive buses. At least N plus one (N+1) vias are coupled between every one of the conductive bridges and a respective feature in an integrated circuit when: (1) a width of the respective conductive bridge is less than a width of each of the at least two portions of the at least one of the conductive buses to which the respective conductive bridge is coupled, and (2) a distance along the respective conductive bridge and at least one of the vias is less than a critical distance. N is a number of conductive couplings between the respective one of the conductive bridges and the at least one of the conductive buses.

Abstract: A semiconductor circuit pattern includes an angled conductive pattern having a line portion and a pad portion at an end of the line portion extending normal to the line portion on a first side of the line portion. The pad portion has a width greater than a width of the line portion. A spacing has a first portion adjacent the first side of the pad portion, and a second portion adjacent a second side of the pad portion opposite the first side. The first portion of the spacing has a width greater than the width of the second portion of the spacing.

Abstract: A semiconductor device includes a first insulating layer; a wiring layer formed on a first surface of the first insulating layer and including a first electrode pad; a semiconductor chip; a second insulating layer including a semiconductor chip accommodating portion; a third insulating layer on the second insulating layer; and a passive element including an electrode and formed of an embedded portion and a protruding portion on a second surface of the first insulating layer, wherein an end surface of the embedded portion is coated by the insulating layer, the electrode of the passive element is electrically connected to the wiring layer through a via wiring formed in the insulating layers, the first electrode pad is electrically connected to another semiconductor device through a joining portion, and a protruding amount of the protruding portion is less than a gap between the second surface and the another semiconductor device.

Abstract: According to an aspect of the invention, a semiconductor device includes a substrate having an opening area, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip has a first electrode for high-speed communication and that is disposed around the opening area on the substrate. The second semiconductor chip has a second electrode and third electrode for power and low-speed communication and that is disposed on the first semiconductor chip so that the first electrode is coupled with the second electrode by electrostatic coupling and dielectric coupling, the third electrode facing the opening area.

Abstract: A semiconductor module comprising a plurality of semiconductor chips where at least one semiconductor chip is laterally offset with respect to a second semiconductor chip, and substantially aligned with a third semiconductor chip such that an electrical connection can be made between an electrical contact in the first semiconductor chip and an electrical contact in the third semiconductor chip.

Abstract: One aspect provides an integrated circuit (IC) packaging assembly that comprises a substrate having conductive traces located thereon, wherein the signal traces are located in an IC device region and the power traces are located in a wafer level fan out (WLFO) region located lateral the IC device region. This embodiment further comprises a first IC device located on a first side of the substrate within the IC device region and that contacts the signal traces in the IC device region. A second IC device is located on a second side of the substrate opposite the first side and overlaps the IC device region and the WLFO region. The second IC device contacts a first portion of the signal traces in the IC device region and contacts a first portion of the power traces in the WLFO region.

Abstract: Disclosed herein is a semiconductor package substrate including a base substrate, a mounting member mounted on an upper portion of the base substrate, and an adhesive layer formed between the base substrate and the mounting member, wherein the adhesive layer includes a thermally conductive adhesive and a ductile adhesive formed at the outer circumference of the thermally conductive adhesive.

Abstract: A chip package includes a PCB, a connecting pad fixed on a surface of the PCB and a chip fixed on the connecting pad. The connecting pad includes a first metal film on its surface facing away from the PCB. The chip includes a second metal film formed on its surface opposite to the PCB. The first and the second metal are connected to each other via a eutectic manner.

Abstract: A pad structure is suitable for a circuit carrier or an integrated circuit chip. The pad structure includes an inner pad, a conductive via and an outer pad. The conductive via connects the inner pad. The outer pad connects the conductive via and further connects a conductive ball or a conductive bump. The outer diameter of the outer pad is greater than the outer diameter of the inner pad.

Abstract: A sensor array package can include a sensor disposed on a first side of a substrate. Signal trenches can be formed along the edges of the substrate and a conductive layer can be deposited in the signal trench and can couple to sensor signal pads. Bond wires can be attached to the conductive layers and can be arranged to be below a surface plane of the sensor. The sensor array package can be embedded in a printed circuit board enabling the bond wires to terminate at other conductors within the printed circuit board.

Abstract: Systems and methods for forming an encapsulated device include a hermetic seal which seals an insulating environment between two substrates, one of which supports the device. The hermetic seal is formed by an alloy of two metal layers, one deposited on a first substrate and the other deposited on the second substrate. At least one of the substrates may include a raised feature formed under at least one of the metal layers. The two metals may for an alloy of a predefined stoichiometry in at least two locations on either side of the midpoint of the raised feature. This alloy may have advantageous features in terms of density, mechanical, electrical or physical properties that may improve the hermeticity of the seal, for example.

Abstract: In various embodiments, an assembly having a microstructure is provided, the device includes a cylindrical capture receptacle associated with a substrate, the capture receptacle comprising of a material having an expansion coefficient and comprising alignment structures having alignment projections extending inward from a periphery of the cylindrical capture receptacle. In one embodiment, the projections include a large width alignment projection and plurality of small width alignment projections. A plurality of medium width alignment projections also may be provided. A cylindrical key is associated with the microstructure and has a smaller circumference than the cylindrical capture receptacle and is comprised of a material having an expansion coefficient greater than the expansion coefficient of the cylindrical capture receptacle. The cylindrical key includes alignment receptacles spaced about a periphery of the cylindrical base to receive corresponding alignment projections.

Abstract: A bonding inspection structure is provided. The bonding inspection structure includes at least a elastic bump located on a substrate. At least an opening is formed in the top portion of the elastic bump. An inspection area of the top portion of the elastic bump is larger than an area of the opening.

Abstract: The present disclosure provides an integrated circuit structure that includes a semiconductor substrate having a first region and a second region having an area less than about 10 micron×10 micron; a first material layer over the semiconductor substrate and patterned to have a first circuit feature in the first region and a first mark in the second region; and a second material layer over the first material layer and patterned to have a second circuit feature in the first region and a second mark in the second region. The first mark includes first mark features oriented in a first direction, and second mark features oriented in a second direction perpendicular to the first direction. The second mark includes third mark features oriented in the first direction, and fourth mark features oriented in the second direction.

Abstract: A method and apparatus for direct energy conversion that combines the properties of Type II superconductor thin films, including the Meissner effect to create vortices to control and modulate static flux coupled in a magnetic circuit, where the laws of induction are used to produce an electrical signal without the use of moving armatures. The dynamics of magnetic flux modulation results from suppression of superconductivity and the Meissner effect by external photon irradiation. The apparatus employs a vortex channel based on the Meissner Effect, a laser, a permanent magnet, fiber optics for carrying the laser beam to the vortex channel, and a transformer composed of two separate windings. The transformer windings are arranged in a circuit having a first path through the permanent magnet and a first coil of the transformer windings; and a second path through the permanent magnet, the vortex channel, and the second coil of the transfer windings.

Abstract: A reciprocal vibration type power generator includes a housing, a coil set seat, a power generation coil set surrounding the coil set seat, and a motion block including an outer magnetic member and a columnar magnet. An inner space is formed between the outer magnetic member and a periphery of the columnar magnet to enable reciprocal relative axial movement between the motion block and the coil set seat when the generator is vibrated. A rectifying and charging circuit is connected to the power generation coil set to rectify power induced in the power generation coil set upon movement of the motion block, and to supply the rectified power to a power storage device. The rectifying and charging circuit is also connected to input/output terminals on the generator housing for outputting power to an external device, and for inputting external charging power to the power storage device.

Abstract: An apparatus for harvesting energy from motion of a human or animal body segment and providing the energy to an electrical load is disclosed. The apparatus comprises a generator operatively coupled to the body segment such that particular movement of the body segment causes the generator to output a generator current and to oppose the particular movement of the body segment with a generator torque. An electrical load is coupled to receive the generator current. A control system is operatively connected between the generator and the electrical load and is configured to control the generator torque during the particular movement of the body segment. Corresponding methods are also disclosed.

Abstract: The present application describes techniques for the harvesting of kinetic energy from the movement of people and/or vehicles. A motion converter is discussed which converts linear progression caused by traffic-related impulse forces, to be converted to rotational motion for driving the rotor of an electricity generator. An assembly for harvesting energy including the motion converter and a floor unit are also described.

Abstract: It is disclosed a device which includes an elongated member, and an energy convertor. The elongated member has a base side and a free end. A certain direction is defined by a line connecting centers of the base side and the free end. The free end oscillates relative to the base side, in a response to a mechanical excitation, in a direction substantially perpendicular to the certain direction. The energy convertor converts mechanical energy of the oscillations of the free end to electrical energy. The energy convertor includes a coil attached to the free end, and a permanent magnet tightly fixed to the base side. Mechanical oscillation of the coil relative to the permanent magnet induces a flow of alternate current from the energy convertor. The energy convertor is electrically connected to a current rectifier for rectifying the alternate current, whereas the rectified direct current feeds a battery. The device is installed within a host mobile device, and the base side is fixed to the host mobile device.