Patents Issued in May 27, 2014
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Patent number: 8735940Abstract: There are provided a semiconductor device and a method for manufacturing the same.Type: GrantFiled: December 10, 2010Date of Patent: May 27, 2014Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Woo Chul Jeon, Ki Yeol Park, Young Hwan Park, Jung Hee Lee
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Patent number: 8735941Abstract: Disclosed herein is a nitride based semiconductor device including: a base substrate; an epitaxial growth layer disposed on the base substrate and generating a 2-dimensional electron gas in an inner portion thereof; and an electrode structure disposed on the epitaxial growth layer, wherein the electrode structure includes: a gate electrode; a source electrode disposed at one side of the gate electrode; and a drain electrode disposed at the other side of the gate electrode and having an extension part extended to the inner portion of the epitaxial growth layer to contact the 2-dimensional electron gas.Type: GrantFiled: March 16, 2011Date of Patent: May 27, 2014Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Kiyeol Park, Woochul Jeon, Younghwan Park
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Patent number: 8735942Abstract: An i-GaN layer (electron transit layer), an n-GaN layer (compound semiconductor layer) formed over the i-GaN layer (electron transit layer), and a source electrode, a drain electrode and a gate electrode formed over the n-GaN layer (compound semiconductor layer) are provided. A recess portion is formed inside an area between the source electrode and the drain electrode of the n-GaN layer (compound semiconductor layer) and at a portion separating from the gate electrode.Type: GrantFiled: February 15, 2012Date of Patent: May 27, 2014Assignee: Fujitsu LimitedInventors: Tadahiro Imada, Atsushi Yamada
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Patent number: 8735943Abstract: A semiconductor device includes a semiconductor layer, an insulating film, a gate electrode, a drain electrode, and a source electrode. The semiconductor layer includes an active layer and is formed on a semi-insulating semiconductor substrate, and a tapered recess area having an inclined sidewall is formed on a surface of the semiconductor layer. The insulating film is formed on the semiconductor layer and has a through hole for exposing the recess area. The through hole has a tapered sidewall which is inclined at an angle smaller than the sidewall of the recess area. The gate electrode is formed so as to fill the recess area and the through hole. The drain electrode and the source electrode are formed at positions on opposite sides of the recess area on the semiconductor layer.Type: GrantFiled: August 30, 2012Date of Patent: May 27, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Ryota Senda, Hisao Kawasaki
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Patent number: 8735944Abstract: A semiconductor device includes a cross-coupled transistor configuration formed by first and second PMOS transistors defined over first and second p-type diffusion regions, and by first and second NMOS transistors defined over first and second n-type diffusion regions, with each diffusion region electrically connected to a common node. Gate electrodes of the PMOS and NMOS transistors are formed by conductive features that are each defined within any one gate level channel. At least a portion of the first p-type diffusion region and at least a portion of the second p-type diffusion region are formed over a first common line of extent that extends perpendicular to the first parallel direction. Also, at least a portion of the first n-type diffusion region and at least a portion of the second n-type diffusion region are formed over a second common line of extent that extends perpendicular to the first parallel direction.Type: GrantFiled: April 5, 2010Date of Patent: May 27, 2014Assignee: Tela Innovations, Inc.Inventors: Scott T. Becker, Jim Mali, Carole Lambert
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Patent number: 8735945Abstract: A semiconductor device includes a transistor array including a plurality of transistors each having a gate electrode extended in a first direction, the plurality of transistors being arranged in a second direction intersecting the first direction, and a pad electrode arranged in the first direction of the transistor array and electrically connected to source regions of the plurality of transistors.Type: GrantFiled: September 2, 2011Date of Patent: May 27, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Masashi Shima, Kaoru Saigoh, Nobuhiro Misawa, Takao Sasaki
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Patent number: 8735946Abstract: Embodiments of the invention relate to substrates comprising a base wafer, an insulating layer and a top semiconductor layer, wherein the insulating layer comprises at least a zone wherein a density of charges is in absolute value higher than 1010 charges/cm2. The invention also relates to processes for making such substrates.Type: GrantFiled: September 16, 2013Date of Patent: May 27, 2014Assignee: SoitecInventors: Mohamad A Shaheen, Frederic Allibert, Gweltaz Gaudin, Fabrice Lallement, Didier Landru, Karine Landry, Carlos Mazure
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Patent number: 8735947Abstract: Non-volatile switches and methods for making the same include a gate material formed in a recess of a substrate; a flexible conductive element disposed above the gate material, separated from the gate material by a gap, where the flexible conductive element is supported on at least two points across the gap, and where a voltage above a gate threshold voltage causes a deformation in the flexible conductive element such that the flexible conductive element comes into contact with a drain in the substrate, thereby closing a circuit between the drain and a source terminal. The gap separating the flexible conductive element and the gate material is sized to create a negative threshold voltage at the gate material for opening the circuit.Type: GrantFiled: December 4, 2012Date of Patent: May 27, 2014Assignee: International Business Machines CorporationInventors: Dechao Guo, Shu-Jen Han, Fei Liu, Keith Kwong Hon Wong, Jun Yuan
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Patent number: 8735948Abstract: A semiconductor device according to the present invention includes: a semiconductor substrate; a source region formed in a top layer portion of the semiconductor substrate; a drain region formed in the top layer portion of the semiconductor substrate and spaced apart from the source region; a gate electrode formed on the semiconductor substrate and opposing to an interval between the source region and the drain region; a wiring formed on the semiconductor substrate and connected to the source region, the drain region, or the gate electrode; and a MEMS sensor disposed on the semiconductor substrate. The MEMS sensor includes: a thin film first electrode made of the same material as the gate electrode and formed in the same layer as the gate electrode; and a second electrode made of the same material as the wiring, formed in the same layer as the wiring, and spaced apart from the first electrode at a side opposite to the semiconductor substrate side of the first electrode.Type: GrantFiled: November 13, 2008Date of Patent: May 27, 2014Assignee: Rohm Co., Ltd.Inventor: Goro Nakatani
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Patent number: 8735949Abstract: According to one embodiment, a junction type field effect transistor includes a first conductive type semiconductor substrate, a first conductive type drift layer, a second conductive type gate region, a first conductive type channel layer, a first conductive type source region, a source electrode, a drain electrode, a second conductive type gate contact layer, and a gate electrode. The drift layer is provided on a first main surface of the semiconductor substrate. The gate region is provided on a surface of the drift layer. The channel layer is provided on the drift layer and the gate region. The source region is provided on a surface of the channel layer to face the gate region, and has an impurity concentration higher than the channel layer. The source electrode is provided on the channel layer with Schottky contact and on the source region with ohmic contact.Type: GrantFiled: August 31, 2012Date of Patent: May 27, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Kohei Morizuka
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Patent number: 8735950Abstract: A device includes a semiconductor substrate, first and second electrodes supported by the semiconductor substrate, laterally spaced from one another, and disposed at a surface of the semiconductor substrate to form an Ohmic contact and a Schottky junction, respectively. The device further includes a conduction path region in the semiconductor substrate, having a first conductivity type, and disposed along a conduction path between the first and second electrodes, a buried region in the semiconductor substrate having a second conductivity type and disposed below the conduction path region, and a device isolating region electrically coupled to the buried region, having the second conductivity type, and defining a lateral boundary of the device. The device isolating region is electrically coupled to the second electrode such that a voltage at the second electrode during operation is applied to the buried region to deplete the conduction path region.Type: GrantFiled: September 6, 2012Date of Patent: May 27, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Weize Chen, Xin Lin, Patrice M. Parris
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Patent number: 8735951Abstract: A semiconductor device includes an isolation pattern disposed on a substrate, the isolation pattern defining an active part, a gate pattern crossing the active part on the substrate, the gate pattern including a dielectric pattern and a first conductive pattern, and the dielectric pattern being between the active part and the first conductive pattern, a pair of doping regions in the active part adjacent to side walls of the gate pattern, the gate pattern being between the pair of doping regions, and a diffusion barrier element injection region disposed in an upper region of the active part.Type: GrantFiled: December 16, 2011Date of Patent: May 27, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Hajin Lim, Moonhan Park, Jinho Do, Moonkyun Song
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Patent number: 8735952Abstract: A solid-state imaging device is provided. The solid-state imaging device includes an imaging region having a plurality of pixels arranged on a semiconductor substrate, in which each of the pixels includes a photoelectric converting portion and a charge converting portion for converting a charge generated by photoelectric conversion into a pixel signal and blooming is suppressed by controlling a substrate voltage of the semiconductor substrate.Type: GrantFiled: July 17, 2007Date of Patent: May 27, 2014Assignee: Sony CorporationInventors: Maki Sato, Yoshiharu Kudoh
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Patent number: 8735953Abstract: An image sensor comprising at least: CMOS-type photodiodes and transistors produced in a semiconductor layer having a thickness of between approximately 1 ?m and 1.5 ?m, a dielectric layer in which electrical interconnect layers are made, which are electrically connected to one another and/or to the CMOS photodiodes and/or transistors, said dielectric layer being arranged against a first face of the semiconductor layer opposite a second face of the semiconductor layer through which the light received by the sensor from the exterior is intended to enter, light-reflecting means arranged in the dielectric layer, opposite the photodiodes, and capable of reflecting at least a portion of the light received by the sensor towards the photodiodes.Type: GrantFiled: September 1, 2009Date of Patent: May 27, 2014Assignee: Commissariat a l'Energie AtomiqueInventors: Pierre Gidon, Yvon Cazaux
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Patent number: 8735954Abstract: A semiconductor device includes a semiconductor substrate; a first insulating film that is formed over the semiconductor substrate; a capacitor that is formed over the first insulating film and is formed by sequentially stacking a lower electrode, a capacitor dielectric film, and an upper electrode; a second insulating film that is formed over the capacitor and has a hole including the entire region of the upper electrode in plan view; and a conductor plug that is formed in the hole and contains tungsten.Type: GrantFiled: November 28, 2012Date of Patent: May 27, 2014Assignee: Fujitsu Semiconductor LimitedInventor: Naoya Sashida
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Patent number: 8735955Abstract: A grounding system for a semiconductor module of a variable speed drive includes a first conductive layer, a second conductive layer; a substrate disposed between the first conductive layer and the second conductive layer; and a base attached to the second conductive layer, the base being connected to earth ground via a grounding harness. The first conductive layer is in electrical contact with the semiconductor module and the substrate, and electrically insulated from the second conductive layer by the substrate. The second conductive layer is in electrical contact with the substrate and disposed between the substrate and the base in electrical communication with an earth ground. The first conductive layer, the substrate and the second conductive layer form a capacitance path between the semiconductor module and the base as well as electrical conductors and the base for reduction circulating currents within the semiconductor module.Type: GrantFiled: July 8, 2009Date of Patent: May 27, 2014Assignee: Johnson Controls Technology CompanyInventors: Konstantin Borisov, Michael S. Todd, Shreesha Adiga-Manoor, Ivan Jadric
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Patent number: 8735956Abstract: A semiconductor device and a method for manufacturing the same are disclosed. An additional spacer is formed at a lateral surface of an upper part of the bit line so that the distance of insulation films between a storage node and a neighboring storage node contact plug is increased. Accordingly, the distance between the storage node and the neighboring storage node contact is guaranteed and a bridge failure is prevented.Type: GrantFiled: January 10, 2012Date of Patent: May 27, 2014Assignee: Hynix Semiconductor Inc.Inventor: Un Hee Lee
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Patent number: 8735957Abstract: Consistent with an example embodiment, there is a package that includes a first voltage terminal, and a second voltage terminal, a first die including a first MOSFET having a drain region electrically connected to the first voltage terminal and further having a source region, A second die is adjacent to the first die, the second die includes a second MOSFET having a drain region electrically connected to the source region of the first MOSFET and having a source region electrically connected to the second voltage terminal. The semiconductor package further includes a vertical capacitor having a first plate electrically connected to the drain region of the first MOSFET and a second plate electrically connected to the source region of the second MOSFET and the second plate is electrically insulated from the first plate by a dielectric material. The capacitor is integrated on the first die or the second die.Type: GrantFiled: July 16, 2012Date of Patent: May 27, 2014Assignee: NXP B.V.Inventor: Phil Rutter
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Patent number: 8735958Abstract: A blocking semiconductor layer minimizes penetration of implant species into a semiconductor layer beneath the blocking semiconductor layer. The blocking semiconductor layer may have grains with relatively fine or small grain sizes and/or may have a dopant in a relatively low concentration to minimize penetration of implant species into the semiconductor layer beneath the blocking semiconductor layer.Type: GrantFiled: December 27, 2012Date of Patent: May 27, 2014Assignee: Macronix International Co., Ltd.Inventors: Chun Ling Chiang, Wen-Ming Chang, Chun-Ming Cheng, Ling-Wuu Yang, Kuang-Chao Chen
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Patent number: 8735959Abstract: A device includes a substrate; a shallow trench isolation (STI) region located in the substrate, the STI region comprising an STI material, and further comprising a recess in the STI material, the recess having a bottom and sides; a floating gate, wherein a portion of the floating gate is located on a side of the recess in the STI region and is separated from the substrate by a portion of the STI material; and a gate dielectric layer located over the floating gate, and a control gate located over the gate dielectric layer, wherein a portion of the control gate is located in the recess.Type: GrantFiled: November 14, 2013Date of Patent: May 27, 2014Assignee: International Business Machines CorporationInventor: Erwan Dornel
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Patent number: 8735960Abstract: An ultraviolet light absorbent silicon oxynitride layer overlies a memory cell including a pair of source/drains, a gate insulator, a floating gate, a dielectric layer, and a control gate. A conductor is disposed through the silicon oxynitride layer for electrical connection to the control gate, and another conductor is disposed through the silicon oxynitride layer for electrical connection to a source/drain.Type: GrantFiled: November 17, 2008Date of Patent: May 27, 2014Assignee: Spansion LLCInventors: Minh Q. Tran, Minh-Van Ngo, Alexander H. Nickel, Sung Jin Kim, Simon Chan, Ning Cheng
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Patent number: 8735961Abstract: A non-volatile memory device having a string of a plurality of memory cells that are serially coupled, wherein the string of memory cells includes a plurality of second channels of a pillar type, a first channel coupling lower end portions of the plurality of the second channels with each other, and a plurality of control gate electrodes surrounding the plurality of the second channels.Type: GrantFiled: September 14, 2010Date of Patent: May 27, 2014Assignee: SK Hynix Inc.Inventor: Han-Soo Joo
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Patent number: 8735962Abstract: A semiconductor device according to an embodiment of the present invention includes a vertical channel layer protruding upward from a semiconductor substrate, a tunnel insulating layer covering a sidewall of the vertical channel layer, a plurality of floating gates separated from each other and stacked one upon another along the vertical channel layer, and surrounding the vertical channel layer with the tunnel insulating layer interposed therebetween, a plurality of control gates enclosing the plurality of floating gates, respectively, and an interlayer insulating layer provided between the plurality of control gates.Type: GrantFiled: August 30, 2012Date of Patent: May 27, 2014Assignee: SK Hynix Inc.Inventors: Sung Jin Whang, Dong Sun Sheen, Seung Ho Pyi, Min Soo Kim
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Patent number: 8735963Abstract: A semiconductor device includes a semiconductor substrate; a tunneling layer over the semiconductor substrate, wherein the tunneling layer has a first conduction band; a storage layer over the tunneling layer, wherein the storage layer has a second conduction band; a blocking layer over the storage layer, wherein the blocking layer has a third conduction band; a gate electrode over the blocking layer; and at least one of a first leakage-inhibition layer and a second leakage-inhibition layer. The first leakage-inhibition layer is between the tunneling layer and the storage layer, and has a fourth conduction band lower than the first conduction band. The second leakage-inhibition layer is between the blocking layer and the gate electrode, and has a fifth conduction band lower than the third conduction band.Type: GrantFiled: July 7, 2008Date of Patent: May 27, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Tsong Wang, Tong-Chern Ong, Albert Chin, Hsueh-Jen Yang
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Patent number: 8735964Abstract: An apparatus is provided which includes an array of impurity ions disposed in an insulating region, a semiconductor region adjacent to the insulating region, an array of electrometers arranged to detect charge carriers in the semiconductor region and an array of sets of at least one control gate configured to apply an electric field to the insulating region and semiconductor region. Each control gate is operable to cause at least one charge carrier in the semiconducting material region to bind to the impurity ion without the at least one charge carrier leaving the semiconductor material region. The electrometers are operable to detect whether the at least one charge carrier is bound to the impurity ion.Type: GrantFiled: October 12, 2010Date of Patent: May 27, 2014Assignee: Hitachi, Ltd.Inventor: Thierry Ferrus
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Patent number: 8735965Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, an electrode layer provided above the substrate, a first insulating layer provided on the electrode layer, a stacked body provided on the insulating layer, a memory film, a channel body layer, a channel body connecting portion and a second insulating layer. The stacked body has a plurality of conductive layers and a plurality of insulating film alternately stacked on each other. The memory film is provided on a sidewall of each of a pair of holes penetrating the stacked body in a direction of stacking the stacked body. The channel body layer is provided on an inner side of the memory film in each of the pair of the holes.Type: GrantFiled: March 15, 2012Date of Patent: May 27, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hanae Ishihara, Mitsuru Sato, Toru Matsuda
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Patent number: 8735966Abstract: First and second memory cells have first and second channels, first and second tunnel insulating films, first and second charge storage layers formed of an insulating film, first and second block insulating films, and first and second gate electrodes. A first select transistor has a third channel, a first gate insulating film, and a first gate electrode. The first channel includes a first-conductivity-type region and a second-conductivity-type region which is formed on at least a part of the first-conductivity-type region and whose conductivity type is opposite to the first conductivity type. The third channel includes the first-conductivity-type region and the second-conductivity-type region formed on the first-conductivity-type region. The number of data stored in the first memory cell is smaller than that of data stored in the second memory cell.Type: GrantFiled: October 17, 2011Date of Patent: May 27, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Toshitake Yaegashi
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Patent number: 8735967Abstract: A semiconductor memory device includes a lower select transistor formed within a semiconductor substrate, memory cells stacked over the lower select transistors, and an upper select transistor formed over the memory cells.Type: GrantFiled: February 15, 2012Date of Patent: May 27, 2014Assignee: SK Hynix Inc.Inventors: Se Yun Lim, Eun Seok Choi
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Patent number: 8735968Abstract: The present technology discloses a semiconductor die integrating a MOSFET device and a Schottky diode. The semiconductor die comprises a MOSFET area comprising the active region of MOSFET, a Schottky diode area comprising the active region of Schottky diode, and a termination area comprising termination structures. Wherein the Schottky diode area is placed between the MOSFET area and the termination area such that the Schottky diode area surrounds the MOSFET area.Type: GrantFiled: December 28, 2010Date of Patent: May 27, 2014Assignee: Monolithic Power Systems, Inc.Inventors: Tiesheng Li, Lei Zhang
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Patent number: 8735969Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a stacked structure, a plurality of first conductive blocks, a plurality of first conductive layers, a plurality of second conductive layers, and a plurality of conductive damascene structures. The stacked structure, comprising a plurality of conductive strips and a plurality of insulating strips, is formed on a substrate, and the conductive strips and the insulating strips are interlaced. The first conductive blocks are formed on the stacked structure. The first conductive layers and the second conductive layers are formed on two sidewalls of the stacked structure, respectively. The conductive damascene structures are formed on two sides of the stacked structure, wherein each of the first conductive blocks is electrically connected to each of the conductive damascene structures via each of the first conductive strips and each of the second conductive strips.Type: GrantFiled: November 7, 2012Date of Patent: May 27, 2014Assignee: Macronix International Co., Ltd.Inventors: Erh-Kun Lai, Yen-Hao Shih, Shih-Chang Tsai
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Patent number: 8735970Abstract: A semiconductor device is provided which includes: semiconductor pillars which include impurity diffused layers, each semiconductor pillar having a width which allows full depletion of a semiconductor forming each semiconductor pillar, the impurity diffused layers being electrically connected to each other; and a common gate section which covers side faces of the pillars.Type: GrantFiled: September 23, 2008Date of Patent: May 27, 2014Inventor: Yoshihiro Takaishi
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Patent number: 8735971Abstract: A SGT production method includes a step of forming first and second fin-shaped silicon layers, forming a first insulating film, and forming first and second pillar-shaped silicon layers; a step of forming diffusion layers by implanting an impurity into upper portions of the first and second pillar-shaped silicon layers, upper portions of the first and second fin-shaped silicon layers, and lower portions of the first and second pillar-shaped silicon layers; a step of forming a gate insulating film and first and second polysilicon gate electrodes; a step of forming a silicide in upper portions of the diffusion layers formed in the upper portions of the first and second fin-shaped silicon layers; and a step of depositing an interlayer insulating film, exposing and etching the first and second polysilicon gate electrodes, then depositing a metal, and forming first and second metal gate electrodes.Type: GrantFiled: November 16, 2012Date of Patent: May 27, 2014Assignee: Unisantis Electronics Singapore Pte. Ltd.Inventors: Fujio Masuoka, Hiroki Nakamura
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Patent number: 8735972Abstract: An SRAM cell and a method of forming an SRAM cell. The SRAM cell includes a first pass gate field effect transistor (FET) and a first pull-down FET sharing a first common source/drain (S/D) and a first pull-up FET having first and second S/Ds; a second pass gate FET and a second pull-down FET sharing a second common S/D and a second pull-up FET having first and second S/Ds; a first gate electrode common to the first pull-down FET and the first pull-up FET and physically and electrically contacting the first S/D of the first pull-up FET; a second gate electrode of the first pull-up FET; a third gate electrode common to the second pull-down FET and the second pull-up FET and physically and electrically contacting the first S/D of the second pull-up FET; and a fourth gate electrode of the first pull-up FET.Type: GrantFiled: September 8, 2011Date of Patent: May 27, 2014Assignee: International Business Machines CorporationInventors: Brent A. Anderson, Edward J. Nowak, Jed H. Rankin
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Patent number: 8735973Abstract: The embodiments of the present disclosure disclose a trench-gate MOSFET device and the method for making the trench-gate MOSFET device. The trench-gate MOSFET device comprises a curving dopant profile formed between the body region and the epitaxial layer so that the portion of the body region under the source metal contact has a smaller vertical thickness than the other portion of the body region. The trench-gate MOSFET device in accordance with the embodiments of the present disclosure has improved UIS capability compared with the traditional trench-gate MOSFET device.Type: GrantFiled: May 2, 2012Date of Patent: May 27, 2014Assignee: Chengdu Monolithic Power Systems Co., Ltd.Inventors: Lei Zhang, Donald Ray Disney, Tiesheng Li, Rongyao Ma
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Patent number: 8735974Abstract: An object of the present application is to reduce the gate capacitance without lowering the withstand voltage of a semiconductor device and prevent generation of a leak current between main electrodes even when an oxide film is formed poorly. A semiconductor device of the present application comprises a gate electrode and a dummy gate electrode. The gate electrode is insulated from an emitter electrode and faces a part of a body region via an insulating film, the part of the body region separating a drift region and an emitter region from each other. The dummy gate electrode is electrically connected with the emitter electrode and is connected with the drift region and the body region via the insulating film. At least a part of the dummy gate electrode comprises a first conductive region of the same type as the drift region. In the dummy gate electrode, the emitter electrode is separated from the drift region by the first conductive region.Type: GrantFiled: February 16, 2010Date of Patent: May 27, 2014Assignee: Toyota Jidosha Kabushiki KaishaInventor: Masaru Senoo
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Patent number: 8735975Abstract: A method and structures are provided for implementing metal via gate node high performance stacked vertical transistors in a back end of line (BEOL) on a semiconductor System on Chip (SoC). The high performance stacked vertical transistors include a pair of stacked vertical field effect transistors (FETs) formed by polycrystalline depositions in a stack between planes of a respective global signal routing wire. A channel length of each of the stacked vertical FETs is delineated by the polycrystalline depositions with sequential source deposition, channel deposition and drain deposition; and a wire via defines the gate node.Type: GrantFiled: January 9, 2013Date of Patent: May 27, 2014Assignee: International Business Machines CorporationInventors: Karl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann, Kelly L. Williams
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Patent number: 8735976Abstract: A Thin Film Transistor-Liquid Crystal Display (TFT-LCD) array substrate is presented which includes a gate line, a data line, and a pixel electrode. The pixel electrode is disposed in a pixel region defined by the intersection between the gate line and the data line. In the pixel region, a partition groove for forming a pixel electrode pattern is provided at the periphery of the pixel electrode.Type: GrantFiled: February 26, 2013Date of Patent: May 27, 2014Assignee: Beijing Boe Optoelectronics Technology Co., Ltd.Inventors: Hongxi Xiao, Jae Yun Jung, Zuhong Liu, Taek Ho Hong, Jeong Hun Rhee
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Patent number: 8735977Abstract: A semiconductor device includes active regions defined by a device isolation layer, gates disposed in the active regions of cell channel regions, word lines disposed on the gates and extending along a first direction, and gate contacts configured to connect the gates to the word lines. The gates have a box shape which extends over two active regions.Type: GrantFiled: December 18, 2012Date of Patent: May 27, 2014Assignee: SK Hynix Inc.Inventor: Dong Min Lee
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Patent number: 8735978Abstract: Embodiments of a semiconductor device include a semiconductor substrate having a first surface and a second surface opposed to the first surface, a trench formed in the semiconductor substrate and extending from the first surface partially through the semiconductor substrate, a gate electrode material deposited in the trench, and a void cavity in the semiconductor substrate between the gate electrode material and the second surface. A portion of the semiconductor substrate is located between the void cavity and the second surface.Type: GrantFiled: February 24, 2011Date of Patent: May 27, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Ljubo Radic, Edouard D. de Frésart
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Patent number: 8735979Abstract: Mutual triggering of electrostatic discharge (ESD) fingers is improved by creating a base contact in each individual finger and connecting all of these base contacts in parallel. The local base contact in each ESD finger is located at a position where the base voltage significantly increases when the ESD current increases. Thus when an ESD finger is triggered its local base voltage will tend to significantly increase. Since all of the ESD finger bases are connected in parallel this local voltage increase will forward bias the base-emitter junctions of the other ESD fingers, thus triggering them all. By sharing the triggering current from the fastest ESD finger with the slower ones ensures that all ESD fingers are triggered during an ESD event.Type: GrantFiled: July 19, 2012Date of Patent: May 27, 2014Assignee: Microchip Technology IncorporatedInventors: Philippe Deval, Marija Fernandez, Patrick Besseux
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Patent number: 8735980Abstract: A semiconductor structure, which serves as the core of a semiconductor fabrication platform, has a combination of empty-well regions and filled-well regions variously used by electronic elements, particularly insulated-gate field-effect transistors (“IGFETs”), to achieve desired electronic characteristics. A relatively small amount of semiconductor well dopant is near the top of an empty well. A considerable amount of semiconductor well dopant is near the top of a filled well. Some IGFETs (100, 102, 112, 114, 124, and 126) utilize empty wells (180, 182, 192, 194, 204, and 206) in achieving desired transistor characteristics. Other IGFETs (108, 110, 116, 118, 120, and 122) utilize filled wells (188, 190, 196, 198, 200, and 202) in achieving desired transistor characteristics.Type: GrantFiled: November 6, 2012Date of Patent: May 27, 2014Assignee: National Semiconductor CorporationInventors: Constantin Bulucea, Sandeep Bahl, William French, Jeng-Jiun Yang, Donald Archer, David C. Parker, Prasad Chaparala
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Patent number: 8735981Abstract: Disclosed is a transistor component having a control structure with a channel control layer of an amorphous semiconductor insulating material extending in a current flow direction along a channel zone.Type: GrantFiled: June 17, 2009Date of Patent: May 27, 2014Assignee: Infineon Technologies Austria AGInventor: Gerhard Schmidt
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Patent number: 8735982Abstract: A superjunction semiconductor device is disclosed which has, in the active section, a first alternating-conductivity-type layer which makes a current flow in the ON-state of the device and sustains a bias voltage in the OFF-state of the device. There is a second alternating-conductivity-type layer in a edge-termination section surrounding the active section. The width of a region of a second conductivity type in the second alternating-conductivity-type layer becomes narrower at a predetermined rate from the edge on the active section side toward the edge of the edge termination section. The superjunction semiconductor device facilitates manufacturing the edge-termination section which exhibits a high breakdown voltage and a high reliability for breakdown voltage through a process that exhibits a high mass-productivity.Type: GrantFiled: November 7, 2011Date of Patent: May 27, 2014Assignee: Fuji Electric Co., Ltd.Inventor: Yasuhiko Onishi
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Patent number: 8735983Abstract: Metal-oxide-semiconductor transistors are provided. A metal-oxide-semiconductor transistor may be formed on a semiconductor substrate. Source and drain regions may be formed in the substrate. A gate insulator such as a high-K dielectric may be formed between the source and drain regions. A gate may be formed from multiple gate conductors. The gate conductors may be metals with different workfunctions. A first of the gate conductors may form a pair of edge gate conductors that are adjacent to dielectric spacers. An opening between the edge gate conductors may be filled with the second gate conductor to form a center gate conductor. A self-aligned gate formation process may be used in fabricating the metal-oxide-semiconductor transistor.Type: GrantFiled: November 26, 2008Date of Patent: May 27, 2014Assignee: Altera CorporationInventors: Jun Liu, Albert Ratnakumar, Qi Xiang, Jeffrey Xiaoqi Tung
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Patent number: 8735984Abstract: FinFET devices are formed with body contact structures enabling the fabrication of such devices having different gate threshold voltages (Vt). A body contact layer is formed to contact the gate electrode (contact) enabling a forward body bias and a reduction in Vt. Two example methods of fabrication (and resulting structures) are provided. In one method, the gate electrode (silicon-based) and body contact layer (silicon) are connected by growing epitaxy which merges the two structures forming electrical contact. In another method, a via is formed that intersects with the gate electrode (suitable conductive material) and body contact layer and is filled with conductive material to electrically connect the two structures. As a result, various FinFETs with different Vt can be fabricated for different applications.Type: GrantFiled: July 6, 2010Date of Patent: May 27, 2014Assignee: Globalfoundries Singapore PTE, Ltd.Inventors: Chunshan Yin, Kian Ming Tan, Jae Gon Lee
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Patent number: 8735985Abstract: A graphene substrate is doped with one or more functional groups to form an electronic device.Type: GrantFiled: December 13, 2012Date of Patent: May 27, 2014Assignee: The Invention Science Fund I, LLCInventors: Jeffrey A. Bowers, Roderick A. Hyde, Muriel Y. Ishikawa, Jordin T. Kare, Clarence T. Tegreene, Tatsushi Toyokuni, Richard N. Zare
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Patent number: 8735986Abstract: A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices.Type: GrantFiled: December 6, 2011Date of Patent: May 27, 2014Assignee: International Business Machines CorporationInventors: Alan B. Botula, Renata Camillo-Castillo, James S. Dunn, Jeffrey P. Gambino, Douglas B. Hershberger, Alvin J. Joseph, Robert M. Rassel, Mark E. Stidham
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Patent number: 8735987Abstract: A semiconductor device includes a substrate having a semiconducting surface having formed therein a first active region and a second active region, where the first active region consists of a substantially undoped layer at the surface and a highly doped screening layer of a first conductivity type beneath the first substantially undoped layer, and the second active region consists of a second substantially undoped layer at the surface and a second highly doped screening layer of a second conductivity type beneath the second substantially undoped layer. The semiconductor device also includes a gate stack formed in each of the first active region and the second active region consists of at least one gate dielectric layer and a layer of a metal, where the metal has a workfunction that is substantially midgap with respect to the semiconducting surface.Type: GrantFiled: June 6, 2012Date of Patent: May 27, 2014Assignee: Suvolta, Inc.Inventors: Thomas Hoffmann, Scott E. Thompson, Pushkar Ranade
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Patent number: 8735988Abstract: The present disclosure describes a semiconductor device including a semiconductor substrate and a gate stack disposed on the semiconductor substrate. A first spacer element is disposed on the substrate abutting the first gate stack. In an embodiment, the first spacer element includes silicon nitride. A second spacer element is adjacent the first spacer element. In an embodiment, the second spacer element includes silicon oxide. A raised source and a first raised drain is provided laterally contacting sidewalls of the second spacer element. In an embodiment, a contact directly interfaces with the second spacer element.Type: GrantFiled: April 26, 2013Date of Patent: May 27, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yun Jing Lin, Wei-Han Fan, Yu-Hsien Lin, Yimin Huang
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Patent number: 8735989Abstract: According to one embodiment, a semiconductor device includes a main element and a sense element. The main element is connected between a collector terminal and an emitter terminal. The main element has an insulated gate bipolar transistor structure. The sense element is connected in parallel with the main element via a sense resistor between the collector terminal and the emitter terminal. The sense element has an insulated gate bipolar transistor structure with a feedback capacitance larger than a feedback capacitance of the main element.Type: GrantFiled: November 7, 2011Date of Patent: May 27, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Kenichi Matsushita