Abstract: The invention provides a porous sensor and sensing methods that use a porous sensor with a porous nanostructure having an optical response and having a portion of the porous nanostructure filled with a fiducial marker that is non-reactive to an analyte of interest. In a preferred sensing method, reflectance spectra from both the fiducial marker and reactive portions of the porous structure are acquired simultaneously. The fiducial marker provides an internal reference that permits compensation for humidity, as well as off angle measurements. In addition, simple visual observations can reveal the presence of an analyte, including human observations.

Abstract: A method for measuring bromate ion is provided that provides high-sensitivity measurement results more simply and more quickly than conventional bromate ion measurement methods. A fluorescent substance that is quenched by coexistence with bromate ions is added to a sample 130 and the fluorescence intensity of the fluorescent substance after quenching is measured, the measured fluorescence intensity being subtracted from the fluorescence intensity of a standard sample containing no bromate ions to calculated the fluorescence intensity difference. The bromate ion concentration is calculated from the calculated fluorescence intensity difference, using a pre-determined calibration line between the fluorescence intensity difference and the bromate ion concentration.

Abstract: The invention relates to a method of monitoring a concentration of a halogenated disinfectant in swimming pools or the like and a device for implementing the method. The method comprises: a liquid-injection step of injecting the liquid to be analyzed into the analysis chamber; a reagent-injection step of injecting a reagent into the analysis chamber; a measurement step of measuring the liquid/reagent mixture by colorimetry; a processing step of processing the measurement in relation to data; and a verification step of verifying the colorimetric measurement when the measurement corresponds to the reagent being bleached or to an absence of reaction color.

Abstract: A subject of the invention is a kit for the identification, characterization and quantification by a single detection of the carboxylic, thiol and amine functional groups contained in a sample.

Abstract: Provided herein are batch methods and devices for enriching trace quantities of impurities in gaseous mixtures, such as hydrogen fuel. The methods and devices rely on concentrating impurities using hydrogen transport membranes wherein the time period for concentrating the sample is calculated on the basis of optimized membrane characteristics, comprising its thickness and permeance, with optimization of temperature, and wherein the enrichment of trace impurities is proportional to the pressure ratio Phi/Plo and the volume ratio V1/V2, with following detection of the impurities using commonly-available detection methods.

Abstract: Methods and apparatuses for analyzing proteins and other biological materials and xenobiotics within a sample. A specimen is generated, which may include an energy absorbent matrix. The specimen is struck with laser beams such that the specimen releases proteins. The atomic mass of the released proteins over a range of atomic masses is measured. An atomic mass window of interest within the range of atomic masses is analyzed to determine the spatial arrangement of specific proteins within the sample, and those specific proteins are identified as a function of the spatial arrangement. By analyzing the proteins, one may monitor and classify disease within a sample.

Abstract: A microfluidic processing unit for the automated processing of liquid samples and method thereof are disclosed. In one embodiment, the unit comprises first and second main channels connected to a pump for generating a negative or positive pressure therein; a sample channel which supplies a liquid sample is connectable to a sample vessel containing the liquid sample, the sample channel communicates with the first main channel and is equipped with an on/off valve; one or more reagent channels for supplying one or more reagents, the reagent channels being connectable to reagent vessels containing reagents for reacting with the liquid samples, each of the reagent channels communicating with the first or second main channel and being equipped with an on/off valve; and a reaction chamber for reacting a sample and reagent, the reaction chamber being connected to the first and second main channels via at least one on/off valve.

Abstract: The invention provides a method of measuring the affinity of first and second biomolecules in which a first biomolecule is tethered by a first tether portion having a first tether portion length and a second biomolecule is tethered by a second tether portion having a second tether portion length, the method comprising determining binding of adjacent first and second biomolecules to each other, varying at least one of the first and second tether lengths and determining binding of the first and second biomolecules. The invention also provides apparatus suitable for use in the method of the invention.

Abstract: In a chromatography quantitative measuring apparatus, a beam applied from a light source to a chromatography test strip is formed into an elliptical shape by an optical means such as a cylindrical lens, a variation in absorbance that accompanies elution of a marker regent is detected while the elliptical beam is applied between a marker reagent hold part and a detection part, and a measurement is automatically started in a prescribed period of time since the detection of variation. According to the chromatography quantitative measuring apparatus so configured, non-uniform coloration is reduced by shaping the beam elliptically with the optical means, whereby the accuracy of quantitative analysis is enhanced, and the apparatus can be operated easily.

Abstract: A method for determining the amount of NT-proBNP in blood samples from animals. The method includes detecting degradation products of NT-proBNP by various methods, including using antibodies, kits and device.

Abstract: An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for at least partially enclosing a FeCap array with hydrogen barrier walls and a hydrogen barrier top plate.

Abstract: A production method of the present disclosure includes: a first step of preparing a multi-layer graphene, and an iron oxide that is a ferromagnetic material contacting the graphene and containing Fe3O4; and a second step of applying a voltage or a current between the graphene and the iron oxide with an electric potential of the graphene being positive relative to that of the iron oxide, so as to oxidize a part of the graphene or oxidize a part of the graphene and a part of Fe3O4, and thus to form a barrier layer composed of oxidized graphene or of oxidized graphene and Fe2O3 between the graphene and the iron oxide, and thereby forming a spin injection electrode that includes the graphene, the iron oxide, and the barrier layer located at an interface between the graphene and the iron oxide, and that allows spins to be injected into the graphene from the iron oxide via the barrier layer.

Abstract: A wafer inspection method comprises imaging a full surface of the wafer at an imaging resolution insufficient to resolve individual microstructures which are repetitively arranged on the wafer. A mask 109 is applied to the recorded image and unmasked portions 111 of the image are further processed by averaging. The unmasked portions 111 are selected such that they include memory portions of the wafer.

Abstract: An extremely non-degenerate two photon absorption (END-2PA) method and apparatus provide for irradiating a semiconductor material substrate simultaneously with two photons each of different energy less than a bandgap energy of the semiconductor material substrate but in an aggregate greater than the bandgap energy of the semiconductor material substrate. A ratio of a higher energy photon energy to a lower energy photon energy is at least about 3.0. Alternatively, or as an adjunct, the higher energy photon has an energy at least about 75% of the bandgap energy and the lower energy photon has an energy no greater than about 25% of the bandgap energy.

Abstract: A self-powered integrated circuit (IC) device includes a lead frame and a solar cell having first and second main surfaces. The solar cell is mounted on a surface of the lead frame. An IC chip is also provided. A first electrical interconnector electrically couples the IC chip to the lead frame and a second electrical interconnector electrically couples the solar cell to the IC chip. A portion of the first main surface of the solar cell is configured to receive light from an external source. The solar cell converts energy of the received light into electrical power that is supplied to the IC chip. A mold compound encapsulates the IC chip, the first and second electrical interconnectors, and at least a portion of the solar cell.

Abstract: A light-emitting diode (“LED”) device has an LED chip attached to a substrate. The terminals of the LED chip are electrically coupled to leads of the LED device. Elastomeric encapsulant within a receptacle of the LED device surrounds the LED chip. A second encapsulant is disposed within an aperture of the receptacle on the elastomeric encapsulant.

Abstract: Encapsulated LEDs can be made by taking a mold tool defining a cavity that defines a lens shape and providing a patterned release film defining the inverse of a microstructure in a surface of the film. The patterned release film is conformed to the cavity of the mold tool. An LED chip is placed in a spaced relationship from the patterned release film in the cavity. A resin is then introduced into the space between the LED chip and the patterned release film in the cavity. The resin is cured in the space between the LED chip and the patterned release film in the cavity while contact is maintained between the patterned release film and the curing resin. The encapsulated LED is then freed from the mold tool and the patterned release film.

Abstract: A method for fabricating a silicon submount for LED packaging. A silicon substrate is provided. A reflection layer is formed on the silicon substrate. Portions of the reflection layer and the silicon substrate are removed to form openings. A wafer backside grinding process is carried out to thin the silicon substrate thereby turning the openings into through silicon vias. An insulating layer is then deposited to cover the reflection layer and the silicon substrate. A seed layer is formed on the insulating layer. A resist pattern is then formed on the seed layer. A metal layer is formed on the seed layer not covered by the resist pattern. The resist pattern is then stripped. The seed layer not covered by the metal layer is then removed.

Abstract: There is provided a process for forming a layer of electroactive material having a substantially flat profile. The process includes: providing a workpiece having at least one active area; depositing a liquid composition including the electroactive material onto the workpiece in the active area, to form a wet layer; treating the wet layer on the workpiece at a controlled temperature in the range of ?25 to 80° C. and under a vacuum in the range of 10?6 to 1,000 Torr, for a first period of 1-100 minutes, to form a partially dried layer; heating the partially dried layer to a temperature above 100° C. for a second period of 1-50 minutes to form a dried layer.

Abstract: A method for making light emitting diode includes following steps. A substrate is provided. A first semiconductor layer is grown on a surface of the substrate. A patterned mask layer is located on a surface of the first semiconductor layer, and the patterned mask layer includes a number of bar-shaped protruding structures, a slot is defined between each two adjacent protruding structures to expose a portion of the first semiconductor layer. The exposed first semiconductor layer is etched to form a protruding pair. A number of three-dimensional nano-structures are formed by removing the patterned mask layer. An active layer and a second semiconductor layers are grown on the number of three-dimensional nano-structures in that order. A first electrode is electrically connected with the first semiconductor layer. A second electrode is located to cover the entire surface of the second semiconductor layer which is away from the active layer.

Abstract: A display substrate is provided that can prevent the opening of an upper conduction layer. The display substrate comprises a semiconductor layer pattern formed on a substrate, a data interconnection pattern formed on the semiconductor layer pattern, a protection layer formed on the substrate and the data interconnection pattern, contact holes formed on the substrate to expose at least a portion of an upper surface of the semiconductor pattern and at least a portion of an upper surface of the data interconnection pattern, and contact electrodes formed in the contact holes to be in contact with the exposed upper surfaces of the data interconnection pattern and the semiconductor layer pattern.

Abstract: A display apparatus includes a display substrate and a counter substrate. The display substrate includes a first substrate and a plurality of pixel electrodes formed on the first substrate. The counter substrate includes a second substrate facing the first substrate, a common electrode formed on the second substrate, a first spacer formed on the common electrode and making contact with the display substrate, a second spacer having a first gap with the display substrate, a third spacer having a second gap larger than the first gap with the display substrate, and a fourth spacer having a third gap larger than the second gap with the display substrate.

Abstract: An organic electroluminescence display panel includes a thin-film transistor layer above a substrate. A planarizing film is above the thin-film transistor layer with contact holes being formed in the planarizing film. A bank is above the planarizing film. The bank includes openings arranged in rows and columns that define regions for forming organic electroluminescence elements. Each opening is between a pair of adjacent concaves in one of the columns. The concaves are formed in an upper surface of the bank and sunken into the contact holes. The upper surface of the bank has repellency. A light-emitting layer is formed in each opening by ejecting drops of an ink from nozzles of an inkjet head into the openings while moving the inkjet head relative to the substrate. The nozzles further eject drops of the ink into the concaves when above the concaves for ejecting the drops of the ink through every nozzle.

Abstract: In one aspect, an encapsulation sheet, a method of manufacturing an organic light emitting display device using the encapsulation sheet, and an organic light emitting display device is provided. The encapsulation sheet includes a carrier film; and a first sheet formed on the carrier film, wherein the first sheet comprises at least one of tin fluorophosphates glass, chalcogenide glass, tellurite glass, borate glass, and phosphate glass.

Abstract: A gas sensitive material comprising SnO2 nanocrystals doped with In2O3 and an oxide of a platinum group metal, and a method of making the same. The platinum group metal is preferably Pd, but also may include Pt, Ru, Ir, and combinations thereof. The SnO2 nanocrystals have a specific surface of 7 or greater, preferably about 20 m2/g, and a mean particle size of between about 10 nm and about 100 nm, preferably about 40 nm. A gas detection device made from the gas sensitive material deposited on a substrate, the gas sensitive material configured as a part of a current measuring circuit in communication with a heat source.

Abstract: A method of making a neutron detector such as a microstructured semiconductor neutron detector is provided. The method includes the step of providing a particle-detecting substrate having a surface and a plurality of cavities extending into the substrate from the surface. The method also includes filling the plurality of cavities with a neutron-responsive material. The step of filling including the step of centrifuging nanoparticles of the neutron-responsive material with the substrate for a time and a rotational velocity sufficient to backfill the cavities with the nanoparticles. The material is responsive to neutrons absorbed, thereby, for releasing ionizing radiation reaction products.

Abstract: Techniques, apparatus and systems are described for wafer-scale processing of aligned nanotube devices and integrated circuits. In one aspect, a method can include growing aligned nanotubes on at least one of a wafer-scale quartz substrate or a wafer-scale sapphire substrate. The method can include transferring the grown aligned nanotubes onto a target substrate. Also, the method can include fabricating at least one device based on the transferred nanotubes.

Abstract: A method of forming an integrated circuit structure includes providing a silicon substrate, and implanting a p-type impurity into the silicon substrate to form a p-type region. After the step of implanting, performing an anneal to form a silicon oxide region, with a portion of the p-type region converted to the silicon oxide region.

Abstract: Disclosed are a method of manufacturing a dye sensitized solar battery and a solar battery assembling apparatus. The method includes: forming electrode pads on electrodes of respective solar battery sub modules; applying a conductive adhesive on the electrode; and overlapping the electrodes of the solar battery sub modules, applying a current to the electrode pads, and then heating and hardening the conductive adhesive.

Abstract: The linear semiconductor substrate 1 or 2 of the present invention comprises at least one desired thin film 4 formed on a linear substrate 3 having a length ten or more times greater than a width, thickness, or diameter of the linear substrate itself. Adopting semiconductor as the thin film 4 forms a linear semiconductor thin film. The linear semiconductor substrate 1 or 2 of the present invention is produced by utilizing a fiber-drawing technique which is a fabricating technique of optical fibers.

Abstract: Discussed is a fabrication method of a solar cell according to an embodiment of the invention, which includes forming an electrode material on a semiconductor substrate for the solar cell; and forming an electrode by heat treating the electrode material by laser irradiation, wherein the electrode material comprises at least one of an electrode paste, electrode ink and aerosol for the electrode.

Abstract: An embodiment of array of Geiger-mode avalanche photodiodes, wherein each photodiode is formed by a body of semiconductor material, having a first conductivity type and housing an anode region, of a second conductivity type, facing a top surface of the body, a cathode-contact region, having the first conductivity type and a higher doping level than the body, facing a bottom surface of the body, an insulation region extending through the body and insulating an active area from the rest of the body, the active area housing the anode region and the cathode-contact region. The insulation region is formed by a first mirror region of polycrystalline silicon, a second mirror region of metal material, and a channel-stopper region of dielectric material, surrounding the first and second mirror regions.

Abstract: An object of the invention is to provide a TFT substrate and a method for producing a TFT substrate which is capable of drastically reducing the production cost by decreasing the number of steps in the production process and improving production yield. A TFT substrate comprises: a substrate; a first oxide layer formed above the substrate; a second oxide layer formed above the first oxide layer with a channel part interposed therebetween; gate insulating film formed above the substrate, the first oxide layer and the second oxide layer; a gate electrode and a gate wire formed above the gate insulating film.

Abstract: The invention relates to a serial connection of thin layer solar cells. The invention provides a structuring method for creating a reliable and effective connections, preventing short-circuits and enlarging usable solar cell surfaces. The solar cells comprise a substrate, a back contact layer, an absorber layer, a buffer layer, and a transparent front contact layer. Each solar cell is subdivided by three trenches A, B, C to create a plurality of adjacent cell segments. Trenches A and B extend down to the back contact layer, trench C extends down to the substrate. Trench C is filled with electrically insulating paste and trench B is filled with electrically conducting paste. The electrically conducting paste also covers trench C. The adjacent cell segments are electrically connected. Trench A is then created and filled with electrically insulating paste.

Abstract: A thin film solar cell and a method fabricating thin film solar cells on flexible substrates. The method includes including providing a flexible polymeric substrate, depositing a photovoltaic precursor on a surface of the substrate, such as CdTe, ZrTe, CdZnTe, CdSe or Cu(In,Ga)Se2, and exposing the photovoltaic precursor to at least one 0.5 microsecond to 10 second pulse of predominately infrared light emitted from a light source having a power output of about 20,000 W/cm2 or less to thermally convert the precursor into a crystalline photovoltaic material having a photovoltaic efficiency of greater than one percent, the conversion being carried out without substantial damage to the substrate.

Abstract: Avalanche photodiodes having special lateral doping concentration that reduces dark current without causing any loss of optical signals and method for the fabrication thereof are described. In one aspect, an avalanche photodiode comprises: a substrate, a first contact layer coupled to at least one metal contract of a first electrical polarity, an absorption layer, a doped electric control layer having a central region and a circumferential region surrounding the central region, a multiplication layer having a partially doped central region, and a second contract layer coupled to at least one metal contract of a second electrical polarity. Doping concentration in the central section of the electric control layer is lower than that of the circumferential region. The absorption layer can be formed by selective epitaxial growth.

Abstract: An organic light emitting display in which differential pressure is controlled to prevent Newton's rings from being generated and a method of fabricating the same are provided. The organic light emitting display includes a first substrate including a pixel region in which at least one organic light emitting diode (OLED) is formed and a non-pixel region, a second substrate attached to one region including the pixel region of the first substrate, and a frit provided between the non-pixel region of the first substrate and the second substrate. At least one of the first substrate and the second substrate is formed to be convex outward.

Abstract: Provided is a method of manufacturing an organic electroluminescence display device including: an organic compound layer-forming step of forming an organic compound layer on a first electrode; a release layer-forming step of forming a release layer on the organic compound layer; a first processing step for the release layer of patterning the release layer; an organic compound layer-processing step of removing the organic compound layer in a region not covered with the release layer processed in the first processing step for the release layer; and a second processing step for the release layer of removing a part of the release layer, in which the release layer is a deposited film formed of a charge-transportable organic compound and is dissolved by a solvent containing an organic solvent miscible with water.

Abstract: Methods of manufacturing non-volatile memory devices may include separating first phase-change material groups and second phase-change material groups, which have different sizes, from a target including phase-change materials and faulting a phase-change material layer on an object by using the first phase-change material groups and the second phase-change material groups.

Abstract: A semiconductor device in which a defect is suppressed and miniaturization is achieved is provided.

Abstract: The present invention provides a highly reliable circuit board that includes TFTs a semiconductor layer of which is formed from an oxide semiconductor; and low-resistance aluminum wirings. The circuit board of the present invention includes an oxide semiconductor layer; source wirings; and drain wirings, wherein each of the source wirings and the drain wirings includes a portion in contact with the semiconductor layer, portions of the source wirings in contact with the semiconductor layer and respective portions of the drain wirings in contact with the semiconductor layer spacedly facing each other, and the source wirings and the drain wirings are formed by stacking a layer formed from a metal other than aluminum and a layer containing aluminum.

Abstract: A method of manufacturing silver (Ag)-doped zinc oxide (ZnO) nanowires and a method of manufacturing an energy conversion device are provided. In the method of manufacturing Ag-doped ZnO nanowires, the Ag-doped nanowires are grown by a low temperature hydrothermal synthesis method using a Ag-containing aqueous solution.

Abstract: Microelectronic devices, associated assemblies, and associated methods are disclosed herein. For example, certain aspects of the invention are directed toward a microelectronic device that includes a microfeature workpiece having a side and an aperture in the side. The device can further include a workpiece contact having a surface. At least a portion of the surface of the workpiece contact can be accessible through the aperture and through a passageway extending between the aperture and the surface. Other aspects of the invention are directed toward a microelectronic support device that includes a support member having a side carrying a support contact that can be connectable to a workpiece contact of a microfeature workpiece. The device can further include recessed support contact means carried by the support member. The recessed support contact means can be connectable to a second workpiece contact of the microfeature workpiece.

Abstract: In one embodiment, a method of forming a semiconductor package includes placing a first die and a second die over a carrier. At least one of the first and the second dies are covered with an encapsulation material to form an encapsulant having a top surface and an opposite bottom surface. The encapsulant is thinned from the bottom surface to expose a first surface of the first die without exposing the second die. The exposed first surface of the first die is selectively etched to expose a second surface of the first die. A back side conductive layer is formed so as to contact the first surface. The second die is separated from the back side conductive layer by a first portion of the encapsulant.

Abstract: A system and method for efficiently addressing dies in a three-dimensional stacked integrated circuit. Multiple stacked dies may be included in a single package or module. At least two of the dies are vertically stacked. One or more of the dies may include die enumeration logic that generates a unique die address space identifier (ID) for a particular die. Unless a die is a base die, each die receives a unique die ID for itself from a die placed below itself. The die then generates a unique die ID for one or more dies placed above itself and sends these die IDs to the dies located on top of itself. If a die is a base die, then the logic may receive a root value for a first unique die ID within the vertical stack from the package substrate or silicon based interposer beneath it.

Abstract: A WLCSP method comprises: depositing a metal bump on bonding pads of chips; forming a first packaging layer at front surface of wafer to cover metal bumps while forming an un-covered ring at the edge of wafer to expose the ends of each scribe line located between two adjacent chips; thinning first packaging layer to expose metal bumps; forming a groove on front surface of first packaging layer along each scribe line by cutting along a straight line extended by two ends of scribe line exposed on front surface of un-covered ring; grinding back surface of wafer to form a recessed space and a support ring at the edge of the wafer; depositing a metal layer at bottom surface of wafer in recessed space; cutting off the edge portion of wafer; and separating individual chips from wafer by cutting through first packaging layer, the wafer and metal layer along groove.

Abstract: A structure for a semiconductor component is provided having a bi-layer capping coating integrated and built on supporting layer to be transferred. The bi-layer capping protects the layer to be transferred from possible degradation resulting from the attachment and removal processes of the carrier assembly used for layer transfer. A wafer-level layer transfer process using this structure is enabled to create three-dimensional integrated circuits.

Abstract: Methods for bonding substrate surfaces, bonded substrate assemblies, and design structures for a bonded substrate assembly. Device structures of a product chip are formed using a first surface of a device substrate. A wiring layer of an interconnect structure for the device structures is formed on the product chip. The wiring layer is planarized. A temporary handle wafer is removably bonded to the planarized wiring layer. In response to removably bonding the temporary handle wafer to the planarized first wiring layer, a second surface of the device substrate, which is opposite to the first surface, is bonded to a final handle substrate. The temporary handle wafer is then removed from the assembly.

Abstract: Packaged semiconductor devices and packaging devices and methods are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a first integrated circuit die that is coupled to a first surface of a substrate that includes through-substrate vias (TSVs) disposed therein. A conductive ball is coupled to each of the TSVs on a second surface of the substrate that is opposite the first surface of the substrate. A second integrated circuit die is coupled to the second surface of the substrate, and a molding compound is formed over the conductive balls, the second integrated circuit die, and the second surface of the substrate. The molding compound is removed from over a top surface of the conductive balls, and the top surface of the conductive balls is recessed. A redistribution layer (RDL) is formed over the top surface of the conductive balls and the molding compound.

Abstract: A method of manufacturing a lead frame, includes forming a rectangular first dimple includes, first inclined side surfaces inclined to a depth direction, and arranged in two opposing sides in one direction, and standing side surfaces standing upright to a depth direction, and arranged in two opposing sides in other direction, on a backside of a die pad by a first stamping, and forming a second dimple having second inclined side surfaces inclined on the backside of the die pad by a second stamping, such that a second inclined side surfaces of the second dimple are arranged in side areas of the standing side surfaces of the first dimple, wherein the standing side surfaces are transformed into reversed inclined side surfaces inclined to a reversed direction to the first inclined side surfaces, and a front side of the die pad is semiconductor element mounting surface.