Patents Issued in July 15, 2014
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Patent number: 8778740Abstract: To avoid shorts between adjacent die pads in mounting a multi-die semiconductor package to a printed circuit board (PCB), one of the die pads is embedded in the polymer capsule, while the other die pad is exposed at the bottom of the package to provide a thermal escape path to the PCB. This arrangement is particularly useful when one of the dice in a multi-die package generates more heat than another die in the package. A process for fabricating the package includes a partial etch that defines the bottom surface of the embedded die pad and may include a through-etch that leaves one or more of the contacts or leads integrally connected to the embedded die pad.Type: GrantFiled: May 19, 2013Date of Patent: July 15, 2014Assignees: Advanced Analogic Technologies Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard K. Williams, Keng Hung Lin
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Patent number: 8778741Abstract: Disclosed herein is a device package that comprises a device having a top substrate that is disposed on a supporting surface of a package substrate. A package frame contacts the top surface of the top substrate and top surface of the package substrate, and hermetically seals the device between the top surfaces of the top substrate and package substrate. The device can be a semiconductor device, a microstructure such as a microelectromechanical device, or other devices.Type: GrantFiled: December 19, 2008Date of Patent: July 15, 2014Assignee: Texas Instruments IncorporatedInventors: Robert M. Duboc, Terry Tarn
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Patent number: 8778742Abstract: Methods and systems are disclosed for gate dimension control in multi-gate structures for integrated circuit devices. Processing steps for formation of one or more subsequent gate structures are adjusted based upon dimensions determined for one or more previously formed gate structures. In this way, one or more features of the resulting multi-gate structures can be controlled with greater accuracy, and variations between a plurality of multi-gate structures can be reduced. Example multi-gate features and/or dimensions that can be controlled include overall gate length, overlap of gate structures, and/or any other desired features and/or dimensions of the multi-gate structures. Example multi-gate structures include multi-gate NVM (non-volatile memory) cells for NVM systems, such as for example, split-gate NVM cells having select gates (SGs) and control gates (CGs).Type: GrantFiled: April 26, 2013Date of Patent: July 15, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Sung-Taeg Kang, ShanShan Du
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Patent number: 8778743Abstract: An approach for providing a latch-up robust PNP-triggered SCR-based device is disclosed. Embodiments include providing a silicon control rectifier (SCR) region; providing a PNP region having a first n-well region proximate the SCR region, a first N+ region and a first P+ region in the first n-well region, and a second P+ region between the SCR region and the first n-well region; coupling the first N+ region and the first P+ region to a power rail; and coupling the second P+ region to a ground rail.Type: GrantFiled: August 17, 2012Date of Patent: July 15, 2014Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Da-Wei Lai, Mahadeva Iyer Natarajan
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Patent number: 8778744Abstract: The present disclosure provides a method for manufacturing a semiconductor field effect transistor, comprising: forming a semiconductor substrate having a local Silicon-on-Insulator (SOI) structure, which comprises a local buried isolation dielectric layer; forming a fin on a silicon substrate above the local buried isolation dielectric layer; forming a gate stack structure on a top and on side faces of the fin; forming source/drain structures in the fin at both sides of the gate stack structure; and metallizing. The present disclosure uses a conventional top-to-bottom process based on quasi-plane, which has a good compatibility with CMOS planar processes. Also, the method can suppress short channel effects and help to reduce the dimensions of MOSFETs.Type: GrantFiled: November 18, 2011Date of Patent: July 15, 2014Assignee: Institute of Microelectronics, Chinese Academy of SciencesInventors: Huajie Zhou, Qiuxia Xu
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Patent number: 8778745Abstract: A method for manufacturing a semiconductor device comprises the steps of forming a seed over the insulating film by introducing hydrogen and a deposition gas into a first treatment chamber under a first condition and forming a microcrystalline semiconductor film over the seed by introducing hydrogen and the deposition gas into a second treatment chamber under a second condition: a second flow rate of the deposition gas is periodically changed between a first value and a second value; and a second pressure in the second treatment chamber is higher than or equal to 1.0×102 Torr and lower than or equal to 1.0×103 Torr.Type: GrantFiled: June 14, 2011Date of Patent: July 15, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Ryu Komatsu, Yasuhiro Jinbo, Hidekazu Miyairi
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Patent number: 8778746Abstract: A thin-film transistor device manufacturing method forms a plurality of gate electrodes above a substrate. A silicon nitride layer is formed on the plurality of gate electrodes. A silicon oxide layer is formed on the silicon nitride layer. An amorphous silicon layer is formed on the silicon oxide layer. The amorphous silicon layer is crystallized using predetermined laser light to produce a crystalline silicon layer. A source electrode and a drain electrode are formed on the crystalline silicon layer in a region that corresponds to each of the plurality of gate electrodes. A film thickness of the silicon oxide layer, a film thickness of the silicon nitride layer, and a film thickness of the amorphous silicon layer satisfy predetermined conditional expressions.Type: GrantFiled: April 25, 2012Date of Patent: July 15, 2014Assignee: Panasonic CorporationInventor: Yuta Sugawara
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Patent number: 8778747Abstract: Embodiments include but are not limited to apparatuses and systems including a buffer layer, a group III-V layer over the buffer layer, a source contact and a drain contact on the group III-V layer, and a regrown Schottky layer over the group III-V layer, and between the source and drain contacts. The embodiments further include methods for making the apparatuses and systems. Other embodiments may be described and claimed.Type: GrantFiled: May 25, 2011Date of Patent: July 15, 2014Assignee: TriQuint Semiconductor, Inc.Inventor: Edward A. Beam, III
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Patent number: 8778748Abstract: A method for manufacturing a semiconductor device includes forming a source electrode and a drain electrode on a front face of a semiconductor substrate which is transparent to visible light, forming a front-side gate electrode between the source electrode and the drain electrode on the front face of the semiconductor substrate; forming an aligning mark on a region of the front face of the semiconductor substrate other than a region between the source electrode and the drain electrode, aligning the semiconductor substrate based on the aligning mark that is seen through the semiconductor substrate, and forming a back-side gate electrode on a back face of the semiconductor substrate in a location opposite the front-side gate electrode.Type: GrantFiled: January 23, 2012Date of Patent: July 15, 2014Assignee: Mitsubishi Electric CorporationInventor: Yoshitaka Kamo
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Patent number: 8778749Abstract: Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Air gaps are formed at least partially in isolation regions between active areas of the substrate. The air gaps may further extend above the substrate surface between adjacent layer stack columns. A sacrificial material is formed at least partially in the isolation regions, followed by forming a dielectric liner. The sacrificial material is removed to define air gaps prior to forming the control gate layer and then etching it and the layer stack columns to form individual control gates and columns of non-volatile storage elements.Type: GrantFiled: January 11, 2012Date of Patent: July 15, 2014Assignee: SanDisk Technologies Inc.Inventors: Jayavel Pachamuthu, Vinod R. Purayath, George Matamis
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Patent number: 8778750Abstract: A method for fabricating a CMOS device includes the following steps. A wafer is provided. STI is used to form at least one active area in the wafer. A silicon oxide layer is deposited onto the wafer covering the active area. A first high-k material is deposited onto the silicon oxide layer. Portions of the silicon oxide layer and the first high-k material are selectively removed, such that the silicon oxide layer and the first high-k material remain over one or more first regions of the active area and are removed from over one or more second regions of the active area. A second high-k material is deposited onto the first high-k material over the one or more first regions of the active area and onto a surface of the wafer in the one or more second regions of the active area. A CMOS device is also provided.Type: GrantFiled: May 5, 2012Date of Patent: July 15, 2014Assignee: International Business Machines CorporationInventors: Eduard Albert Cartier, Michael P. Chudzik, Andreas Kerber, Siddarth Krishnan, Naim Moumen
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Patent number: 8778751Abstract: A semiconductor component includes a semiconductor body having a surface and a cutout in the semiconductor body. The cutout extends from the surface of the semiconductor body into the semiconductor body in a direction perpendicular to the surface. The cutout has a base and at least one sidewall. The component further includes a layer on the surface of the semiconductor body and in the cutout. The layer forms a well above the cutout. The well has a well base, a well edge and at least one well sidewall. The at least one well sidewall forms an angle ? in the range of 20° to 80° with respect to the surface of the semiconductor body. The layer has at least one edge which, proceeding from the well edge, extends in the direction of the surface of the semiconductor body.Type: GrantFiled: September 19, 2011Date of Patent: July 15, 2014Assignee: Infineon Technologies Austria AGInventor: Martin Poelzl
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Patent number: 8778752Abstract: A method for designing a semiconductor device includes arranging at least a pattern of a first active region in which a first transistor is formed and a pattern of a second active region in which a second transistor is formed; arranging at least a pattern of a gate wire which intersects the first active region and the second active region; extracting at least a first region in which the first active region and the gate wire are overlapped with each other; arranging at least one pattern of a compressive stress film on a region including the first active region; and obtaining by a computer a layout pattern of the semiconductor device, when the at least one pattern of the compressive stress film is arranged, end portions of the at least one pattern thereof are positioned based on positions of end portions of the first region.Type: GrantFiled: November 3, 2010Date of Patent: July 15, 2014Assignee: Fujitu Semiconductor LimitedInventor: Yasunobu Torii
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Patent number: 8778753Abstract: A substrate including an NMOS transistor region and a PMOS transistor region is prepared. A silicon-germanium layer is formed on the PMOS transistor region. Nitrogen atoms are injected in an upper portion of the silicon-germanium layer. A first gate dielectric layer is formed on the NMOS transistor region and the PMOS transistor region. The nitrogen atoms are injected into the upper portion of the silicon-germanium layer before forming the first gate dielectric layer.Type: GrantFiled: March 19, 2012Date of Patent: July 15, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jinho Do, Hajin Lim, WeonHong Kim, Kyungil Hong, Moonkyun Song
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Patent number: 8778754Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate with a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a metal layer over the high-k dielectric layer, the metal layer having a first work function, protecting the metal layer in the first region, treating the metal layer in the second region with a de-coupled plasma that includes carbon and nitrogen, and forming a first gate structure in the first region and a second gate structure in the second region. The first gate structure includes the high-k dielectric layer and the untreated metal layer. The second gate structure includes the high-k dielectric layer and the treated metal layer.Type: GrantFiled: February 2, 2009Date of Patent: July 15, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Su-Horng Lin
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Patent number: 8778755Abstract: A method for fabricating a metal-insulator-metal capacitor (MIMCap) is disclosed. A first metal layer is provided on top of an oxide layer. A nitride layer is then deposited on the first metal layer. The nitride layer and the first metal layer are etched to form a MIMCap metal layer. The gaps among the MIMCap metal layer are filled with a plasma oxide, and the excess plasma oxide is polished using the nitride layer a polish stop. After removing the nitride layer, a dielectric layer and a second metal layer are deposited on the MIMCap metal layer. Finally, the dielectric layer and the second metal layer are etched to form a set of MIMCap structures.Type: GrantFiled: July 12, 2012Date of Patent: July 15, 2014Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Jason F. Ross, Chi-Hua Yang, Thomas J. McIntyre
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Patent number: 8778756Abstract: A method of manufacturing a semiconductor device comprising the steps of: forming a first interlayer insulating film over a substrate; forming a first conductive film over the first interlayer insulating film; forming a ferroelectric film on the first conductive film; forming a second conductive film on the ferroelectric film; forming an upper electrode of a capacitor by patterning the second conductive film; forming a capacitor dielectric film by patterning the ferroelectric film; and forming a lower electrode of the capacitor by patterning the first conductive film, wherein forming the first conductive film includes: forming a lower conductive layer made of a noble metal other than iridium over the first interlayer insulating film; and forming an upper conductive layer on the lower conductive layer, the upper conductive layer being made of a conductive material, which is different from a material for the lower conductive layer, and which is other than platinum.Type: GrantFiled: October 22, 2012Date of Patent: July 15, 2014Assignee: Fujitsu Semiconductor LimitedInventor: Wensheng Wang
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Patent number: 8778757Abstract: In methods of manufacturing a DRAM device, a buried-type gate is formed in a substrate. A capping insulating layer pattern is formed on the buried-type gate. A conductive layer pattern filling up a gap between portions of the capping insulating layer pattern, and an insulating interlayer covering the conductive layer pattern and the capping insulating layer pattern are formed. The insulating interlayer, the conductive layer pattern, the capping insulating layer pattern and an upper portion of the substrate are etched to form an opening, and a first pad electrode making contact with a first pad region. A spacer is formed on a sidewall of the opening corresponding to a second pad region. A second pad electrode is formed in the opening. A bit line electrically connected with the second pad electrode and a capacitor electrically connected with the first pad electrode are formed.Type: GrantFiled: July 3, 2012Date of Patent: July 15, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Chul Park, Sang-sup Jeong
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Patent number: 8778758Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a plurality of electrode structures above a substrate. The method includes forming an insulating film on the plurality of electrode structures to make a gap between mutually-adjacent electrode structures. The method includes forming a silicon nitride film having compressive stress above the insulating film. The method includes forming a planarization film above the silicon nitride film. The method includes planarizing a surface of the planarization film by polishing by CMP (chemical mechanical polishing) method.Type: GrantFiled: December 3, 2012Date of Patent: July 15, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Hiroshi Kubota
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Patent number: 8778759Abstract: A gate dielectric as formed includes a first interfacial dielectric layer and a high dielectric constant (high-k) dielectric layer containing a dielectric metal oxide. A polycrystalline semiconductor material layer is deposited on the high-k dielectric layer, and a second interfacial dielectric layer is formed at an interface between the polycrystalline semiconductor material layer and the high-k dielectric layer. A scavenging-metal-containing layer including a scavenging metal in an elemental form or in a metallic non-metal-element-containing compound is formed over the polycrystalline semiconductor material layer. A metallic compound such as a metallic nitride and a metallic carbide may be present above and/or over the scavenging-metal-containing layer. After formation of a gate stack by patterning, an anneal is performed, during which the oxygen in the interfacial dielectric layers diffuses into the scavenging-metal containing layer so that the thicknesses of the interfacial layers are reduced.Type: GrantFiled: September 11, 2013Date of Patent: July 15, 2014Assignee: International Business Machines CorporationInventors: Martin M. Frank, Isaac Lauer, Jeffrey W. Sleight
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Patent number: 8778760Abstract: A method of manufacturing a flash memory cell includes providing a substrate having a first dielectric layer formed thereon, forming a control gate on the first dielectric layer, forming an oxide-nitride-oxide (ONO) spacer on sidewalls of the control gate, forming a second dielectric layer on the substrate at two sides of the ONO spacer, and forming a floating gate at outer sides of the ONO spacer on the second dielectric layer, respectively.Type: GrantFiled: December 23, 2013Date of Patent: July 15, 2014Assignee: Taiwan Memory CompanyInventors: Yung-Chang Lin, Nan-Ray Wu, Le-Tien Jung
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Patent number: 8778761Abstract: A semiconductor device fabrication method particularly suitable for the fabrication of a 90 nm embedded flash memory is disclosed. The method includes: forming a dielectric layer having a first thickness over a first device region and forming a dielectric layer having a second thickness different from the first thickness over a second device region, the dielectric layer having a first thickness serving as a tunnel oxide layer of a split-gate structure, the dielectric layer having a second thickness serving as a gate oxide layer of a MOS transistor. The method enables the fabrication of a MOS transistor including a gate oxide layer with a desired thickness.Type: GrantFiled: June 10, 2013Date of Patent: July 15, 2014Assignee: Shanghai Huahong Grace Semiconductor Manufacturing CorporationInventors: Jing Gu, Binghan Li
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Patent number: 8778762Abstract: Some embodiments include methods of forming vertically-stacked structures, such as vertically-stacked memory cells. A first hardmask is formed over a stack of alternating electrically conductive levels and electrically insulative levels. A first opening is formed through the first hardmask and the stack. Cavities are formed to extend into the electrically conductive levels. A fill material is formed within the first opening and within the cavities. A second hardmask is formed over the first hardmask and over the fill material. A second opening is formed through the second hardmask. The second opening is narrower than the first opening. The second opening is extended into the fill material to form an upwardly-opening container from the fill material. Sidewalls of the upwardly-opening container are removed, while leaving the fill material within the cavities as a plurality of vertically-stacked structures.Type: GrantFiled: December 7, 2012Date of Patent: July 15, 2014Assignee: Micron Technology, Inc.Inventors: Saurabh Keshav, Scott Pook, Fatma Arzum Simsek-Ege
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Patent number: 8778763Abstract: A method for forming a memory cell transistor is disclosed which includes providing a substrate, forming a trench structure in the substrate, depositing a conductive substance on the surface of the substrate to form a conductive member inside the trench structure, forming one or more dielectric layers on the surface of the substrate, forming one or more first conductive layers on top of the dielectric layers, and etching the first conductive layers and the dielectric layers to form a hole structure extending through the first conductive and the dielectric layers, reaching to the substrate surface. One or more second conductive layers may be formed on top of the first conductive layers, with the second conductive layer material filling the hole structure.Type: GrantFiled: December 8, 2011Date of Patent: July 15, 2014Assignee: Hermes Microvision, Inc.Inventor: Hong Xiao
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Patent number: 8778764Abstract: In one embodiment, a semiconductor device includes a multi-portion shield electrode structure formed in a drift region. The shield electrode includes a wide portion formed in proximity to a channel side of the drift region, and a narrow portion formed deeper in the drift region. The narrow portion is separated from the drift region by a thicker dielectric region, and the wide portion is separated from the drift region by a thinner dielectric region. That portion of the drift region in proximity to the wide portion can have a higher dopant concentration than other portions of the drift region.Type: GrantFiled: July 16, 2012Date of Patent: July 15, 2014Assignee: Semiconductor Components Industries, LLCInventor: Zia Hossain
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Patent number: 8778765Abstract: Methods of fabricating semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a gate material stack over a workpiece having a first region and a second region. The gate material stack includes a semiconductive gate material. A thickness is altered or a substance is introduced to the semiconductive gate material in the first region or the second region of the workpiece. The gate material stack is patterned in the first region and the second region resulting in a first transistor in the first region of the workpiece comprising an NMOS FET of a CMOS device and a second transistor in the second region of the workpiece comprising an NMOS FET of the CMOS device. The first transistor has a first threshold voltage and the second transistor has a second threshold voltage different than the first threshold voltage.Type: GrantFiled: April 1, 2013Date of Patent: July 15, 2014Assignee: Infineon Technologies AGInventors: Knut Stahrenberg, Jin-Ping Han
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Patent number: 8778766Abstract: A field effect transistor of an embodiment of the present invention includes, a semiconductor substrate containing Si atoms; a protruding structure formed on the semiconductor substrate; a channel region formed in the protruding structure and containing Ge atoms; an under channel region formed under the channel region in the protruding structure and containing Si and Ge atoms, the Ge composition ratio among Si and Ge atoms contained in the under channel region continuously changing from the channel region side to the semiconductor substrate side; a gate insulating film formed on the channel region; and a gate electrode formed on the gate insulating film on the channel region.Type: GrantFiled: September 14, 2012Date of Patent: July 15, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Tsutomu Tezuka, Toshifumi Irisawa
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Patent number: 8778767Abstract: A method of forming an integrated circuit includes forming a gate structure over a substrate. Portions of the substrate are removed to form recesses adjacent to the gate structure. A silicon-containing material structure is formed in each of the recesses. The silicon-containing material structure has a first region and a second region, the second region is closer to the gate structure than the first region, and the first region is thicker than the second region.Type: GrantFiled: February 17, 2011Date of Patent: July 15, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Hsien Huang, Yi-Fang Pai, Chien-Chang Su
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Patent number: 8778768Abstract: An alternating stack of two different semiconductor materials is patterned to include two pad regions and nanowire regions. A semiconductor material is laterally etched selective to another semiconductor material to form a nanomesh including suspended semiconductor nanowires. Gate dielectrics, a gate electrode, and a gate cap dielectric are formed over the nanomesh. A dielectric spacer is formed around the gate electrode. The semiconductor materials in the two pad regions and physically exposed portions of the nanomesh are removed employing the dielectric spacer and the gate cap dielectric as an etch mask. A source region and a drain region are epitaxially grown from end surfaces of the nanomesh.Type: GrantFiled: March 12, 2013Date of Patent: July 15, 2014Assignee: International Business Machines CorporationInventors: Josephine B. Chang, Paul Chang, Issac Lauer, Jeffrey W. Sleight
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Patent number: 8778769Abstract: The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a substrate, a first capacitor, a first protective layer, a first metal layer and a second protective layer. The substrate has at least one via structure. The first capacitor is disposed on a first surface of the substrate. The first protective layer encapsulates the first capacitor. The first metal layer is disposed on the first protective layer, and includes a first inductor. The second protective layer encapsulates the first inductor. Whereby, the first inductor, the first capacitor and the via structure are integrated into the semiconductor package, so that the size of the product is reduced.Type: GrantFiled: December 21, 2012Date of Patent: July 15, 2014Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Chien-Hua Chen, Teck-Chong Lee
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Patent number: 8778770Abstract: A semiconductor device comprises a trench isolation. The trench isolation is formed in a surface of a semiconductor substrate to define an active region a well region, and a bottom of the trench isolation is positioned within the well region. The trench isolation includes a conductive wiring electrically connected to the well region and an insulating film which buries the conductive wiring in the bottom of the trench isolation. Semiconductor elements are disposed in the active region.Type: GrantFiled: March 12, 2012Date of Patent: July 15, 2014Assignee: PS4 Luxco S.A.R.L.Inventor: Kiyonori Oyu
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Patent number: 8778771Abstract: A method of manufacturing a semiconductor device includes steps of providing a substrate including a semiconductor portion, a non-porous semiconductor layer, and a porous semiconductor layer arranged between the semiconductor portion and the non-porous semiconductor layer, forming a porous oxide layer by oxidizing the porous semiconductor layer, forming a bonded substrate by bonding a supporting substrate to a surface, on a side of the non-porous semiconductor layer, of the substrate on which the porous oxide layer is formed, and separating the semiconductor portion from the bonded substrate by utilizing the porous oxide layer.Type: GrantFiled: June 17, 2011Date of Patent: July 15, 2014Assignee: Canon Kabushiki KaishaInventor: Kazuo Kokumai
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Patent number: 8778772Abstract: Methods of forming transistor devices having an increased gate width dimension are disclosed. In one example, the method includes forming an isolation structure in a semiconducting substrate, wherein the isolation structure defines an active region in the substrate, performing an ion implantation process on the isolation structure to create a damaged region in the isolation structure and, after performing the implantation process, performing an etching process to remove at least a portion of the damaged region to define a recess in the isolation structure, wherein a portion of the recess extends below an upper surface of the substrate and exposes a sidewall of the active region. The method further includes forming a gate insulation layer above the active region, wherein a portion of the insulation layer extends into the recess, and forming a gate electrode above the insulation layer, wherein a portion of the gate electrode extends into the recess.Type: GrantFiled: January 11, 2012Date of Patent: July 15, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Chung Foong Tan, Maciej Wiatr, Peter Javorka, Falong Zhou
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Patent number: 8778773Abstract: Embodiments of the present invention include methods of directly bonding together semiconductor structures. In some embodiments, a cap layer may be provided at an interface between directly bonded metal features of the semiconductor structures. In some embodiments, impurities are provided within the directly bonded metal features of the semiconductor structures. Bonded semiconductor structures are formed using such methods.Type: GrantFiled: December 16, 2010Date of Patent: July 15, 2014Assignee: SoitecInventor: Mariam Sadaka
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Patent number: 8778774Abstract: Methods are provided for enhancing properties, including polarization, of thin-film ferroelectric materials in electronic devices. According to one embodiment, a process for enhancing properties of ferroelectric material in a device having completed wafer processing includes applying mechanical stress to the device, independently controlling the temperature of the device to cycle the temperature from room temperature to at or near the Curie temperature of the ferroelectric material and back to room temperature while the device is applied with the mechanical stress, and then removing the mechanical stress. Certain of the subject methods can be performed as part of a back end of line (BEOL) process, and may be performed during the testing phase at wafer or die level.Type: GrantFiled: September 23, 2011Date of Patent: July 15, 2014Assignees: University of Florida Research Foundation, Inc., Texas Instruments IncorporatedInventors: Toshikazu Nishida, Antonio Guillermo Acosta, John Anthony Rodriguez, Theodore Sidney Moise
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Patent number: 8778775Abstract: A method for preparing a thin layer of GaN from a starting substrate in which at least one thick surface area extending along a free face of the starting substrate includes GaN, where the method includes bombarding the free face of the substrate with helium and hydrogen atoms, the helium being implanted first into the thickness of the thick surface area and the hydrogen being implanted thereafter, and where the helium and hydrogen doses each vary between 1.1017 atoms/cm2 and 4.1017 atoms/cm2. The starting substrate is subjected to a rupture process in order to induce the separation, relative to a residue of the starting substrate, of the entire portion of the thick area located between the free face and the helium and hydrogen implantation depth. The helium is advantageously implanted in a dose at least equal to that of hydrogen, and can also be implanted alone.Type: GrantFiled: December 18, 2007Date of Patent: July 15, 2014Assignee: Commissariat a l'Energie AtomiqueInventors: Aurélie Tauzin, Jérôme Dechamp, Frédéric Mazen, Florence Madeira
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Patent number: 8778776Abstract: Provided is a method of forming a semiconductor package including providing a substrate having a first side and an opposite second side and providing a wafer having a plurality of semiconductor chips, each of the semiconductor chips having a conductive pad, wherein at least one of the substrate and the wafer includes a seed pattern. The first side of the substrate is bonded to the wafer with the conductive pad positioned adjacent to the first side of the substrate and the seed pattern positioned between the conductive pad and the first side of the substrate. A through hole is then formed penetrating the substrate from the second side of the substrate to expose the seed pattern. A through electrode is formed in the through hole using the seed pattern as a seed. Corresponding devices are also provided.Type: GrantFiled: July 21, 2011Date of Patent: July 15, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Ju-il Choi, Kyu-Ha Lee, Jae-hyun Phee, Jung-Hwan Kim, Tae Hong Min
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Patent number: 8778777Abstract: A method for manufacturing a heterostructure for applications in the fields of electronics, photovoltaics, optics or optoelectronics, by implanting atomic species in a donor substrate so as to form an embrittlement area therein, assembling a receiver substrate on the donor substrate, wherein the receiver substrate has a larger thermal expansion coefficient than that of the donor substrate, detaching a rear portion of the donor substrate along the embrittlement area so as to transfer a thin layer of interest of the donor substrate onto the receiver substrate, and applying a detachment annealing after assembling and but before detaching, in order to facilitate the detaching. The detachment annealing includes the simultaneous application of a first temperature to the donor substrate and a second temperature different from the first to the receiver substrate; with the first and second temperatures being selected to reduce the tensile stress condition of the donor substrate.Type: GrantFiled: September 9, 2009Date of Patent: July 15, 2014Assignee: SoitecInventor: Mark Kennard
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Patent number: 8778778Abstract: According to an embodiment, an active layer is formed on a first surface of a semiconductor substrate, a wiring layer is formed on the active layer, and an insulating layer is formed covering the wiring layer. The first surface of the semiconductor substrate is bonded to a support substrate via the insulating layer, and the semiconductor substrate bonded to the support substrate is thinned leaving the semiconductor substrate having a predetermined thickness which covers the active layer from a second surface. At least a part of area of the thinned semiconductor substrate is removed to expose the active layer.Type: GrantFiled: August 18, 2011Date of Patent: July 15, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kazumasa Tanida, Masahiro Sekiguchi, Masayuki Dohi, Tsuyoshi Matsumura, Hideo Numata, Mari Otsuka, Naoko Yamaguchi, Takashi Shirono, Satoshi Hongo
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Patent number: 8778779Abstract: A method for producing semiconductor device includes: performing first, second and third exposures of a photoresist film formed on a semiconductor wafer via a mask; wherein: first, second and third shot regions respectively defined by the first, second and third exposures are aligned in a first direction; the mask has a shot region including a peripheral scribe region having a first and second side crossing the first direction; the photoresist film is of positive type, a first pattern is formed as a light shielding pattern disposed on the first side, and a second pattern is formed as a light transmitting region disposed on the second side; the first and second exposures are performed in such a manner that the first and second patterns do not overlap each other; and the second and third exposures are performed in such a manner that the first and second patterns overlap each other.Type: GrantFiled: August 10, 2012Date of Patent: July 15, 2014Assignee: Fujitsu Semiconductor LimitedInventor: Mitsufumi Naoe
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Patent number: 8778780Abstract: Techniques for fabricating metal devices, such as vertical light-emitting diode (VLED) devices, power devices, laser diodes, and vertical cavity surface emitting laser devices, are provided. Devices produced accordingly may benefit from greater yields and enhanced performance over conventional metal devices, such as higher brightness of the light-emitting diode and increased thermal conductivity. Moreover, the invention discloses techniques in the fabrication arts that are applicable to GaN-based electronic devices in cases where there is a high heat dissipation rate of the metal devices that have an original non- (or low) thermally conductive and/or non- (or low) electrically conductive carrier substrate that has been removed.Type: GrantFiled: October 11, 2006Date of Patent: July 15, 2014Assignee: SemiLEDS Optoelectronics Co., Ltd.Inventors: Trung-Tri Doan, Chen-Fu Chu, Hao-Chun Cheng, Feng-Hsu Fan
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Patent number: 8778781Abstract: A method of growing a thin film comprises growing a thin film by conformally forming at least one layer over a substrate having structures extending from a surface of the substrate, whereby the or each layer is formed over the surface of the substrate and over the structures extending from the surface. The thickness of the conformal layer, or the sum of the thicknesses of the conformal layers, is at least half the average spacing of the structures, and; at least one of the height of the structures, the average spacing of the structures and the size of the smallest dimension of the structures is set so as to provide an enhanced growth rate for the or each conformal layer (compared to the growth rate over a planar substrate).Type: GrantFiled: July 24, 2009Date of Patent: July 15, 2014Assignee: Sharp Kabushiki KaishaInventors: Christian Lang, Ying Jun James Huang, Thomas Heinz-Helmut Altebaeumer, Stephen Day, Jonathan Heffernan
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Patent number: 8778782Abstract: A method for fabricating an electronic component, comprising providing a substrate; and depositing a graphene layer; wherein the substrate is either provided with a van-der-Waals functional layer or a van-der-Waals functional layer is deposited on the substrate before depositing the graphene layer; a surface step contour is formed; and growth of the graphene layer is seeded at the step contour.Type: GrantFiled: November 29, 2011Date of Patent: July 15, 2014Assignee: IHP GmbH—Innovations for High Performance MicroelectronicsInventors: Gunther Lippert, Jaroslaw Dabrowski, Grzegorz Lupina, Olaf Seifarth
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Patent number: 8778783Abstract: Methods are disclosed for growing high crystal quality group III-nitride epitaxial layers with advanced multiple buffer layer techniques. In an embodiment, a method includes forming group III-nitride buffer layers that contain aluminum on suitable substrate in a processing chamber of a hydride vapor phase epitaxy processing system. A hydrogen halide or halogen gas is flowing into the growth zone during deposition of buffer layers to suppress homogeneous particle formation. Some combinations of low temperature buffers that contain aluminum (e.g., AlN, AlGaN) and high temperature buffers that contain aluminum (e.g., AlN, AlGaN) may be used to improve crystal quality and morphology of subsequently grown group III-nitride epitaxial layers. The buffer may be deposited on the substrate, or on the surface of another buffer. The additional buffer layers may be added as interlayers in group III-nitride layers (e.g., GaN, AlGaN, AlN).Type: GrantFiled: May 10, 2012Date of Patent: July 15, 2014Assignee: Applied Materials, Inc.Inventors: Yuriy Melnik, Lu Chen, Hidehiro Kojiri
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Patent number: 8778784Abstract: Stress regulated semiconductor devices and associated methods are provided. In one aspect, for example, a stress regulated semiconductor device can include a semiconductor layer, a stress regulating interface layer including a carbon layer formed on the semiconductor layer, and a heat spreader coupled to the carbon layer opposite the semiconductor layer. The stress regulating interface layer is operable to reduce the coefficient of thermal expansion difference between the semiconductor layer and the heat spreader to less than or equal to about 10 ppm/° C.Type: GrantFiled: October 29, 2011Date of Patent: July 15, 2014Assignee: RiteDia CorporationInventors: Chien-Min Sung, Ming Chi Kan, Shao Chung Hu
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Patent number: 8778785Abstract: There is provided a process for forming a layer of electroactive material having a substantially flat profile. The process includes the steps of providing a workpiece having at least one active area; depositing a liquid composition including the electroactive material onto the workpiece in the active area, to form a wet layer; treating the wet layer on the workpiece at a controlled temperature in the range of ?25 to 80° C. and under a vacuum in the range of 10?6 to 1,000 Torr, for a first period of 1-100 minutes, to form a partially dried layer; and heating the partially dried layer to a temperature above 100° C. for a second period of 1-50 minutes to form a dried layer.Type: GrantFiled: May 15, 2009Date of Patent: July 15, 2014Assignee: E I du Pont de Nemours and CompanyInventors: Reid John Chesterfield, Nugent Truong, Jeffrey A. Merlo, Adam Fennimore, Jonathan M. Ziebarth
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Patent number: 8778786Abstract: Silicon loss prevention in a substrate during transistor device element manufacture is achieved by limiting a number of photoresist mask and chemical oxide layer stripping opportunities during the fabrication process. This can be achieved through the use of a protective layer that remains on the substrate during formation and stripping of photoresist masks used in identifying the implant areas into the substrate. In addition, undesirable reworking steps due to photoresist mask misalignment are eliminated or otherwise have no effect on consuming silicon from the substrate during fabrication of device elements. In this manner, device elements with the same operating characteristics and performance can be consistently made from lot to lot.Type: GrantFiled: May 29, 2012Date of Patent: July 15, 2014Assignee: SuVolta, Inc.Inventors: Lance Scudder, Pushkar Ranade, Dalong Zhao, Teymur Bakhishev, Urupattur C. Sridharan, Taiji Ema, Toshifumi Mori, Mitsuaki Hori, Junji Oh, Kazushi Fujita, Yasunobu Torii
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Patent number: 8778787Abstract: Methods of forming contacts for solar cells are described. In one embodiment, a method includes forming a silicon layer above a substrate, forming and patterning a solid-state p-type dopant source on the silicon layer, forming an n-type dopant source layer over exposed regions of the silicon layer and over a plurality of regions of the solid-state p-type dopant source, and heating the substrate to provide a plurality of n-type doped silicon regions among a plurality of p-type doped silicon regions.Type: GrantFiled: June 28, 2013Date of Patent: July 15, 2014Assignee: SunPower CorporationInventor: Jane Manning
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Patent number: 8778788Abstract: A semiconductor structure includes a III-nitride substrate with a first side and a second side opposing the first side. The III-nitride substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure also includes a III-nitride epitaxial structure including a first III-nitride epitaxial layer coupled to the first side of the III-nitride substrate and a plurality of III-nitride regions of a second conductivity type. The plurality of III-nitride regions have at least one III-nitride epitaxial region of the first conductivity type between each of the plurality of III-nitride regions. The semiconductor structure further includes a first metallic structure electrically coupled to one or more of the plurality of III-nitride regions and the at least one III-nitride epitaxial region. A Schottky contact is created between the first metallic structure and the at least one III-nitride epitaxial region.Type: GrantFiled: October 11, 2011Date of Patent: July 15, 2014Assignee: Avogy, Inc.Inventors: Andrew P. Edwards, Hui Nie, Isik C. Kizilyalli, Linda Romano, David P. Bour, Richard J. Brown, Thomas R. Prunty
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Patent number: 8778789Abstract: Methods for fabricating integrated circuits having low resistance metal gate structures are provided. One method includes forming a metal gate stack in a FET trench formed in a FET region. The metal gate stack is etched to form a recessed metal gate stack and a recess. The recess is defined by sidewalls in the FET region and is disposed above the recessed metal gate stack. A liner is formed overlying the sidewalls and the recessed metal gate stack and defines an inner cavity in the recess. A copper layer is formed overlying the liner and at least partially fills the inner cavity. The copper layer is etched to expose an upper portion of the liner while leaving a copper portion disposed in a bottom portion of the inner cavity. Copper is electrolessly deposited on the copper portion to fill a remaining portion of the inner cavity.Type: GrantFiled: November 30, 2012Date of Patent: July 15, 2014Assignee: GLOBALFOUNDRIES, Inc.Inventors: Paul R. Besser, Sean X. Lin, Valli Arunachalam